(Only representative publications have been included).
The first paper is included because the general purpose circuit simulator BITSIM ( built at VLSI Design centre, IIT Bombay in 1992) which used efficient, sparse hybrid equation formulation, was based on it. The remaining are largely on partitioning, dc-analysis and applications. The theory papers are based on Principal Lattice of Partitions and Principal Partition of a submodular function.
H. Narayanan, A theorem on graphs and its application to network analysis, Proceedings of IEEE International Symposium on Circuits and Systems (1979) 1008-1011
S. Roy and H. Narayanan, A new approach to the problem of PLA partitioning using the theory of the principal lattice of partitions of a submodular function, Proceedings of the Fourth Annual ASIC Conference and Exhibit (Rochester, 1991)
S. Patkar and H. Narayanan, Fast algorithm for the principal partition of a graph, Proceedings of Eleventh Annual Symposium on Foundations of Software Technology and Theoretical Computer Science (FSTTCS-11) LNCS-560 (1991) 288-306
H. Narayanan, S. Roy and S. Patkar, Min k-cut and the principal partition of a graph, Proceedings of Second National Seminar on Theoretical Computer Science (India, 1992)
V.S. Ovalekar and H. Narayanan, Fast loop matrix generation for hybrid analysis and a comparison of the sparsity of the loop impedance and MNA impedance submatrices, Proceedings of IEEE International Symposium on Circuits and Systems (1992)
S. Patkar and H. Narayanan, Principal lattice of partitions of submodular functions on graphs: Fast algorithm for principal partition and generic rigidity, Proceedings of the Third Annual International Symposium on Algorithms and Computation (Nagoya, Japan 1992)
S. Patkar and H. Narayanan, Fast sequential and randomized parallel algorithms for rigidity and approximate min-k-cut, Proceedings of Twelfth Annual Symposium on FSTTCS (New Delhi, 1992) (Springer Verlag, 1992)
S. Roy and H. Narayanan, Application of the principal partition and principal lattice of partitions of a graph to the problem of decomposition of a finite state machine, Proceedings of the IEEE International Symposium of Circuits and Systems (Chicago, Illinois, 1993)
H. Narayanan, S. Patkar and K.V. Subramanian, On the membership problem over polymatroid intersection, Proceedings of the Conference of the European Chapter on Combinatorial Optimization, (Milan, Italy 1994)
H. Narayanan, S. Roy and S. Patkar, Approximation algorithms for min-k-overlap using the PLP approach, Proceedings of the Conference on the Mathematical Foundations of Computer Science (Bratislava, Czech Republic, 1994)
S.Patkar, S.Batterywala, M.Chandramouli and H.Narayanan, A New Partitioning Strategy Based on Supermodular Functions, Proceedings of 10th International Conference on VLSI Design, Hyderabad, India, (1997) 32-37
Shabbir H. Batterywala and H. Narayanan, Time Domain Method for Reduced Order Network Synthesis of Large RC Circuits, The proceedings of the 1998 IEEE International Symposium on Circuits and Systems, VI-82-VI-85, Monterey, California, USA, 1998
Shabbir H. Batterywala and H. Narayanan, Efficient DC analysis of RVJ circuits for moment and derivative computations of interconnect networks, Proceedings of 12th international conference in VLSI design, Jan. 1999, 169-174
H.Narayanan B.N.V.M. Gupta and M.P.Desai, A state assignment scheme targeting performance and area, Proceedings of 12th international conference in VLSI design, Jan. 1999, 378-383
R.Shelar, M.P.Desai and H.Narayanan, Decomposition of Finite State Machines for Area, Delay minimization, Proceedings of the 1999 IEEE International Conference on Computer Design, Austin, Texas, USA
Shabbir H. Batterywala and H. Narayanan, Spectral Approximation Method for Choosing `Relevant' Eigenvalues During Interconnect Analysis, Proceedings of the 3rd World Multiconference on Systemics, Cybernetics and Informatics & the 5th International Conference on Information Systems, Analysis and Synthesis, Orlando, USA, September 1999
H.Narayanan, On the Duality between Controllability and Observability in Behavioural Systems Theory, Proc. International Conference on Communications Control and Signal Proc. CCSP 2000, Bangalore, July 25-July 28,2000, 183-186
R. Shelar, H. Narayanan and M. P. Desai, Orthogonal Partitioning and Gated Clock Architecture for Low Power Realization of FSMs, Proceedings of the 13th Annual IEEE International ASIC/SOC Conference, 13-16 Sept. 2000, Washington, 266-270
Sachin B. Patkar, H. Narayanan, Fast Algorithm for Successive Reinforcement of a Network, Proceedings of FSTTCS2000, New Delhi, December 2000
H.Narayanan, Matroids representable over Modules, Electrical Network Topology and Behavioural Systems Theory, Research report of the EE Dept., IIT Bombay, May 2000 (postscript).
H.Narayanan, Polyhedrally tight functions and convexity, Invited Talk, ISMP2003, Aug.18-Aug.22, 2003, Copenhagen, Denmark.
H.Narayanan: Mathematical Programming and Electrical Networks, {\it Proceedings of the International Conference on Operations Research 2004}, January 8-10,2004, ISI Kolkata
H.Narayanan,Mathematical Programming and Resistor Transformer Diode Networks, ICECS 2004, Dec 13-15, Tel Aviv, Israel, 2004, 69-72
S.Fujishige and H.Narayanan, Polyhedrally tight set functions and Discrete Convexity, Kurims (Kyoto University Research Institute of Mathematical Sciences) preprint, September 2005.
Gaurav Trivedi, Madhav P. Desai and H. Narayanan, “Fast DC Analysis and its Application to Combinatorial Optimization Problems”, 19th International Conference on VLSI Design,2006,pp 695-700
Gaurav Trivedi, Madhav P. Desai and H. Narayanan, Parallelization of DC Analysis through Multiport Decomposition, 20th International Conference on VLSI Design,2007,pp
Gaurav Trivedi, Sumit Punglia and H. Narayanan, Application of DC Analyzer to combinatorial optimization problems,20th International Conference on VLSI Design,2007,pp
H. Narayanan, Mathematical Programming and Electrical Network Analysis II: Computational Linear Algebra through Network analysis, International Symposium on Mathematical Programming for Decision Making: Theory and Applications (ISMPDM07), ISI Delhi, January 10-11, 2007.
G.Trivedi and H.Narayanan, Application of Fast DC Analysis to Partitioning Hypergraphs,ISCAS 2007 pp 3407-3410.
V. Siva Sankar, H. Narayanan, and Sachin B. Patkar, “Exploiting Hybrid Analysis in Solving Electrical Networks ”, 22nd International Conference on VLSI Design,2009, pp 2061