Department of Electrical Engineering
IIT Bombay

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Maryam Shojaei Baghini

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RESEARCH INTERESTS

Specific Knowledge can be applied to many application areas.

  • Technology-aware design (device circuit co-design); integrated circuits and system design with emerging devices
  • Analog/Mixed-signal VLSI design and test
    (SoC, LV, LP, LE, Biomedical/Biosensors, Bio-inspired circuits and systems, I/O, highly-precise circuits & systems, instrumentation, energy harvesting and many more applications)
  • Specific technologies and performance-optimized analog/mixed-signal/RF circuits & systems for healthcare applications
  • Integrated power management for SOC applications
  • High-speed data transmission and interconnects
  • Circuit and system modeling/optimization
  • Circuit and system design with organic thin film components
  • RF/Microwave integrated circuit design
  • Analog aspects of digital circuits
  • Sensor-Circuit Integration
  • Analog/Mixed-signal/RF EDA (CAD tools, theory and implementation)
  • VLSI design and embedded systems

COURSES OFFERED IN IIT-B

  1. EE204, Analog Circuits
  2. EE719, Mixed-Signal VLSI Design (Live EDUSAT course, record, broadcast and webcast by CDEEP IIT-B)
  3. EE618, Analog VLSI Design (record and webcast by CDEEP IIT-B)
  4. EE224, Digital Systems
  5. EE705, VLSI Design Lab (record and webcast by CDEEP IIT-B)
  6. Bridge course: Electronic Circuits
  7. EE214, Digital Circuits Lab
  8. EE232, Analog Electronics (Minor Course) (Live EDUSAT course, record and broadcast by CDEEP IIT-B)
  9. EE318, Electronic Design Lab
  10. Associate instructor for EE236, EDL Lab

Link to syllabus of all courses: http://www.ee.iitb.ac.in/web/academics/courses

RESEARCH LABS

  • VLSI Lab (Teaching and Research Lab)
  • Integrated Systems Lab (ISL)
  • Embedded Systems lab

ACADEMIC BACKGROUND

  • Post Doc. Research (Dept. of Electrical Engineering, IIT-Bombay)
  • Ph.D. and M.S., both in Electrical Engineering (Major: Electronics), Sharif Univ. of Technology
  • B. S., Electrical Engineering (Major: Electronics), S. B. Univ. of Kerman

WORK EXPERIENCE

  • Professor in E.E. Department of IIT-Bombay (at present)
  • Associate Professor in E.E. Department of IIT-Bombay
  • Assistant Professor in E.E. Department of IIT-Bombay
  • Member of team of designers for commercial chips in industry (all of the designs have been fabricated and tested successfully).

PH.D. STUDENTS

GRADUATED PH.D. STUDENTS

  1. Dr. Mahima Arrawatia (Graduated in 2016, Guides: M. Shojaei Baghini and Girish Kumar)
    Joined IIT-Jodhpur as Assitanst Professor.
  2. Dr. Tailor Ketan Harishbhai (Graduated in 2016, Guides: V. Rampgopal Rao and M. Shojaei Baghini)
    Joined Global Foundries, Singapore.
  3. Dr. Vinayak Hande (Graduated in 2015)
    Continued as Associate Researcher, IIT-Bombay and then joined IIT-Ropar as Assitanst Professor.
  4. Dr. Ankur Gupta (Graduated in 2015, Guides: M. Shojaei Baghini and V. Ramgopal Rao)
    Joined Global Foundries, Singapore.
  5. Dr. Marshnil V. Dave (Graduated in 2013, Guides: D. K. Sharma and M. Shojaei Baghini)
    Joined Marvell Semiconductor, USA.
  6. Dr. Ramesh R. Navan (Graduated in 2012, Guides: V. Rampgopal Rao and M. Shojaei Baghini)
    Joined TSMC, Taiwan.
  7. Dr. Angada B. Sachid (Graduated in 2010, Guides: V. Rampgopal Rao and M. Shojaei Baghini)
    Joined Post-Doctoral Research Program at Univ. of California, Berkeley, USA.
  8. Dr. Mayank Shrivastava (Graduated in 2010, Guides: V. Rampgopal Rao and M. Shojaei Baghini)
    Joined Intel Mobile Communications, Munich, Germany. Currently faculty member in IISc Bangalore.
  9. Dr. Rajesh Thakker (QIP, Graduated in 2009, Guides: M. B. Patil and M. Shojaei Baghini)
    Rejoined as Professor, EC Department, V.G.E.C., Chandkheda, Ahmedabad, India.

PH.D. STUDENTS WHO HAVE SUBMITTED THE PRE-SYNOPSIS OR THESIS

  1. S. Gandhi (submitted the thesis) (Guides: Soumyo Mukherjee and M. Shojaei Baghini)
  2. N. A. Gilda (submitted the thesis) (Guides: V. Ramgopal Rao and M. Shojaei Baghini)
  3. M. Bakshi (submitted the pre-synopsis) (Guides: V. R. Sule and M. Shojaei Baghini)
  4. P. S. Swain (submitted the thesis) (Guides: M. Shojaei Baghini and V. Rampgopal Rao)
    Joined Maxim Integrated - India.

CURRENT PH.D. STUDENTS (IN ALPHABETICAL ORDER)

  1. M. Ahmad
  2. S. Agrawal (Guides: Soumyo Mukherjee and M. Shojaei Baghini)
  3. S. Boyapati (Guides: M. Shojaei Baghini and Jean-Michel Redoute (Monash University, Australia))
  4. D. M. Das
  5. H. S. Gupta (Guides: D. K. Sharma and M. Shojaei Baghini)
  6. J. John (Guides: M. Shojaei Baghini and G. Kasbekar)
  7. N. Kadayinti (Guides: M. Shojaei Baghini and D. K. Sharma)
  8. V. S. Palaparthy (Guides: M. Shojaei Baghini and D. N. Singh)
  9. G. M. Rajan (Guides: M. Shojaei Baghini and G. Pendharkar (RMIT, Monash University, Australia))
  10. T G. Rao (Guides: M. Shojaei Baghini and D. K. Sharma)
  11. S. Roymohapatra (Guides: M. Shojaei Baghini and M. B. Patil)
  12. G. Saini
  13. S. Sivaneswaran
  14. A. Srivastava

GRADUATED MTECH/DD STUDENTS

  • Supervision of 88 completed M.Tech./D.D. projects (from 2006)
  • Graduated students joined (as per alphabetical order) AMCC-India, Analog Devices-India, Broadcom-India, Cadence-India, Cypress-India, Consultancy firms in India and outside India, Cosmic Circuits, GlobalFoundries-India, IBM-India, Intel-India, Maxim India Integrated Circuit Design, NXP-India, Philips-India, Qualcomm-India, Rambus-India, Samsung-India, Sandisk-India, Seagate-India, Startups, Sysco-India, Sysmex Japan, Tata Technologies, Techtronics, TI-India, TS-India and TSMC Taiwan/ or pursuing higher education.

RESEARCH PROJECTS

COMPLETED RESEARCH PROJECTS (14)

  • 1 Completed research project funded by industry in 2016.
  • 1 Completed research project funded by WRCB in 2016.
  • 1 Completed research project sponsored by DST Government of India (jointly with G. Kumar) and 2 Completed research project with industry in 2015.
  • 4 Completed research projects in 2013: Sponsored by DST Government of India (jointly with G. Kumar), NCPRE MNRE Government of India (jointly with S. Ganguly), IRCC_IIT-Bombay and industry.
  • 1 Completed research project with industry in 2012.
  • Contributed to 1 completed research project under INUP in 2011.
  • 2 research projects with industry and 1 interuniversity research project ended in 2010.

ON-GOING RESEARCH PROJECTS (7)

  • MeitY funded research
    (1 individual project and 2 joint projects with V. R. Rao, D. K. Sharma, M. P. Desai and D. N. Singh)
  • DST funded research
    (2 projects: Joint research with V. R. Rao, C. Subramanyam and T. Kundu)
  • Industry funded research under IITB-industry collaborations
    (1 individual project, 1 joint project with V. R. Rao)

TEST CHIPS IN IIT-BOMBAY (FABRICATED AND SUCCESSFULLY TESTED)

  1. Test chip: Ultra low temperature compensated bidirectional current source (V. G. Hande, N. Gilda, M. Shojaei Baghini)
  2. Test chip: 100MHz-500MHz VCO (P. Aravind, K. Singh, M. Shojaei Baghini)
  3. Two different RF Power Amplifier Test Chips (World's First Reported RF PAs in 28nm CMOS Technology) (A. Gupta, M. Shrivastava, M. Shojaei Baghini, H. Gossner, D. K. Sharma, V. R. Rao)
  4. Test chip: Wireless Transmitter for Biomedical Applications (B. Chatterjee, A. Shrivastava, J. Ananthapadmanabhan, V. Saraf, M. Shojaei Baghini, D. K. Sharma)
  5. Test chip: Current-Mode INA (D. M. Das., M. Shojaei Baghini)
  6. Test chip: A Fully On-chip PT-Invariant Transconductor (Anvesha A., M. Shojaei Baghini)
  7. Test chip: ULP PV-invariant PTAT current source (Anvesha A., M. Shojaei Baghini)
  8. Test chip CMS3: LP, PVT-compensated high-speed CM signaling (Marshnil V. Dave, M. Shojaei Baghini, Dinesh K. Sharma)
  9. Test chip SC_IITB_2: Ultra Low-Noise ULP INA and Buffer, Rail-to-Rail Active Filter Stage and RLD Modules for Biomedical and Sensor Applications (Sanjay Joshi, Viral Thaker, Mugdha Nazre, M. Shojaei Baghini (with special thanks to Marshnil V. Dave))
  10. Test chip CMS2: Uni/Bi-directional LP, PVT-compensated high-speed CM signaling (Marshnil V. Dave, M. Shojaei Baghini, Dinesh K. Sharma)
  11. Test chip: Linear Delay Element (Achal Venkatesh, M. Shojaei Baghini)
  12. Test chip: HS comparator and offset compensation circuit (Santosh K. Gowdhaman, M. Shojaei Baghini (with special thanks to Marshnil V. Dave))
  13. Test chip CMS1: Unidirectional LP HS CM signaling (Marshnil V. Dave, M. Shojaei Baghini, Dinesh K. Sharma)
  14. Test chip SC_IITB_1: (M. Shojaei Baghini, Rakesh K. Lal, Dinesh K. Sharma) (INA module in SC_IITB_1 had minimum PD compared to already-reported IAs). Test chip SC_IITB_1 was fabricated, tested and used as a complete signal conditioning chip for simultaneous three-lead ECG recording as a part of SiLoc project (Internal link to SiLoc project and team members: http://sharada.ee.iitb.ac.in/~siloc/).

DEVICE FABRICATION AND CHARACTERIZATION IN IIT-BOMBAY

- MIM tunnel diodes (Yaksh D. Rawal, Swaroop Ganguly and M. Shojaei Baghini) (2011-2013)

- Memristors (Mohit Pimpalkar (DD, graduated in 2012), Ashish Kumar (intern 2012), Yaksh D. Rawal, M. Shojaei Baghini)

AWARDS

  1. Impactful Research Award, IIT-Bombay (2015)
  2. Joint-recipient of the Richard Feynman Prize for the best paper, ICE (UK) Journal of Emerging Materials Research (2013).
  3. Project guide and joint-recipient of the first place award all over India in Cadence Design Contest-India (two consecutive years 2012, 2011).
  4. Project guide for one of the finalist projects in international chip design competition in ISIC, Singapore (2011).
  5. Project guide and joint-recipient of the first place award in Anveshan Design Contest held by Analog Devices-India all over India (Healthcare category), 2010-2011
  6. Joint-recipient of the best paper award, IEEE ISVLSI Symposium, India (2011).
  7. Project guide and joint-recipient of the runner up award all over India in Cadence Design Contest-India (2010).
  8. Joint-recipient of IIT-Bombay Industry Impact Award (2008).
  9. Joint-recipient of the best research award in the Circuit Design Category, Intel Corporation AAF, Taiwan (2008).
  10. Guide for the winner project of the first Cadence Student Design Contest among SAARC countries (2006).
  11. Joint-recipient of the third award on Research and Development in 15th international festival of Kharazmi (2002).

MY STUDENTS' AWARDS

=== ==== ===== 1. ===== ==== ===

Akshay Adlakha (M.Tech., graduated in 2016)
* Excellence Award among all M.Tech students in E. E. Department IIT-Bombay, 2016.
* Institute Silver Medal in 54th Convocation ceremony of IIT-Bombay, 2016.
* Ajit Shelat Award , E. E. Department IIT-Bombay, 2016.

=== ==== ===== 2. ===== ==== ===

Ashish Behra (M.Tech., graduated in 2016) and his teammates
* One of top finalists in GE Edison Challenge, all over India, 2016.
* First prize winner of Aavriti , IIT-Bombay, 2016.

=== ==== ===== 3. ===== ==== ===

Baibhab Chaterjee (M.Tech., graduated in 2015)
* Silver Medalist, E.E. Department, IIT-Bombay, M.Tech. batch (graduated in 2015) among 138 students.

=== ==== ===== 4. ===== ==== ===

Neeraj Babu C (M.Tech., graduated in 2015) and his teammates Apurv Mittal, Riyaz Mohammed A, Anjaly T R and Vineesh V S (M. Tech., graduated in 2015)
* Winner of Anveshan Design Contest and Fellowship Program held by Analog Devices, all over India , 2015.
* One of the 3 winning teams of ERICSSON Innovation Award , all over India , 2015.

=== ==== ===== 5. ===== ==== ===

Vinay Palaparthy (Ph.D. scholar, guides: M. Shojaei Baghini and D. N. Singh)
* Joint Recipient of Richard Feynman Prize in 2014, ICE (Institute of Civil Engineers), UK for the best paper published in ICE Journal of Emerging Materials Research in 2013.

=== ==== ===== 6. ===== ==== ===

Dr. Marshnil Dave (Ph.D., Graduated in 2013, Guides: Dinesh K. Sharma and M. Shojaei Baghini)
* IESA Techno Inventor Award, India, 2013.

=== ==== ===== 7. ===== ==== ===

Priyanka Kabara (M.Tech., Graduated in 2012) and Sanket Thakur (Intern, 2011)
* First place in Design Contest in International Conf. on VLSI Design, India, 2013.
* First place in Cadence Design Contest (Master project category), all over India, 2012.
* One of finalist teams in Student Project Contest in International Conference on VLSI Design, India, 2012.

=== ==== ===== 8. ===== ==== ===

Anvesha Amaravati (M.Tech., Graduated in 2012)
* First place in Student Project Contest in International Conference on VLSI Design , India, 2012.
* First place in Cadence Design Contest (Master project category), all over India, 2011.
Anvesha Amaravati and Deepesh Kamani
* First place in Anveshan Design Contest and Fellowship Program held by Analog Devices (healthcare category), all over India , 2010-2011.

=== ==== ===== 9. ===== ==== ===

Vineeth Anavangot (M.Tech., Graduated in 2012)
* Winner of the second prize in Nebula'11 by Cosmic Circuits, all over India.

=== ==== ===== 10. ===== ==== ===

Ani Xavier (M.Tech., Graduated in 2012)
* One of finalists in Nebula'11 by Cosmic Circuits, all over India.

=== ==== ===== 11. ===== ==== ===

Sanjay Joshi and Viral P. Thaker (M.Tech., Graduated in 2011)
* One of finalist teams in international chip design competition in ISIC-2011, Singapore.
* Runner up place all over India in Cadence-India design contest (Master project category), all over India, 2010).

=== ==== ===== 12. ===== ==== ===

Dr. Aangada B. Sachid (Ph.D., Graduated in 2010, Guides: V. Rampgopal Rao and M. Shojaei Baghini)
* Best Ph.D. thesis award, E.E. Department, IIT-Bombay, 2011.
* The best TA award in EE Dept., IIT-Bombay in 2008.
* Co-recipient of the best research award in the Circuit Design Category, Intel Corporation AAF, Taiwan (2008).

=== ==== ===== 13. ===== ==== ===

Naveen K. Kancharapu (M.Tech., Graduated in 2011, Guides: M. Shojaei Baghini and Dinesh K. Sharma)
Best Paper Award in IEEE ISVLSI Symposium, 2011, India
Naveen K. Kancharapu, Marshnil V. Dave, Veerraju Masimukkula, M. Shojaei Baghini, Dinesh K. Sharma

=== ==== ===== 14. ===== ==== ===

Dr. Mayank Shrivastava (Ph.D., Graduated in 2010, Guides: V. Rampgopal Rao and M. Shojaei Baghini)
* Ph.D. Excellence Thesis Work, E. E. Department, IIT-Bombay, 2010.
* Dr. Mayank Srivastava has been awarded as one of the finalists of the first India TR35 list, 2010.
* He's also listed in “2000 Outstanding Intellectuals of the 21st Century-2010”-
Biography publication by International Biographical Center (IBC), Cambridge, England.
* Co-recipient of the best research award in the circuit design category, Intel Corporation AAF, Taiwan (2008).

=== ==== ===== 15. ===== ==== ===

Santosh K. Gowdhaman (M.Tech., Graduated in 2010)
* Winner of the third prize in Nebula'09 by Cosmic Circuits, all over India.

=== ==== ===== 16. ===== ==== ===

Dr. Rajesh Thakker (Ph.D., Graduated in 2009, Guides: M. B. Patil and M. Shojaei Baghini))
* Co-recipient of the best research award in the Circuit Design Category, Intel Corporation AAF, Taiwan (2008).

MORE TECHNICAL ACTIVITIES

  1. Invited member of editorial board, Scientia Iranica, Transactions D: Computer Science & Engineering and Electrical Engineering http://www.scientiairanica.com/en
  2. Chair, focus area of NEMS & Sensors, and Exhibition & Sponsorship, ICEE 2016 http://www.iceeconf.org
  3. Invited TPC member, Emerging Applications and Technologies sub-committee, IEEE A-SSCC
    (Sister conference of IEEE ISSCC)http://www.a-sscc2014.org/ (2009-2014)
  4. Invited TPC member and Design Contest Chair, Int. Conf. on VLSI Design
    (Sister conference of IEEE DAC)http://www.vlsiconference.com/ (2004-2016)
  5. Invited technical chair, (Signal Processing and VLSI track), IEEE INDICON http://www.indicon2013.org
  6. Invited track chair (Analog and Mixed-Signal System Design) and TPC member, IEEE ISED http://ised.seedsnet.org/ 2016 and (2011-2013)
  7. Invited TPC member, IEEE ISVLSI Conference http://www.isvlsi.org/
  8. Invited TPC member, Circuit and System Design, IEDEC and ISQED Conference) http://www.isqed.org/ , http://www.iedec.org/
  9. Invited TPC member (circuit and system design track), ASQED Conference http://www.asqed.com/
  10. Invited TPC member, Nanoelectronics Track, IEEE ICM Conference http://www.ieee-icm.com/
  11. Senior Member of IEEE
  12. Invited lectures and talks (total: 34)
  13. Reviewer: Journals and conferences (IEEE, IET, Elsevier, IETE, Sadhana-Springer, American Scientific Publishers and other technical societies/publishers)

PUBLICATIONS (BOOKS)

  • Chapter title: Anodic MIM Capacitors
    by D. Kannadasan, P. S. Mallick and M. Shojaei Baghini
    in Nano-CMOS and Post-CMOS Electronics: Devices and Modelling, Edited by S. P. Mohanty and A. Srivastava
    The Institute of Engineering and Technology (IET), 2016
  • Monograph Title: Applications of Evolutionary Algorithms in VLSI
    by R. Thakker, M. B. Patil and M. Shojaei Baghini
    Publisher: LAMBERT Academic Publishing, ISBN 978-3-8454-0434-9, 2010
  • Invited Chapter Title: Hardware Development of Wearable ECG Devices
    by M. Shojaei Baghini, D. K. Sharma, R. K. Lal
    Monograph Title: Ambulation Analysis in Wearable ECG by S. Chaudhuri, T. Pawar, S. P. Duttagupta
    Publisher: Springer, ISBN: 978-1-4419-0723-3, August 2009

PATENTS

Granted patents

  1. US Patent US 9,136,831, “Frequency to Voltage Converter”, G. S. Kumar, M. Shojaei Baghini, A. Vineeth, J. Mukherjee, Issue date: September 2015.

  2. US Patent US 8,610,616, “Successive Approximation Register Analog to Digital Converter Circuit”, M. Shojaei Baghini, V. G. Hande, Issue date: December 2013.

  3. US Patent US 8,455,947, “Device and Method for Coupling First and Second Device Portions”, M. Shrivastava, C. C. lluss, H. Gossner, V. Ramgopal Rao, M. Shojaei Baghini, Issue date: June 2013.

  4. Indian Patent 258773 and US Patent US 8,436,413, “Nonvolatile Floating Gate Analog Memory Cell”, M. Shrivastava, M. Shojaei Baghini, D, K. Sharma, V. Ramgopal Rao, Issue dates: October 2008 and May 2013, respectively.

  5. US Patent US 8,354,710, “Field-Effect Device and Manufacturing Method Thereof”, M. Shrivastava, H. Gossner, V. Ramgopal Rao, M. Shojaei Baghini, Issue date: January 2013.

  6. US Patent US 8,097,930, “Semiconductor Devices with Trench Isolations”, M. Shrivastava, H. Gossner, V. Ramgopal Rao, M. Shojaei Baghini, Issue date: January 2012.

  7. US Patent US 8,089,314, “Operational Amplifier Having Improved Slew Rate”, R. A. Thakker, M. Shrivastava, M. Shojaei Baghini, D. K. Sharma, Ramgopal V. Rao, M. B. Patil, Issue date: January 2012.

Filed Patent Applications

- Inventor/co-inventor of 35 more filed patent applications.

PUBLICATIONS (57 JOURNAL PAPERS and 115 CONFERENCE PAPERS)

2017

  1. A. Srivastava, N. Sankar, D. M. Das and M. Shojaei Baghini, “LNA-LO Co-Design Considerations For Low Intermediate Frequency Receivers In 401-406 MHz MedRadio Spectrum For Healthcare Applications”, Accepted in International Conf. on VLSI Design, 2017, India.

  2. N. Kadayinti, M. Shojaei Baghini and D. K. Sharma, “A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects”, Accepted in International Conf. on VLSI Design, 2017, India.

2016

  1. “Application of Heat of Wetting for Determination of Soil-Specific Characteristics of Fine-Grained Soils”, S. Kadali, S. U. Susha Lekshmi, D. N. Singh, and M. Shojaei Baghini, ASTM Journal of Testing and Evaluation, November 2016.

  2. “A Critical Analysis of the Performance of Plate- and Point-electrodes for Determination of Electrical Properties of the Soil Mass”, S.U. S. Lekshmi, P. N.V. Jayanthi, P. Aravind, D.N. Singh, M. Shojaei Baghini, Elsevier Measurement Journal, November 2016.

  3. “Modelling and Design of EMI Immune OpAmps in 0.18 um CMOS Technology”, S. Boyapati, Jean-Michel Redoute and M. Shojaei Baghini, IEEE Transactions on Electromagnetic Compatibility, October 2016.

  4. “Graphene Quantum Dot Soil Moisture Sensor”, H. Kalita,V. S Palaparthy, M. Shojaei Baghini and M. Aslam, Elsevier Sensors & Actuators: B. Chemical, October 2016.

  5. “Robust Soft Error Tolerant CMOS Latch Configurations”, A. Kumar Pudi N S and M. Shojaei Baghini, IEEE Transactions on Computers, September 2016.

  6. “A novel low-noise fully differential CMOS instrumentation amplifier with 1.88 noise efficiency factor for biomedical and sensor applications”, D. M. Das, Ananthapadmanabhan J., M. Ahmad and M. Shojaei Baghini, Elsevier Microelectronics Journal (one of the most downloaded papers in 2016), July 2016.

  7. “On the Improved High-Frequency Linearity of Drain Extended MOS Devices”, A. Gupta, M. Shrivastava, M. Shojaei Baghini, D. K. Sharma, H. Gossner and V. Ramgopal Rao, Accepted for publication in IEEE Microwave and Wireless Components Letters, 2016.

  8. “On the Geometrically Dependent Quasi-saturation and gm Reduction in Advanced DeMOS Transistors”, P. S. Swain, M. Shrivastava, M. Shojaei Baghini, H. Gossner and V. Ramgopal Rao“, IEEE Transactions on Electron Devices, April 2016.

  9. “Low Power, Area Efficient,and Temperature-Variation Tolerant Bidirectional Current Source for Sensor Applications”, N. A. Gilda, V. G. Hande, D. K. Sharma, V. Ramgopal Rao and M. Shojaei Baghini, Elsevier Microelectronics Journal, March 2016. (DOI: http://dx.doi.org/doi:10.1016/j.mejo.2015.12.010)

  10. “Broadband Bent Triangular Omnidirectional Antenna for RF Energy Harvesting”, M. Arrawatia, M. Shojaei Baghini, Girish Kumar, IEEE Antennas and Wireless Propagation Letters, February 2016. (DOI: http://dx.doi.org/doi:10.1109/LAWP.2015.2427232)

  11. “A Methodology to Determine Thermal Conductivity of Soils from Flux Measurement”, S. Mondal, G. P. Padmakumar, V. Sharma, D. N. Singh, and M. Shojaei Baghini Taylor & Francis Geomechanics and Geoengineering: An International Journal, Issue 1 2016.

  12. A. Srivastava, D. M. Das, Vignesh M S, Bharadwaj K., S. Dewan and M. Shojaei Baghini, “Bio-Telemetry And Bio-Instrumentation Technologies For Health Care Monitoring Systems”, Accepted in IEEE HTC, 2016, India.

  13. S. Boyapati, Jean-Michel Redoute and M. Shojaei Baghini, “A Highly EMI Immune Folded Cascode OpAmp in 0.18 μm CMOS Technology”, Proc. of EMC Europe (one of the eight selected nominees for the best student paper award) 2016, Poland.

  14. N. Sankar K, A. Srivastava, B. Chatterjee, Rakesh K K and M. Shojaei Baghini,”FSK Demodulator and FPGA Based BER Measurement System For Low IF Receivers“, Proc. of VDAT 2016, India.

  15. S. Sarkar, G. Saini, M. Arrawatia and M. Shojaei Baghini, “Optimal Design Flow of CMOS Doubler-based Rectifiers”, Proc. of VDAT 2016, India.

  16. A. Srivastava, N. Sankar K, Rakesh K K, B. Chatterjee, D. M. Das and M. Shojaei Baghini, “Design and Measurement Techniques for a Low Noise Amplifier in a Receiver Chain for MedRadio Spectrum Of 401-406 MHz Frequency Band”, Proc. of VDAT 2016, India.

  17. P. Kimtee, D. M. Das and M. Shojaei Baghini, “A Mismatch Insensitive Reconfigurable Discrete Time Biosignal Conditioning Circuit in 180 nm MM CMOS Technology”, Proc. of VDAT 2016, India.

  18. P. Verma, R. Halba, H. Patel and M. Shojaei Baghini, “On-chip Delay Measurement Circuit for Reliability Characterization of SRAM”, Proc. of IEEE ISVLSI 2016, USA.

  19. A. Srivastava, D. M. Das, D. K. Sharma and M. Shojaei Baghini, “SAW Resonator Oscillator Based Injection Locked OOK Transmitter for MedRadio Spectrum”, Proc. of IEEE NEWCAS 2016, Canada.

  20. G. Saini, S. Sarkar, M. Arrawatia and M. Shojaei Baghini, “Efficient Power Management Circuit for RF Energy Harvesting with 74.27% Efficiency at 623nW Available Power”, Proc. of IEEE NEWCAS 2016, Canada.

  21. P. S. Swain, M. Shrivastava, M. Shojaei Baghini, H. Gossner, V. R. Rao, “Device-Circuit Co-design for High Performance Level Shifter by Limiting Quasi-saturation Effects in Advanced DeMOS Transistors”, Proc. of IEEE INEC 2016, China.

  22. M. Arrawatia, M. Shojaei Baghini and Girish Kumar,”Broadband Rectenna Array for RF Energy Harvesting“, Accepted in IEEE APS/URSI 2016, Puerto Rico.

  23. M. Arrawatia, M. Shojaei Baghini and Girish Kumar,”Broadband RF Energy Harvesting System covering CDMA, GSM900, GSM1800, 3G Bands with Inherent Impedance Matching“, Proc. of IEEE IMS 2016, USA.

  24. A. Gupta, M. Shrivastava, M. Shojaei Baghini, H. Gossner, V. R. Rao, “A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology mounted in BGA Package”, Proc. of International Conf. on VLSI Design, (Sister Conf. of IEEE DAC, DATE and ICCAD) 2016, India.

2015

  1. “Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device”, K. Tailor, M. Shrivastava, H. Gossner, M. Shojaei Baghini and V. Ramgopal Rao, IEEE Transactions on Electron Devices, December 2015.

  2. “Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain Extended PMOS Device”, K. Tailor, M. Shrivastava, H. Gossner, M. Shojaei Baghini and V. Ramgopal Rao, IEEE Transactions on Electron Devices, December 2015.

  3. “Part II: A Fully Integrated RF PA in 28nm CMOS with Device Design for Optimized Performance and ESD Robustness”, A. Gupta, M. Shrivastava, M. Shojaei Baghini, A. N. Chandorkar, H. Gossner and V. Ramgopal Rao, IEEE Transactions on Electron Devices, October 2015.

  4. “Part I: High Voltage MOS Device Design for Improved Static and RF Performance”, A. Gupta, M. Shrivastava, M. Shojaei Baghini, D. K. Sharma, H. Gossner and V. Ramgopal Rao, IEEE Transactions on Electron Devices, October 2015.

  5. “A Low-Power, Low-Cost Soil-Moisture Sensor Using Dual-Probe Heat-Pulse Technique”, N. Jorapur, V. S Palaparthy, S. Sarik, J. John, M. Shojaei Bhagini and G. K. Ananthasuresh, Elseveir Sensors & Actuators: A. Physical, September 2015.

  6. “A Fully On-chip PT-Invariant Transconductor”, Anvesha A, M. V. Dave, M. Shojaei Baghini, D. K. Sharma, IEEE Transactions on VLSI Systems, September 2015.

  7. “An Inherent Curvature-Compensated Voltage Reference Using Non-linearity of Gate Coupling Coefficient”, V. G. Hande, M. Shojaei Baghini, IOP Science, Journal of Semiconductors, August 2015.

  8. “Differential Microstrip Antenna for RF Energy Harvesting”, M. Arrawatia, M. Shojaei Baghini, Girish Kumar, IEEE Transactions on Antennas and Propagation, April 2015 (One of the most downloaded articles from IEEE Transactions on Antennas and Propagation in 2015).

  9. N. Modak, B. Chatterjee and M. Shojaei Baghini, “A 120 nW, Tunable, PVT Invariant Voltage Reference with 80 dB Supply Noise Rejection”, Proc. of IEEE iNIS, 2015, India.

  10. P. Aravind, M. Gurav, A. Mehta, R. Shelar, J. John, V. S. Palaparthy, K. K. Singh, S. Sarik, M. Shojaei Baghini, “A Wireless Multi-Sensor System for Soil Moisture Measurement”, Proc. of IEEE Sensors Conference, 2015, South Korea.

  11. V. S. Palaparthy, S. Sarik, A. Mehta, K. K. Singh, M. Shojaei Baghini, “An Automated, Self Sustained Soil Moisture Measurement System using Low Power Dual Probe Heat Pulse (DPHP) Sensor ”, Proc. of IEEE Sensors Conference, 2015, South Korea.

  12. S. Gandhi, M. Shojaei Baghini, Soumyo Mukherji, “Mental Stress Measurement ‐ A Comparison Between HRV based and Respiration Based Technique”, Proc. of CinC, 2015, France.

  13. G. Saini, M. Arrawatia, S. Sarkar and M. Shojaei Baghini, “A Battery-Less Power Management Circuit for RF Energy Harvesting with Input Voltage Regulation and Synchronous Rectification”, Proc. of IEEE MWSCAS, 2015, USA.

  14. M. Arrawatia, M. Shojaei Baghini and Girish Kumar, “A CMOS Power Amplifier with 180 Degree Hybrid On-Chip Coupler for 4G Applications”, Proc. of IEEE MWSCAS, 2015, USA.

  15. M. Arrawatia, M. Shojaei Baghini and Girish Kumar, “Dual Band Dual Polarized Bidirectional Horse Shoe Shape Antenna”, Proc. of IEEE ISAP, 2015, Canada.

  16. A. Srivastava, B. Chatterjee, Vineeth A., and M. Shojaei Baghini, “A Novel FM/FSK Based Receiver Front-End for MedRadio Spectrum in 401-406 MHz Band”, Proc. of IEEE ISCAS, 2015, Portugal.

  17. P. S. Sengar, M. Shojaei Baghini and D. N. Singh, “Implementation of a System for Measuring Velocity of Primary & Secondary Waves in Rocks and Soils”, Proc. of IEEE SoutheastCon 2015, 2015, USA.

  18. J. John, V. S Palaparthy, S. Sarik, M. Shojaei Baghini, G. S Kasbekar, “Design and Implementation of a Soil Moisture Wireless Sensor Network”, Proc. of NCC, 2015, India.

  19. M. Gurav, S. Sarik, M. Shojaei Baghini, “Time Extraction Method for Time Domain Reflectometry Measurements”, Proc. of IEEE SAS, 2015, Croatia.

  20. G. Rao Talluri, Rakesh K K, M. Shojaei Baghini, “A 4-14 Gbps Inductor-Less Adaptive Linear Equalizer Using Hybrid Filter in 65 nm CMOS Technology”, Proc. of IEEE ISQED, 2015, USA.

  21. K. Tailor, M. Shrivastava, H. Gossner, M. Shojaei Baghini, V. R. Rao, “Comparison of Breakdown Characteristics of DeNMOS Devices with Various Drain Structures”, Proc. of IEEE EDSSC, 2015, Singapore.

  22. K. Tailor, M. Shrivastava, H. Gossner, M. Shojaei Baghini, V. R. Rao, “On the Breakdown Physics of Trench-Gate Drain Extended NMOS”, Proc. of IEEE EDSSC, 2015, Singapore.

2014

  1. “Experimental Study for Selection of the Electrode Material for ZnO Based Memristor”, A. Kumar and M. Shojaei Baghini, IET Electronics Letters, October 2014.
    (DOI: http://dx.doi.org/10.1049/el.2014.1491)

  2. “An Ultra-sensitive Piezoresistive Polymer Nano-Composite Microcantilever Platform for Humidity and Soil Moisture Detection”, S. J. Patil, A. Adhikari, M. Shojaei Baghini, V. Ramgopal Rao, Elsevier Sensors & Actuators B: Chemical, November 2014.
    (DOI: http://dx.doi.org/10.1016/j.snb.2014.06.110)

  3. “A Critical Review of Soil Moisture Measurement”, SushaLekshmi S. U., D. N. Singh and M. Shojaei Baghini, Elsevier Measurement Journal, May 2014, (One of the most downloaded measurement articles from Elsevier ScienceDirect in 2015).
    (DOI:http://dx.doi.org/10.1016/j.measurement.2014.04.007)

  4. “Modeling the Voltage Nonlinearity of High-k MIM capacitors”, D. Kannadassan, R. Karthik, M. Shojaei Baghini and P. S. Mallick, Elsevier Solid State Electronics, January 2014.

  5. D. M. Das, J Ananthapadmanabhan, M. Shojaei Baghini, D. K. Sharma, “Design Considerations for High-CMRR Low-Power Current Mode Instrumentation Amplifier for Biomedical Data Acquisition Systems”, Proc. of IEEE ICECS, 2014, France.
    DOI: http://dx.doi.org/10.1109/ICECS.2014.7049969

  6. S. Gandhi, L. Jain, J. Jain, M. Shojaei Baghini, S. Mukherji, “Evaluation of Heart Rate As a Marker for Psychological Stress”, Proc. of IEEE EMBC, 2014, USA.

  7. H. S. Gupta, A. S. K. Kumar, M. Shojaei Baghini, S. Chakrabarti, S. Paul, S. Mehta, R. S. Chaurasia, A. R. Chowdhury, D. K. Sharma, “Implementation of High Performance Read out Integrated Circuit”, Proc. of IEEE MWSCAS, 2014, USA.

  8. H. S. Gupta, A. S. K. Kumar, M. Shojaei Baghini, S. Chakrabarti, S. Paul, S. Mehta, R. S. Chaurasia,A. R. Chowdhury, D. K. Sharma, “Efficient Implementation of High Performance Read out Integrated Circuit”, Proc. of IEEE EDSSC, 2014, China.

  9. S. Boyapati, D. M. Das, M. Shojaei Baghini and J. M. Redoute, “A Balanced CMOS OpAmp with High EMI Immunity”, Proc. of EMC Europe, 2014, Sweden.

  10. V. G. Hande and M. Shojaei Baghini, “Trimless, PVT Insensitive Voltage Reference using Compensation of Beta and Thermal Voltage”, Proc. of International Conf. on VLSID, 2014, (Sister Conf. of IEEE DAC, DATE and ICCAD), India.

  11. A. Gupta, M. Shrivastava, M. Shojaei Baghini, D. K. Sharma, A. N. Chandorkar, H. Gossner and V. Ramgopal Rao, “Drain Extended MOS Device Design for Integrated RF PA in 28nm CMOS with Excellent FoM and ESD Robustness”, Proc. of IEEE IEDM, 2014, USA.

  12. Y. Rawal, D. Burman, P. P. Manik, P. Bhatt, Anoop C., S. Lodha, S. Ganguly, M. Shojaei Baghini, “Performance Comparison of MIM and MIS Diodes for Energy Harvesting Applications”, Proc. of IEEE EDSSC, 2014, China.

2013

  1. “Device-Circuit Co-Design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors”, P. Swain, M. Shrivastava, H. Gossner, M. Shojaei Baghini, IEEE Transactions on Electron Devices, November 2013.
    (DOI: http://dx.doi.org/10.1109/TED.2013.2283421)

  2. “Nanostructured Bilayer Anodic TiO2/Al2O3 Metal-Insulator-Metal Capacitor”, R. Karthik, D. Kannadassan, M. Shojaei Baghini, P. S. Mallick, Journal of Nanoscience and Nanotechnology, American Scientific Publishers, October 2013.

  3. “Review of Polymer-Based Sensors for Agriculture-Related Applications”, V. S. Palaparthy, M. Shojaei Baghini, D. N. Singh, ICE Emerging Materials Research , August 2013 (Awarded Richard Feynman Prize for the best paper published in this journal in 2013). (DOI: http://dx.doi.org/10.1680/emr.13.00010)

  4. “Nanostructured Metal-Insulator-Metal Capacitor with Anodic Titania”, D. Kannadassan, R. Karthik, M. Shojaei Baghini, P. S. Mallick, Elsevier Materials Science in Semiconductor Processing, April 2013.

  5. “Effect of Electrolyte on the Performance of Anodic Titania Metal-Insulator-Metal Capacitors”, R. Karthik, D. Kannadassan, M. Shojaei Baghini, P. S. Mallick, Journal of Nanoelectronics and Optoelectronics, American Scientific Publishers, March 2013.

  6. “A Versatile High Swing Current Mode Instrumentation Amplifier with an Integrated Band-pass Filter for Bio-potential Signal Acquisition”, Anvesha A and M. Shojaei Baghini, Journal of Low-Power Electronics, American Scientific Publishers , December 2013.
    (DOI: http://dx.doi.org/10.1166/jolpe.2013.1287)

  7. “800nA Process and Voltage Invariant, 106dB PSRR PTAT Current Reference”, Anvesha A, M. V. Dave, M. Shojaei Baghini, D. K. Sharma, IEEE Transactions on Circuits and Systems II, September 2013.
    (DOI: http://dx.doi.org/10.1109/TCSII.2013.2268435)

  8. “Design of Large Dynamic Range, Low Power, High precision ROIC for Quantum Dot Infrared Photo-detector”, H. S. Gupta, A S K. Kumar, S. Chakrabarti, S. Paul, RM Parmar, DRM Shamudraiah, M.Shojaei Baghini and D. K. Sharma, IET Electronics Letters, August 2013.

  9. “A Versatile high-swing Gm-C filter with Process and Temperature Invariant Bandwidth and Gain for Neuro-potential Signal Conditioning and Recording”, Anvesha A and M. Shojaei Baghini, Journal of Low-Power Electronics, American Scientific Publishers, August 2013.
    (DOI: http://dx.doi.org/10.1166/jolpe.2013.1257)

  10. “A Variation Tolerant Current-Mode Signaling Scheme for On-chip Interconnects”, M. V. Dave, M. Jain, M. Shojaei Baghini, D. K. Sharma, IEEE Transactions on VLSI Systems, February 2013.

  11. K. Singh, N. Chasta and M. Shojaei Baghini, “Experimental Electrical Modeling of Soil for In Situ Soil Moisture Measurement”, Proc. of ISED, 2013, Singapore.

  12. V. Palaparthy, S. Lekshmi, J. John, S. Sarik, M. Shojaei Baghini and D. N. Singh, “Soil Moisture Measurement System for DPHP Sensors and In Situ Applications”, Proc. of ISED, 2013, Singapore.

  13. V. G. Hande, P. Gupta, M. Shojaei Baghini, “Ultra Low-Supply Voltage Reference Generator with Low Sensitivity to PVT Variations”, Proc. of IEEE ASQED , 2013, Malaysia.

  14. V. G. Hande, M. Shojaei Baghini, “Design of Voltage Reference with Low Sensitivity to Process, Supply Voltage and Temperature Variations”, Proc. of IEEE MWSCAS , 2013, USA.

  15. S. R. Kulkarni, M. Shojaei Baghini, “Spiking Neural Network based ASIC for Character Recognition”, Proc. of IEEE ICNC , 2013, China.

  16. S. Gandhi, J. Jain, M. Shojaei Baghini, Soumyo Mukherji, “Comparing Stress Markers Across Various Cohorts in a Mobile Setting”, Proc. of IEEE EMBS , 2013, Japan.

  17. D. Kishan, M. Shojaei Baghini, D. K. Sharma, “A Capacitively Coupled Clock Distribution Network with Correction for Process Dependent Skew”, Proc. of IEEE ICICDT , 2013, Italy.

  18. Anvesha A., M. Shojaei Baghini, “A Versatile Rail to Rail Current Mode Instrumentation Amplifier with an Embedded Band-pass Filter for Bio-potential Signal Conditioning”, Proc. of IEEE ISQED , 2013, USA.

  19. Anvesha A., M. Shojaei Baghini, “A Sub-1V 32nA Process, Voltage and Temperature Invariant Voltage Reference Circuit”, Proc. of International Conf. on VLSID, 2013 (Sister Conf. of IEEE DAC, DATE and ICCAD), India.

  20. N. Kadayinti, M. V. Dave, M. Shojaei Baghini, D. K. Sharma,”A Feed Forward Equalizer for Capacitively Coupled On-Chip Interconnects“, Proc. of International Conf. on VLSID, 2013 (Sister Conf. of IEEE DAC, DATE and ICCAD), India.

  21. S. K. Panigrahi, M. Shojaei Baghini, U. Gogineni, F. Iravani, “120 V Super Junction LDMOS Transistor”, Proc. of IEEE EDSSC 2013, Hong Kong.

2012

  1. “Nanostructured Barrier Type Anodic Oxide MIM Capacitors”, D. Kannadassan, R. Karthik, M. Shojaei Baghini, P. S. Mallick, Journal of Nanoelectronics and Optoelectronics, American Scientific Publishers, August 2012.

  2. “Solution processed photopatternable high-k nanocomposite gate dielectric for low voltage organic field effect transistors”, R. R. Navan, K. Prashanthi, M. Shojaei Baghini, V. Ramgopal Rao, Elsevier Microelectronic Engineering, August 2012.

  3. “Fabrication and Characterization of New Ti-TiO2-Al and Ti-TiO2-Pt Tunnel Diodes”, Y. Rawal, S. Ganguly, M. Shojaei Baghini, Hindawi Active and Passive Electronic Components, 2012.
    (http://dx.doi.org/10.1155/2012/694105).

  4. “Mobility Enhancement of Solution-Processed Poly (3-hexylthiophene) Based Organic Transistor using Zinc Oxide Nanostructures”, R. R. Navan, B. Panigrahy, M. Shojaei Baghini, D. Bahadur and V. Ramgopal Rao, Elsevier Journal of Composites B: Engineering, April 2012.

  5. “Low-Power Low-Noise Analog Signal Conditioning Chip with On-Chip Drivers for Healthcare Applications”, S. Joshi, V. Thaker, Anvesh A., M. Shojaei Baghini, Elsevier Microelectronics Journal, November 2012.
    (DOI: http://dx.doi.org/10.1016/j.mejo.2012.06.008)

  6. “Current Actuation Method for ΔR Measurement in Piezo-Resistive Sensors with a 0.3 ppm Resolution”, N. A. Gilda, S. Nag, S. Patil, M.Shojaei Baghini, D. K. Sharma, V. Ramgopal Rao, IEEE Transactions on Instrumentation & Measurement, March 2012.

  7. “A Process and Temperature Compensated Current Reference Circuit in CMOS Process”, M. V. Dave, M. Shojaei Baghini, D. K. Sharma, Elsevier Microelectronics Journal, February 2012.

  8. Anvesha A., M. V. Dave, M. Shojaei Baghini, D. k. Sharma, “A Process and Temperature Invariant On-Chip Resistor”, Proc. of IEEE MWSCAS , 2012, USA.

  9. Anvesha A, M. Shojaei Baghini, “Process and Temperature Invariant Bandwidth and Gain, Low-Area, Low-Power and High Swing Gm-C Filter for Neuro-Potential Signal Conditioning”, Proc. of IEEE ISLPED , 2012, USA.

  10. M. V. Dave, M. Shojaei baghini, D. K. Sharma, “A Novel Robust Signaling Scheme for High-Speed Low-Power Communication over Long Wires”, Proc. of IEEE ISQED , 2012, USA.

  11. M. V. Dave, M. Shojaei baghini, D. K. Sharma, “High-Speed Low-Power Robust Signaling for On-Chip Long Wires”, IEEE ISSCC Student Research Preview, 2012, USA.

  12. M. Arrawatia, V. Diddi, H. Kochar, M. Shojaei Baghini, Girish Kumar, “An Integrated CMOS RF Energy Harvester with Differential Microstrip Antenna and On-Chip Charger”, Proc. of International Conf. on VLSID 2012 (Sister Conf. of IEEE DAC, DATE and ICCAD) , India.

  13. A. Kumar, Y. Rawal, M. Shojaei Baghini, “Fabrication and Characterization of the ZnO-based Memristor”, IEEE ICEE 2012, India.

  14. D Kannadassan, R Karthik, M. Shojaei Baghini, P. S. Mallick, “Temperature and Stress Dependent Properties of Barrier Type Anodic Al2O3 MIM Capacitor”, IEEE ICEE 2012, India.

  15. A. B. Sachid, P. Paliwal, S. Joshi, M. Shojaei Baghini, D. K. Sharma, V. Ramgopal Rao, “Circuit Optimization at 22nm Technology Node”, Proc. of International Conf. on VLSID 2012 (Sister Conf. of IEEE DAC, DATE and ICCAD), India.

2011

  1. “Towards System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines”, M. Shrivastava, R. Mehta, S. Gupta, N. Agrawal, M. Shojaei Baghini, D. K. Sharma, T. Schulz, K. Arnim, W. Molzer, H. Gossner, V. Ramgopal Rao, IEEE Transactions on Electron Devices, June 2011 (This paper is recognized as feature article in Synopsys newsletter).

  2. “A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs”, R. A. Thakker, M. Srivastava, K. H. Tailor, M. Shojaei Baghini, D. K. Sharma, V. Ramgopal Rao, M. B. Patil Elsevier Microelectronics Journal, May 2011.

  3. P. Kabara, S. Thakur, G. Saileshwar, M. Shojaei Baghini, D. K. Sharma, “CMOS Low-Noise Signal Conditioning with a Novel Differential “Resistance to Frequency” Converter for Resistive Sensor Applications”, Proc. of IEEE ISOCC 2011, South Korea.

  4. S. Joshi, V. Thaker, M. Shojaei Baghini, “Versatile Ultra Low Noise, Low Power Analog Signal Conditioning Chip With Integrated Drivers”, Proc. of IEEE ISIC (one of finalist teams in international chip design competition in ISIC), 2011, Singapore.

  5. V. G. Hande, M. Shojaei baghini, P. R. Apte, “Design and Optimization of High Precision CMOS Voltage Reference Using Taguchi Orthogonal Array Technique”, Proc. of IEEE ISIC, 2011, Singapore.

  6. H. Joshi, M. Shojaei Baghini, “Versatile Battery Chargers for New Age Batteries”, Proc. of IEEE ISED 2011, India.

  7. N. A. Gilda, S. Patil, Seena V, S. Joshi, V. Thaker, S. Thakur, Anvesha A, M. Shojaei Baghini, D. K. Sharma, V. Ramgopal Rao, “Piezoresistive 6-MNA Coated Microcantilevers with Signal Conditioning Circuits for Electronic Nose”, Proc. of IEEE A-SSCC (Sister conference of IEEE ISSCC), 2011, South Korea.

  8. N. A Gilda, S. Surya, S. Joshi, V. Thaker, M. Shojaei Baghini, D. K.Sharma, V.Ramgopal Rao, “A Low-Cost, Ultra Sensitive Hand-Held System for Explosive Detection using Piezo-Resistive Micro-Cantilevers”, Proc. of ISOCC 2011, South Korea (Invited Paper) .

  9. A. Vishnani, M. V. Dave, M. Shojaei Baghini and D. K. Sharma, “A Fully On-Chip Throughput Measurement System for Multi-Gigabits/s On-Chip Interconnects”, Proc. of IEEE ASQED 2011, Malaysia.

  10. A. Vishnani, M. V. Dave, M. Shojaei Baghini and D. K. Sharma, “On-Chip Test Circuits for Throughput Measurement of high-speed Interconnects”, Proc. of VDAT 2011, India.

  11. N. K. Kancharapu, M. V. Dave, M. Shojaei Baghini and D. K. Sharma, “A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology”, Proc. of IEEE ISVLSI (received the best paper award) 2011, India.

  12. S. Sant, S. Waikar, M. V. Dave, M. Shojaei Baghini and D. K. Sharma, “A 16-Gb/s 9mW Transmitter With FFE in 90nm CMOS Technology for Off-Chip Communication”, Proc. of IEEE ISVLSI 2011, India.

  13. M. Arrawatia, M. Shojaei Baghini, Girish Kumar, “RF Energy Harvesting System From Cell Towers in 900MHz Band”, NCC 2011, India.

  14. M. Shojaei Baghini, “Moving Towards 22 nm Node - I/O and ESD Performance”, Tutorial, International Conf. on VLSI Design 2011 (Sister Conf. of IEEE DAC, DATE and ICCAD), India. (Acknowledgment: M. Shrivastava, H. Gossner, S. Bychikhin, V. Ramgopal Rao, D. K. Sharma).

2010

  1. “A Solution Towards the OFF State Degradation in Drain extended MOS Device”, M. Shrivastava, R. Jain, M. Shojaei Baghini, H. Gossner and V. Ramgopal Rao, IEEE Transactions on Electron Devices, December 2010.

  2. “Complementary Organic Circuits using Evaporated F16CuPc and Inkjet Printing of PQT”, H.S. Tan, B.C. Wang, S. Kamath, J. Chua, M. Shojaei Baghini, V. R. Rao, N. Mathews, S.G. Mhaisalkar, IEEE Electron Device Letters, November 2010.

  3. “Part I: On the Behavior of STI Type DeNMOS Device under ESD Conditions”, M. Shrivastava , H. Gossner, M. Shojaei Baghini, V. Ramgopal Rao, IEEE Transactions on Electron Devices, September 2010.

  4. “Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DEMOS Device under Various ESD Conditions”, M. Shrivastava , H. Gossner, M. Shojaei Baghini, V. Ramgopal Rao, IEEE Transactions on Electron Devices, September 2010.

  5. “A Novel Bottom Spacer FinFET Structure For Improved Short Channel, Power-Delay & Thermal Performance”, M. Shrivastava, M. Shojaei Baghini, D. K. Sharma, V. Ramgopal Rao, IEEE Transactions on Electron Devices, June 2010.

  6. “A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance”, R. A. Thakker, C. Sathe, M. Shojaei Baghini, M. B. Patil, IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, April 2010.

  7. “Part I: Mixed Signal Performance of Various High Voltage Drain Extended MOS Devices”, M. Shrivastava, M. Shojaei Baghini, H.Gossner, V. Ramgopal Rao, IEEE Transactions on Electron Devices, Feb. 2010.

  8. “Part II: A Novel Scheme to Optimize the Mixed Signal Performance and Hot Carrier Reliability of Drain Extended MOS Devices”, M. Shrivastava, M. Shojaei Baghini, H.Gossner, V. Ramgopal Rao, IEEE Transactions on Electron Devices, Feb. 2010.

  9. “Comments on “An Analog 2-D DCT Processor””, S. P. Noolu, M. Shojaei Baghini, IEEE Transactions on Circuits and Systems in Video Technology, August 2010.

  10. M. Arrawatia, M. Shojaei Baghini, Girish Kumar, “RF Energy Harvesting System at 2.67GHz and 5.8GHz”, Proc. of APMC 2010, Japan.

  11. M. V. Dave, M. Jain, R. Satkuri, M. Shojaei Baghini, D. K. Sharma, “Energy Efficient Current-Mode Signaling Scheme”, Proc. of IEEE A-SSCC (Sister conference of IEEE ISSCC), 2010, China.

  12. S. K. Gowdhaman, M. Shojaei Baghini, “6-Bit Low-Power Subranging-ADC with Increased Throughput”, Proc. of IEEE MWSCAS 2010, USA.

  13. M. V. Dave, R. Satkuri, M. Jain, M. Shojaei Baghini, D. K. Sharma, “Low-Power Current-Mode Transceiver for On-chip Bidirectional Buses”, Proc. of ACM/IEEE ISLPED 2010, USA.

  14. S. P. Noolu, M. Shojaei Baghini, V. Rajbabu, “Efficient Analog Architectures for DCT Processing”, Proc. of NASA/ESA AHS 2010, USA.

  15. V. G. Hande, M. Shojaei Baghini, “An Ultra Low-Energy DAC for Successive Approximation ADCs”, Proc. of IEEE ISCAS 2010, France.

  16. Y. D. Rawal, M. Shojaei Baghini, S. Ganguly, “Fabrication & Characterization of MIM Tunnel Diodes”, BangaloreNano 2010, India.

  17. M. Shrivastava, H. Gossner, M. Shojaei Baghini, V. Ramgopal Rao, “3D TCAD Based Approach for the Evaluation of Nanoscale Devices During ESD Failure”, Proc. of ISOCC 2010, South Korea (Invited Paper) .

  18. A. B. Sachid, M. Shojaei Baghini, D. K. Sharma, V. Ramgopal Rao, “Alternate Scaling Strategies for Multi-Gate FETs for High-Performance and Low-Power Applications”, Proc. of ISOCC 2010, South Korea (Invited Paper) .

  19. M. Shrivastava, H. Gossner, M. Shojaei Baghini, V. Ramgopal Rao, “On the Transient Behavior of Various Drain Extended MOS Devices Under the ESD Stress Condition”, Proc. of ISOCC 2010, South Korea (Invited Paper) .

  20. S. Prajapati, R.A.Thakker, M. Shojaei Baghini, M.B.Patil, “Performance Evaluation of FinFET and Planar MOSFET Devices at Circuit Level for 45nm Technology”, Proc. of IEEE/VSI VDAT Symposium 2010, India.

  21. M. Shrivastava, J. Schneider, M. Shojaei Baghini, H. Gossner, V. Ramgopal Rao, “On the failure mechanism and current instabilities in RESURF type DeNMOS device under ESD conditions”, Proc. of IEEE IRPS 2010, USA.

  22. M. Shrivastava, S. Bychikhin, D. Pogany, J. Schneider, M. Shojaei Baghini, H. Gossner, E. Gornik, V. Ramgopal Rao, “On the differences between 3D filamentation and failure of n & p type drain extended MOS devices under ESD condition”, Proc. of IEEE IRPS 2010, USA.

  23. A. B. Sachid, R. A. Thakker, C. Sathe, M. Shojaei Baghini, D. K. Sharma, V. R. Rao, M. B. Patil, “Auto-BET-AMS: An Automated Device and Circuit Optimization Platform to Benchmark Emerging Technologies for Performance and Variability using an Analog and Mixed-Signal Design Framework”, Proc. of IEEE ISQED 2010, USA.

2009

  1. “A Novel Table–Based Approach for Design of FinFET Circuits”, R. A. Thakker, C. Sathe, A. B. Sachid, M. Shojaei Baghini, V. R. Rao, M. B. Patil, IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, July 2009.

  2. “Automatic Design of Low-Power Low-Voltage Analog Circuits using PSO with Re-initialization”, R. A. Thakker, M. Shojaei Baghini, M. B. Patil, Journal of Low-Power Electronics, American Scientific Publishers, Oct. 2009 - Special Issue on International Conference on VLSI Design 2009.

  3. R. A. Thakker, M. Shojaei Baghini, M. B. Patil, “Low-Power Low-Voltage Analog Circuit Design using HPSO”, Proc. of International Conf. on VLSID 2009 (Sister Conf. of DAC), India.

  4. R. Modak, M. Shojaei Baghini, “A Generic Analytical Model of Switching Characteristics for Efficiency-Oriented Design and Optimization of CMOS Integrated Buck Converters”, Proc. of IEEE ICIT 2009, Australia.

  5. M. V. Dave, M. Shojaei Baghini, D. K. Sharma, “A Process Variation Tolerant, High-Speed and Low-Power Current Mode Signaling Scheme for On-chip Interconnects”, Proc. of ACM/IEEE GLSVSLI, 2009, USA.

  6. S. R. Krishna, M. Shojaei Baghini, J. Mukherjee, “Current-Mode CMOS Pipelined ADC”, Proc. of IEEE Eurocon 2009, Russia.

  7. K. Bhattacharyya, J. Mukherjee, M. Shojaei Baghini, “27.1GHz CMOS Distributed Voltage Controlled Oscillators With Body Bias for Frequency Tuning of 1.28GHz”, IEEE MWSCAS 2009, Mexico.

  8. J. Mukherjee, M. Shojaei Baghini, M. Johnson, “Phase Noise Reduction in Quadrature LC Oscillators Using Inverter-Based Tail Noise Shaping”, Proc. of IEEE NEWCAS and TAISA, 2009, France.

  9. K. Bhattacharyya, J. Mukherjee, M. Shojaei Baghini, “Effects of Substrate Bias on Noise of 0.18µm CMOS Devices at Microwave Frequency”, IWPSD 2009, India.

  10. K. Bhattacharyya, J. Mukherjee, M. Shojaei Baghini, “20GHz CMOS Distributed Voltage Controlled Oscillators With Frequency Tuning By MOS Varactors”, Proc. of IEEE IEDST 2009, India.

  11. M. Shrivastava, B. Verma, M. Shojaei Baghini, C. Russ, D. K. Sharma, H. Gossner, V. R. Rao, “Benchmarking The Device Performance at Sub 22 nm Node Technologies Using an SoC Framework”, Proc. of IEEE IEDM 2009, USA.

  12. M. Shrivastava, S. Bychikhin, D. Pogany, J. Schneider, M. Shojaei Baghini, H. Gossner, E. Gornik, V. R. Rao, “Filament Study of STI Type Drain Extended NMOS Device Using Transient Interferometric Mapping”, Proc. of IEEE IEDM 2009, USA.

  13. M. Shrivastava, J. Schneider, R. Jain, M. Shojaei Baghini, H. Gossner, V. R. Rao, “IGBT plugged in SCR device for ESD protection in advanced CMOS technology”, Proc. of EOS/ESD Symposium 2009, USA.

  14. R. A. Thakker, C. Sathe, A. B. Sachid, M. Shojaei Baghini, V. R. Rao, M. B. Patil, “Automated Design and Optimization of Circuits in Emerging Technologies”, Proc. of IEEE ASP-DAC (Sister Conf. of IEEE DAC , DATE and ICCAD), 2009, Japan.

  15. M. Shrivastava, J. Schneider, M. Shojaei Baghini, H. Gossner, V. R. Rao, Highly resistive body STI-n-DeMOS: An optimized DeMOS device to achieve moving current filaments for robust ESD protection”, Proc. of IEEE IRPS 2009, Canada.

  16. M. Shrivastava, J. Schneider, M. Shojaei Baghini, H. Gossner, V. R. Rao, “A New Physical Insight and 3D Device Modeling of STI Type DeNMOS Device Failure under ESD Conditions”, Proc. of IEEE IRPS 2009, Canada.

  17. R. R. Navan, H. N. Raval, M. A. Khaderbad, M. Shojaei Baghini and V. Ramgopal Rao, “Low Voltage Patterned Gate Pentacene Organic Circuits with Hafnium oxide High-K Gate Dielectric”, OSC 2009, UK.

  18. R. R. Navan, K. Prashanthi, A. Rajoriya, M. Shojaei Baghini, V. R. Palkar, V. R. Rao, “A Novel High-K (K > 40) Gate Dielectric for Pentacene Organic Thin Film Transistors”, Proc. of ICCE-17 2009, USA.

  19. A. B. Sachid, G. S. Kulkarni, M. Shojaei Baghini, D. K. Sharma, V. R. Rao, “Highly Robust Nanoscale Planar Double-Gate MOSFET Device and SRAM Cell Immune to Gate-Misalignment and Process Variations”, Proc. of IEEE IEDST 2009, India.

  20. R. R. Navan, R. A. Thakker, S. P. Tiwari, M. Shojaei Baghini, M. B. Patil, S. G. Mhaisalkar, V. R. Rao,
    “DC & Transient Circuit Simulation Methodologies for Organic Electronics”, Proc. of IEEE IEDST 2009, India.

2008

  1. “A Novel and Robust Approach for Common Mode feedback using IDDG FinFET”, M. Srivastava, M. Shojaei Baghini, A. B. Sachid, D. K. Sharma, V. R. Rao, IEEE Transactions on Electron Devices, Nov. 2008.

  2. “An Ultra Low-Power Current-Mode Integrated CMOS Instrumentation Amplifier for Personal ECG Recorders”, M. Shojaei Baghini, S. Nag, R. K. Lal, D. K. Sharma, World Scientific Journal of Circuits, Systems, and Computers, Dec. 2008.

  3. M. V. Dave, M. Shojaei Baghini, D. K. Sharma, “Low-Power Current-Mode Receiver with Inductive Input Impedance”, Proc. of ACM/IEEE ISLPED 2008, India.

  4. A. B. Sachid, R. Francis, M.Shojaei Baghini, D.K. Sharma, Karl-Heinz Bach, R. Mahnkopf, V. R. Rao, “Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?“, Proc. of IEEE IEDM 2008, USA.

  5. A. B. Sachid, M. Shrivastava, R. A. Thakker, M. Shojaei Baghini, D. K. Sharma, M.B.Patil, V. R. Rao, “Technology-Aware Design (TAD) for Sub-45nm CMOS Technologies”, Intel Corporation AAF 2008, Taiwan (received the best research paper award in circuit design category) .

  6. R. Satkuri, M. V. Dave, M. Shojaei Baghini, D. K. Sharma, “On-chip Test Circuits for Fast Interconnects”, Proc. of IEEE VDAT 2008, India.

2007 and BEFORE

  1. J. Mukherjee, Young-Gi Kim, I. Suh, P. Roblin, Wan-Rone Liou, Yao-Chian Lin, M. Shojaei Baghini “Microstrip Equivalent Parasitic Modeling of RFIC Interconnects”, Proc. of IEEE MWSCAS 2007, Canada.

  2. R. D. Kanphade, M. Shojaei Baghini, D. G. Wakade, M. Chhangani, M. Patil, S. M. Ranjan, J. R. Verma, N. K. Ingole, P. Gawande, “Design of low power FPAA in 0.35u CMOS Process”, Accepted in IASTED ICCSS 2006, USA.

  3. R. D. Kanphade, M. Shojaei Baghini, D. G. Wakade, M. Chhangani, M. V. Patil, S. M. Ranjan, J. R. Verma, N. K. Ingole, P. Gawande, “Design of FPAA using custom IC and optimization-based design flow”, Proc. of CDNLive 2006, USA.

  4. P. Gawande, M. Chhangani, J. Verma, M. Patil, N. Ingole, M. Shojaei Baghini, R. D. Kanphade, “Design and implementation of low-cost power-optimized OTA-based FPAA in 0.35um MM CMOS process” CDNLive 2006, India, (winner of the First Cadence Design Systems, Inc. Design Contest held among SAARC countries, 2006).

  5. ”Evaluation of the Impact of Layout on Device and Analog Circuit Performance with Lateral Asymmetric Channel MOSFETs”, D. V. Kumar, K. Narasimhulu, P. S. Reddy, M. Shojaei Baghini, D. K. Sharma, M. B. Patil, V. R. Rao, IEEE Transactions on Electron Devices, July 2005.

  6. M. Shojaei Baghini, R. K. Lal, D. K. Sharma, “A Low-Power and Compact Analog CMOS Processing Chip for Portable ECG Recorders”, Proc. of IEEE A-SSCC 2005 (Sister Conf. of IEEE ISSCC), Taiwan.

  7. M. Shojaei Baghini, R. K. Lal, D. K. Sharma, “An Ultra Low-Power Instrumentation Amplifier for Biomedical Applications”, Proc. of IEEE BioCAS 2004, Singapore.

  8. V. M. Tousi, F. Sahandi, M. Atarodi, M. Shojaei Baghini, “A 3.3V / 1W Class D Audio Power Amplifier with 103 dB DR and 90% Efficiency”, Proc. of MIEL 2002, Yugoslavia.

  9. M. Shojaei Baghini, M. P. Desai, “Impact of technology scaling on metastability performance of of CMOS synchronizing latches”, Proc. of International Conf. on VLSID 2002 (Sister Conf. of IEEE DAC, DATE and ICCAD), India.

  10. N. K. Jha, M. Shojaei Baghini, V. R. Rao, “Performance and Reliability of Single Pocket Deep Submicron MOSFETs for Analog Applications”, Proc. of ISPFAIC 2002, Singapore.

  11. “A Mixed Algorithmic and Knowledge-based Approach for Automatic Design of Analog Circuits Based on a Behavioral Model”, M. Shojaei Baghini, M. Sharif-Bakhtiar, Scientia Iranica (International Journal of Science and Technology), Jan. 1999.
  12. M. Shojaei Baghini, M. Sharif-Bakhtiar, “A Method for Automatic Design of Analog Circuits based on a Behavioral Model”, Proc. of IEEE ISCAS 1998, USA.

  13. M. Shojaei Baghini, M. Sharif-Bakhtiar, “Automatic Design of Analog Circuits based on a Behavioral Model”, Proc. of IEEE CCECE 1998, Canada.

Contact Information

Department of Electrical Engineering
IIT-Bombay, Powai
Mumbai 400 076, India
Email : mshojaei[AT]ee.iitb.ac.in
Phone (Internal(O)): 0091 22 25767425
Office: Room 610, EE-NanoE BLDG.

faculty/mshojaei_bkp.txt · Last modified: 2021/09/06 08:38 (external edit)

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