Professor
Fellow - IEEE, INSA, INAE, IASc
Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email: souvik@ee.iitb.ac.in
Email: mahapatra.souvik@gmail.com
Phone (Internal(O)): (0091 22) - 2576 7412
Fax: (0091 22) - 25723707
Office room no: 602, Nanoelectronics Building

Google Scholar profile: http://scholar.google.co.in/citations?user=5j5CLuEAAAAJ

(Note: I do not offer summer internships)

NBTI Book (Springer; 2021-November):

Recent Advances in PMOS Negative Bias Temperature Instability

https://link.springer.com/book/10.1007/978-981-16-6120-4

BTI Book (Springer; 2015-August):

Fundamentals of Bias Temperature Instability in MOS Transistors

http://link.springer.com/book/10.1007/978-81-322-2508-9

Selected recent papers (CMOS logic reliability):

BTI Analysis Tool (BAT) Framework:

https://ieeexplore.ieee.org/document/8233406/

NBTI - SOI FinFET (extended T range):

https://ieeexplore.ieee.org/document/8123522/

NBTI - Bulk Si and SiGe FinFET (different Ge, N):

https://ieeexplore.ieee.org/document/8330761/

https://ieeexplore.ieee.org/document/8330756/

NBTI - FDSOI (different Ge, N, mechanical strain)

https://ieeexplore.ieee.org/document/8353699/

NBTI - Si capped SiGe (planar)

https://ieeexplore.ieee.org/document/8353700/

Stochastic NBTI:

https://ieeexplore.ieee.org/document/7775005/

NBTI - TCAD implementation:

https://ieeexplore.ieee.org/document/7589064/

NBTI - Universality across technologies:

https://ieeexplore.ieee.org/document/6860615/

Physics of NBTI and PBTI:

https://ieeexplore.ieee.org/document/6417017/

https://ieeexplore.ieee.org/document/7556310/

https://ieeexplore.ieee.org/document/7116557/

N, P BTI - Gate stack process impact:

https://ieeexplore.ieee.org/document/6532014/

PBTI modeling:

https://ieeexplore.ieee.org/document/7867042/

Hot Carrier Degradation:

https://ieeexplore.ieee.org/document/8372954/

Device-circuit framework:

https://ieeexplore.ieee.org/document/8510876

https://ieeexplore.ieee.org/document/8563055

https://ieeexplore.ieee.org/document/7112783

• Electrical characterization, modeling and simulation of micro/nano electronic devices
• Design Technology Co-Optimization, Ageing impact on circuits
• NBTI/PBTI and Hot carrier degradation in MOSFETs
• High-k gate dielectrics
• Advanced CMOS devices - scaling and reliability
• Flash memories - 3D NAND
• Solar cells

• PhD (Electrical Engineering), IIT Bombay, 1999
• MSc (Physics), Jadavpur University, Calcutta, 1995

• Professor, Department of Electrical Engineering, IIT Bombay (2009 - present)
• Visiting Faculty Fellow, Applied Materials, Santa Clara, CA, USA (June - December, 2006)
• Associate Professor, Department of Electrical Engineering, IIT Bombay (2005 - 2008)
• Assistant Professor, Department of Electrical Engineering, IIT Bombay (2002 - 2004)
• PMTS, Bell Laboratories, Lucent Technologies, Murray Hill, NJ, USA (2000 - 2001)
• Siemens Research Fellow, IIT Bombay & UniBW, Munich (1997 - 1999)

• Fellow, Institute of Electrical and Electronics Engineers (IEEE)

• Fellow, Indian National Science Academy (INSA)

• Fellow, Indian Academy of Sciences (IASc)

• Fellow, Indian National Academy of Engineering (INAE)

• IBM Faculty Award, 2013 and 2018

• Vikram Sarabhai Award, Physical Research Laboratory (PRL)

• Young Engineer Award, Indian National Academy of Engineering (INAE), 2004

• Innovation Potential of Students Projects Award 2000 - Doctoral Level, Indian National Academy of Engineering (INAE), 2001

• Melchor visiting professor, School of Engineering, University of Notre Dame, USA

• Graduate faculty, School of Electrical Engineering and Computer Science, Purdue University, USA

• Awarded Erasmus Mundus fellowship (visiting fellow at IMEC, Belgium), 2015.

• Awarded Tan Chin Tuan fellowship by Singapore government (visiting faculty, Nanyang Technological University, Singapore), 2008.

• Tutorial speaker, IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA (2020)

• Invited speaker, IEEE Electron Device Technology and Manufacturing (EDTM) conference, Penang, Malaysia (2020)

• Tutorial speaker, IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA (2019)

• Tutorial speaker, IEEE Reliability Physics Symposium (IRPS), Monterey, CA, USA (2017)

• Invited speaker, IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Tayoma, Japan (2017)

• Tutorial speaker, IEEE Reliability Physics Symposium (IRPS), Kona, HI, USA (2014)

• Tutorial and invited speaker, International Symposium of Microelectronics Technology and Devices (SB Micro), Aracaju, Brazil (2014)

• Invited speaker, International Conference on Materials for Advanced Technologies (ICMAT), Singapore (2013)

• Invited speaker,International Conference on Solid State and Integrated Circuits Technology (ICSICT), Xian, China (2012)

• Invited speaker, Solid State Devices & Materials (SSDM) Conference, Nagoya, Japan, 2011.

• Tutorial and invited speaker, International Conference on the Physical and Failure Analysis of Integrated Circuits (IPFA), Seuol, Korea, 2011.

• Invited speaker, International Conference on Materials for Advanced Technologies (ICMAT), Singapore, 2011.

• Invited speaker, MIRAI Variability Conference, Tokyo, Japan, 2011.

• Tutorial speaker, International Reliability Physics Symposium (IRPS), Montreal, Canada, 2009.

• Invited speaker, ECS fall meeting in Vienna, Austria, 2009.

• Invited speaker, ECS spring meeting in San Francisco, CA, USA, 2009.

• Invited speaker, VLSI conference, New Delhi, India, 2009.

• Invited speaker, International Conference on Solid State and Integrated Circuit Technology (ICSICT), Beijing, China, 2008.

• Invited speaker, International Workshop on Physics of Semiconductor Devices (IWPSD), Mumbai, India, 2007.

• Tutorial speaker, International Reliability Physics Symposium (IRPS), Phoenix, AZ, USA, 2007.

• Tutorial speaker, International Reliability Physics Symposium (IRPS), San Jose, CA, USA, 2006.

• Invited speaker, Solid State Devices & Materials (SSDM) Conference, Kobe, Japan, 2005.

• Invited speaker, Insulating Films on Semiconductors (INFOS) Conference, IMEC, Leuven, Belgium, 2005.

• Invited speaker, International Electron Devices Meeting (IEDM), San Francisco, USA, 2004.

• JEDEC standards document JEP122D, release October 2008, referred to the NBTI characterization, modeling and material dependence work.

• S. Mahapatra, V. Huard, A. Kerber, V. Reddy, S. Kalpat and A. Haggag, “Universality of NBTI - From devices to circuits and products”, IEEE International Reliability Physics Symposium (IRPS), Kona, HI, USA, pp.3B.1.1-3B.1.8, 2014 (https://ieeexplore.ieee.org/document/6860615/)

• https://news.synopsys.com/2016-12-05-Synopsys-and-IIT-Bombay-Announce-Release-of-Sentaurus-TCAD-Model-for-NBTI-Reliability-Simulation-of-Advanced-Transistors

• Technical program chair, 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Bangalore, India 2007.

• Transistor subcommittee chair, IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2017

• Transistor subcommittee chair, IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2015

• Transistor subcommittee chair, IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, USA, 2012

• Transistor subcommittee co-chair, IEEE International Reliability Physics Symposium (IRPS), Kona, HI, USA, 2014

• Transistor subcommittee co-chair, IEEE International Reliability Physics Symposium (IRPS), Phoenix, AZ, USA, 2007

• CRY subcommittee member, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2014, 2015

• Transistor subcommittee member, IEEE International Reliability Physics Symposium (IRPS), USA, 2007-2011

• Distinguished Lecturer (DL), IEEE Electron Devices Society.

• EE207 (Electronic Devices and Circuits)
• EE432 (Special Semiconductor devices)
• EE620 (Physics of Transistors)
• EE661 (Physical Electronics)

• EE219 (Electronics)
• EE319 (Analog Circuits)
• EE672 (Microelectronics)

• Reliability of HKMG stacks for sub 20nm CMOS nodes (Applied Materials, USA)
• BTI/HCI model development for TCAD (Synopsys, USA)
• BTI impact on SRAM cells (Synopsys, USA)
• Characterization of thin film solar cells (Applied Materials, USA)
• Reliability of ultrathin gate dielectrics (Renesas Technologies, Japan)
• Devices for 3D memory applications (Micron Technologies, USA)
• Modeling of Metal Nanocrystal Flash (Intel custom via SRC-GRC, USA)
• High-k/MG for memory and logic applications (Applied Materials custom via SRC-GRC, USA)
• Reliability of Flash memory tunnel oxide (Applied Materials, USA)
• Optimization of Charge Trap Flash for NAND applications (Applied Materials, USA)
• Split gate Flash EEPROM performance, scaling & reliability (TSMC, Taiwan, ROC)
• Metal Nanocrystal NAND Flash (Applied Materials, USA)
• NBTI in DPN based SiON devices (Applied Materials, USA)
• Advanced B4 NOR Flash (Genusion, Japan)
• CHISEL NOR Flash (Hitachi, Japan)
• SONOS NOR Flash (Renesas Technologies, Japan)

Souvik Mahapatra, Ed., Fundamentals of Bias Temperature Instability in MOS Transistors, Springer 2016, with following chapters:

• S. Mahapatra, N. Goel and S. Mukhopadhyay, Introduction: Bias Temperature Instability (BTI) in N and P Channel MOSFETs
• S. Mahapatra, N. Goel, A. Chaudhury, K. Joshi and S. Mukhopadhyay, Characterization Methods for BTI Degradation and Associated Gate Insulator Defects
• S. Mukhopadhyay and S. Mahapatra, Physical Mechanism of BTI Degradation – Direct Estimation of Trap Generation and Trapping
• S. Mahapatra, K. Joshi S. Mukhopadhyay, A. Chaudhury and N. Goel, Physical Mechanism of BTI Degradation – Modeling of Process and Material Dependence
• A. E. Islam, N. Goel, S. Mahapatra and M. A. Alam, Reaction-Diffusion Model
• N. Goel and S. Mahapatra, Modeling of DC and AC NBTI Degradation and Recovery for SiON and HKMG MOSFETs

Tibor Grasser, Ed., “Bias Temperature Instability in Devices and Circuits”, Springer (2013)

• S. Mahapatra, A Comprehensive Modeling Framework for DC and AC NBTI
• S. Mahapatra, FEOL and BEOL Process Dependence of NBTI

(Subdivided into research topics, and in reverse chronological order)

• S. Kumar, R. Anandkrishnan, N. Parihar and S. Mahapatra, “A Stochastic Framework for the Time Kinetics of Interface and Bulk Oxide Traps for BTI, SILC, and TDDB in MOSFETs,” in IEEE Transactions on Electron Devices, vol.67, pp.4741-4748, November 2020

• N. Choudhury, N. Parihar, N. Goel, A. Thirunavukkarasu and S. Mahapatra, “Modeling of DC -AC NBTI Stress -Recovery Time Kinetics in P-Channel Planar Bulk and FDSOI MOSFETs and FinFETs,” in IEEE Journal of the Electron Devices Society, vol.8, pp.1281-1288, 2020

• (Invited) S. Mahapatra and N. Parihar, “Modelling of NBTI using BAT framework: DC-AC Stress-Recovery Kinetics, Materials and Process Impact”, IEEE Transactions on Devices and Materials Reliability, pp.4-23, 2020

• N. Parihar, R. Anandkrishnan, A. Chaudhury and S. Mahapatra, “A comparative analysis of NBTI variability and TDDS in GF HKMG Planar p-MOSFETs and RMG HKMG p-FinFETs”, IEEE Transactions on Electron Devices, pp. 3273-3278, 2019.

• N. Goyal, S. Mahapatra, and S. Lodha, “Ultrafast characterization of hole trapping near Black Phosphorous-SiO2 interface during NBTI stress in 2-D BP FETs”, IEEE Transactions on Electron Devices, pp. 4572-4577, 2019.

• R. Tiwari, N. Parihar, K. Thakor, H. Y. Wong, S. Motzny, M. Choi, V. Moroz, and S. Mahapatra, “A 3-D TCAD Framework for NBTI–Part I: Implementation Details and FinFET Channel Material Impact,” IEEE Transactions on Electron Devices, pp. 2086-2092, 2019.

• R. Tiwari, N. Parihar, K. Thakor, H. Y. Wong, S. Motzny, M. Choi, V. Moroz, and S. Mahapatra, “A 3-D TCAD Framework for NBTI, Part-II: Impact of Mechanical Strain, Quantum Effects, and FinFET Dimension Scaling,” IEEE Transactions on Electron Devices, pp. 2093-2099, 2019.

• C. Joishi, S. Ghosh, S. Kothari, N. Parihar, S. Mukhopadhyay, S. Mahapatra, and S. Lodha, “Understanding PBTI in Replacement Metal Gate Ge n-Channel FETs With Ultrathin Al2O3 and GeO<italic>x</italic> ILs Using Ultrafast Charge Trap–Detrap Techniques,” IEEE Transactions on Electron Devices, vol. 65, no. 10, pp. 4245–4253, Oct. 2018.

• N. Parihar, R. G. Southwick, M. Wang, J. H. Stathis, and S. Mahapatra, “Modeling of NBTI Kinetics in RMG Si and SiGe FinFETs, Part-I: DC Stress and Recovery,” IEEE Transactions on Electron Devices, vol. 65, no. 5, pp. 1699–1706, May 2018.

• N. Parihar, R. G. Southwick, M. Wang, J. H. Stathis, and S. Mahapatra, “Modeling of NBTI Kinetics in Replacement Metal Gate Si and SiGe FinFETs—Part-II: AC Stress and Recovery,” IEEE Transactions on Electron Devices, vol. 65, no. 5, pp. 1707–1713, May 2018.

• N. Parihar, N. Goel; S. Mukhopadhyay and S. Mahapatra, “BTI Analysis Tool — Modeling of NBTI DC, AC Stress and Recovery Time Kinetics, Nitrogen Impact, and EOL Estimation”, IEEE Trans. Electron Devices, p.392, v.65, 2018

• N. Parihar, U. Sharma, R. G. Southwick, M. Wang; J. H. Stathis and S. Mahapatra, “Ultrafast Measurements and Physical Modeling of NBTI Stress and Recovery in RMG FinFETs Under Diverse DC–AC Experimental Conditions”, IEEE Trans. Electron Devices, p.23, v.65, 2018

• A. Chaudhary, B. Fernandez, N. Parihar and S. Mahapatra, “Consistency of the Two Component Composite Modeling Framework for NBTI in Large and Small Area p-MOSFETs”, IEEE Trans. Electron Devices, p.256, v.64, 2017

• S. Mukhopadhyay, N. Parihar, N. Goel and S. Mahapatra, “A Comprehensive DC and AC PBTI Modeling Framework for HKMG n-MOSFETs”, IEEE Trans. Electron Devices, p.1474, v.64, 2017

• S. Mukhopadhyay, N. Goel, and S. Mahapatra, “A Comparative Study of NBTI and PBTI Using Different Experimental Techniques”, IEEE Trans. Electron Devices, p.4038, v.63, 2016

• S. Mishra, H. Y. Wong, R. Tiwari, A. Chaudhary, R. Rao, V. Moroz and S. Mahapatra, “TCAD-Based Predictive NBTI Framework for Sub-20-nm Node Device Design Considerations”, IEEE Trans. Electron Devices, p.4624, v.63, 2016

• N. Parihar, N. Goel, A. Chaudhary, and S. Mahapatra, “A Modeling Framework for NBTI Degradation Under Dynamic Voltage and Frequency Scaling”, IEEE Trans. Electron Devices, p.946, v.63, 2016

• S. Mukhopadhyay and S. Mahapatra, “An Experimental Perspective of Trap Generation Under BTI Stress”, IEEE Trans. Electron Devices, p.2092, v.62, 2015

• N. Agrawal, A, V. Thathachary, S. Mahapatra and S. Datta, “Impact of Varying Indium(x) Concentration and Quantum Confinement on PBTI Reliability in InxGa1-xAs FinFET”, IEEE Electron Dev. Lett., v.36, p.120, 2015

• K. Joshi, S. Mukhopadhyay, N. Goel, N. Nanaware and S. Mahapatra, “A detailed study of gate insulator process dependence of NBTI using a compact model”, IEEE Trans. Electron Devices, p.408, v.61, 2014

• (Invited) N. Goel, K. Joshi, S. Mukhopadhyay, N. Nanaware and S. Mahapatra, “A comprehensive modeling framework of gate stack process dependence of DC and AC NBTI in SiON and HKMG p-MOSFETs”, Microelectronics Reliability, v.54, p.491, 2014

• N. Goel, N. Nanaware and S. Mahapatra, “Understanding AC-DC NBTI characterization of deep IL scaled HKMG p-MOSFETs”, IEEE Electron Dev. Lett., v.34, p.1476, 2013

• S. Mahapatra, S. De, K. Joshi, S. Mukhopadhyay, R. K. Pandey and K. V. R. M. Murali, “Understanding process impact of hole traps and NBTI in HKMG p-MOSFETs using measurements and atomistic simulations”, IEEE Electron Dev. Lett., v.34, p.963, 2013

• (Invited) S. Mahapatra, N. Goel, S. Desai, S. Gupta, B. Jose, S. Mukhopadhyay, K. Joshi, A. Jain, A. E. Islam, and M. A. Alam, “A comparative study of different physics-based NBTI models”, IEEE Transactions on Electron Devices, 60 (3), art. no. 6417017, pp. 901-916, 2013

• A. Chaudhary, and S. Mahapatra, “A physical and SPICE mobility degradation analysis for NBTI”, IEEE Transactions on Electron Devices, 60 (7), art. no. 6522513, pp. 2096-2103, 2013

• K. Joshi, S. Hung, S. Mukhopadhyay, T. Sato, M. Bevan, B. Rajamohnan, A. Wei, A. Noori, B. Mc.Dougal, C. Ni, C. Lazik, G. Saheli, P. Liu, D. Chu, S. Datta, A. Brand, J. Swenberg, and S. Mahapatra, “Scaled gate stacks for sub-20nm CMOS logic applications through integration of thermal IL and ALD HfOx”, IEEE Electron Dev. Lett., v.34, p.3, 2013

• S. Deora, P. Narayanasetti, M. Thakkar and S. Mahapatra, “Development of a novel ultrafast direct threshold voltage (UF-DVT) technique to study NBTI stress and recovery”, IEEE Trans. Electron Devices, v.58, no.10, pp.3506-3513, 2011

• S. Deora, A. E. Islam, M. A. Alam and S. Mahapatra, “A common framework of NBTI generation and recovery in plasma nitrided SiON p-MOSFETs”, IEEE Electron Dev. Lett., v.30, p.978, 2009.

• S. Mahapatra, V. D. Maheta, A. E. Islam and M. Alam, “Isolation of NBTI stress generated interface trap and hole trapping components in PNO p-MOSFETs”, IEEE Trans. Electron Devices, v.56, p.236, 2009.

• S. Deora, V. D. Maheta, G. Bersuker, C. Olsen, K. Ahmed, R. Jammy and S. Mahapatra, “A comparative NBTI study of HfO2, HfSiOX and SiON p-MOSFETs using UF-OTF IDLIN technique”, IEEE Electron Dev. Lett., v.30, p.152, 2009.

• V. D. Maheta, E. N. Kumar, S. Purawat, C. Olsen, K. Ahmed and S. Mahapatra, “Development of an ultra-fast on-the-fly IDLIN technique to study NBTI in plasma and thermal oxynitride p-MOSFETs”, IEEE Trans. Electron Devices, v.55, p.2614, 2008.

• V. D. Maheta, C. Olsen, K. Ahmed and S. Mahapatra, “The impact of nitrogen engineering in silicon oxynitride gate dielectric on negative bias temperature instability in p-MOSFETs: A study by ultra-fast on-the-fly IDLIN technique”, IEEE Trans. Electron Devices, v.55, p.1630, 2008.

• A. E. Islam, G. Gupta, K. Z. Ahmed, S. Mahapatra and M. A. Alam, “Optimization of gate leakage and NBTI for plasma-nitrided gate oxides by numerical and analytical models”, IEEE Trans. Electron Devices, v.55, p.1143, 2008.

• (Invited) S. Mahapatra and M. A. Alam, “Defect generation in p-MOSFETs under negative bias stress: An experimental perspective”, IEEE Trans. Materials and Dev. Reliability, v.8, p.35, 2008.

• D. Varghese, G. Gupta, L. Madhav, D. Saha, K. Ahmed, F. Nouri and S. Mahapatra, “Physical Mechanism and Gate Insulator Material Dependence of Generation and Recovery of Negative Bias Temperature Instability in p-MOSFETs”, IEEE Trans. Electron Devices, p.1672, v.54, July 2007.

• (Invited) A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra and M. A. Alam, “Recent issues in negative bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects and relaxation”, IEEE Trans. Electron Devices, p.2143, v.54, September, 2007.

• M. A. Alam, H. Kufluoglu, D. Varghese and S. Mahapatra, “A Comprehensive Model of PMOS NBTI Degradation: Recent progress”, Microelectronics Reliability, v.47, p.853, 2007.

• (Invited) M. A. Alam and S. Mahapatra, “A Comprehensive Model of PMOS NBTI Degradation”, Microelectronics Reliability, special issue on NBTI, v.45, p.71, 2005

• D. Varghese, S. Mahapatra and M. A. Alam, “Hole energy dependent interface trap generation in MOSFET Si/SiO2 interface”, IEEE Electron Devices Lett., v.26, p.572, Aug. 2005.

• S. Mahapatra, P. Bharath Kumar and M. A. Alam, “Investigation and Modeling of Interface and Bulk Trap Generation During Negative Bias Temperature Instability of p-MOSFETs”, IEEE Trans. Electron Devices, v.51, p.1371, 2004.

• S. Bhagdikar and S. Mahapatra, “Benchmarking Charge Trapping Models with NBTI, TDDS and RTN Experiments,” 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kobe, Japan, 2020, pp. 117-120

• R. Tiwari, N. Choudhury, T. Samadder, S. Mukhopadhyay, N. Parihar and S. Mahapatra, “TCAD Incorporation of Physical Framework to Model N and P BTI in MOSFETs,” 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kobe, Japan, 2020, pp. 113-116

• N. Choudhury, N. Parihar, N. Goel, A. Thirunavukkarasu and S. Mahapatra, “A Model for Hole Trapping-Detrapping Kinetics During NBTI in p-Channel FETs: (Invited paper),” 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Penang, Malaysia, 2020, pp. 1-4

• N. Choudhury, N. Parihar and S. Mahapatra, “Analysis of The Hole Trapping Detrapping Component of NBTI Over Extended Temperature Range,” 2020 IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA, 2020, pp. 1-5,

• R. Tiwari, N. Parihar, K. Thakor, H. Wong and S. Mahapatra, “TCAD Framework to Estimate the NBTI Degradation in FinFET and GAA NSFET Under Mechanical Strain,” 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Udine, Italy, 2019, pp. 1-4,

• S. Bhagdikar and S. Mahapatra, “A Stochastic Hole Trapping-Detrapping Framework for NBTI, TDDS and RTN,” 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Udine, Italy, 2019, pp. 1-4,

• N. Parihar, U. Sharma, R. G. Southwick, M. Wang, J. H. Stathis and S. Mahapatra, “On the Frequency Dependence of Bulk Trap Generation During AC Stress in Si and SiGe RMG P-FinFETs,” 2019 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2019, pp. 1-8,

• N. Parihar, R. Tiwari, C. Ndiaye, M. Arabi, S. Mhira, H. Wong, S. Motzny, V. Moroz, V. Huard, and S. Mahapatra, “Modeling of Process (Ge, N) Dependence and Mechanical Strain Impact on NBTI in HKMG SiGe GF FDSOI p-MOSFETs and RMG p-FinFETs,” in 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), p. 167, 2018.

• N. Parihar, R. Tiwari, and S. Mahapatra, “Modeling Channel Length Scaling Impact on NBTI in RMG Si p-FinFETs,” in 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), p.176, 2018.

• R. Anandkrishnan, S. Bhagdikar, N. Choudhury, R. Rao, B. Fernandez, A. Chaudhury, N. Parihar, and S. Mahapatra, “A Stochastic Modeling Framework for NBTI and TDDS in Small Area p-MOSFETs,” in 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), p.181, 2018.

• H. Y. Wong, M. Choi, R. Tiwari, and S. Mahapatra, “On the NBTI of Junction-less Nanowire and Novel Operation Scheme to Minimize NBTI Degradation in Analog Circuits,” in 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), p.172, 2018.

• V. Huard, C. Ndiaye, M. Arabi, N. Parihar, X. Federspiel, S. Mhira, S. Mahapatra, and A. Bravaix, “Key parameters driving transistor degradation in advanced strained SiGe channels,” in 2018 IEEE International Reliability Physics Symposium (IRPS), 2018.

• N. Parihar and S. Mahapatra, “Prediction of NBTI stress and recovery time kinetics in Si capped SiGe p-MOSFETs,” in 2018 IEEE International Reliability Physics Symposium (IRPS), 2018.

• N. Parihar, R. G. Southwick, M. Wang, J. H. Stathis and S. Mahapatra, “Modeling of NBTI Time Kinetics and T Dependence of VAF in SiGe p-FinFETs”, IEEE International Electron Devices Meeting (IEDM), p., 2017

• S. Mishra, H. Y. Wong, R. Tiwari, A. Chaudhary, N. Parihar, R. Rao, S. Motzny, V. Moroz and S. Mahapatra, “Predictive TCAD for NBTI stress-recovery in various device architectures and channel materials”, IEEE International Reliability Physics Symposium (IRPS), p.6A-3.1, 2017

• N. Parihar, R. G. Southwick, U. Sharma, M. Wang, J. H. Stathis, and S. Mahapatra, “Comparison of DC and AC NBTI kinetics in RMG Si and SiGe p-FinFETs”, IEEE International Reliability Physics Symposium (IRPS), p.2D-4.1, 2017

• N. Parihar, U. Sharma, S. Mukhopadhyay, N. Goel, A. Chaudhary, R. Rao and S. Mahapatra, “Resolution of disputes concerning the physical mechanism and DC/AC stress/recovery modeling of Negative Bias Temperature Instability (NBTI) in p-MOSFETs”, IEEE International Reliability Physics Symposium (IRPS), p.XT-1.1, 2017

• C. Joishi, S. Kothari, S. Ghosh, S. Mukhopadhyay, S. Mahapatra and S. Lodha, “Ultrafast PBTI characterization on Si-free gate last Ge nFETs with stable and ultrathin Al2O3 IL”, IEEE International Reliability Physics Symposium (IRPS), p.5C-5.1, 2017

• H. Y. Wong, S. Motzny, V. Moroz, S. Mishra and S. Mahapatra,“FinFET NBTI degradation reduction and recovery enhancement through hydrogen incorporation and self-heating”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), p.101, 2017

• S. Mahapatra, N. Parihar, S. Mishra; B. Fernandez and A. Chaudhary, “A BTI analysis tool (BAT) to simulate p-MOSFET ageing under diverse experimental conditions”, IEEE Electron Devices Technology and Manufacturing Conference (EDTM), p.111, 2017

• N. Goel, T. Naphade and S. Mahapatra, “Combined trap generation and transient trap occupancy model for time evolution of NBTI during DC multi-cycle and AC stress”, IEEE International Reliability Physics Symposium (IRPS), p.4A.3.1, Monterey, CA, USA, 2015

• N. Agrawal, A. Agrawal, S. Mukhopadhyay, S. Mahapatra and S. Datta, “Electron trapping dominance in strained germanium quantum well planar and FinFET devices with NBTI”, Annual Device Research Conference (DRC), p.283, 2015.

• A. Chaudhary, B. Kaczer, P. J. Roussel, T. Chiarella, N. Horiguchi and S. Mahapatra, “Time dependent variability in RMG-HKMG FinFETs: Impact of extraction scheme on stochastic NBTI”, IEEE International Reliability Physics Symposium (IRPS), p.3B.4.1, Monterey, CA, USA, 2015

• R. Pandey, N. Agrawal, V. Chobpattana, K. Henry, M. Kuhn, H. Liu, M. Labella, C. Eichfeld, K. Wang, J. Maier, S. Stemmer, S. Mahapatra and S. Datta, “Tunnel junction abruptness, source random dopant fluctuation and PBTI induced variability analysis of GaAs0.4Sb0.6/In0.65Ga0.35As heterojunction tunnel FETs”, IEEE International Electron Devices Meeting (IEDM), p.14.2.1, 2015

• S. Mukhopadhyay, K. Joshi, V. Chaudhury, N. Goel, S. De, R. K. Pandey, K. V. R. M. Murali and S. Mahapatra, “Trap Generation in IL and HK layers during BTI / TDDB stress in scaled HKMG N and P MOSFETs”, IEEE International Reliability Physics Symposium (IRPS), Kona, HI, USA, pp.GD.3.1-GD.3.11, 2014

• N. Goel, S. Mukhopadhyay, N. Nanaware, S. De, R. K. Pandey, K. V. R. M. Murali and S. Mahapatra, “A comprehensive DC/AC model for ultra-fast NBTI in deep EOT scaled HKMG p-MOSFETs”, IEEE International Reliability Physics Symposium (IRPS), Kona, HI, USA, pp.6A.4.1-6A.4.12, 2014

• T. Naphade, N. Goel, P. R. Nair, and S. Mahapatra, “Investigation of stochastic implementation of reaction diffusion (RD) models for NBTI related interface trap generation”, IEEE International Reliability Physics Symposium (IRPS), art. no. 6532120, pp. XT.5.1-XT.5.11, Monterey, CA, USA, 2013

• K. Joshi, S. Hung, S. Mukhopadhyay, V. Chaudhary, N. Nanaware, B. Rajamohnan, T. Sato, M. Bevan, A. Wei, A. Noori, B. Mc.Dougal, C. Ni, G. Saheli, C. Lazik, P. Liu, D. Chu, L. Date, S. Datta, A. Brand, J. Swenberg, and S. Mahapatra, “HKMG process impact on N, P BTI: Role of thermal IL scaling, IL/HK integration and post HK nitridation”, IEEE International Reliability Physics Symposium (IRPS), art. no. 6532014, pp. 4C.2.1-4C.2.10., Monterey, CA, USA, 2013

• S. Desai, S. Mukhopadhyay, N. Goel, N. Nanaware, B. Jose, K. Joshi, and S. Mahapatra, “A comprehensive AC / DC NBTI model: Stress, recovery, frequency, duty cycle and process dependence”, IEEE International Reliability Physics Symposium (IRPS), art. no. 6532117, pp. XT.2.1-XT.2.11., Monterey, CA, USA, 2013

• (Invited) S. Mahapatra, N. Goel, and K. Joshi, “A physics based model for NBTI in p-MOSFETs”, International Conference on Solid-State and Integrated Circuit Technology, Proceedings, art. no. 6467688, Xian, China, 2012

• J. Yang, M. Masuduzzaman, K. Joshi, S. Mukhopadhyay, J. Kang, S. Mahapatra, and M. A. Alam, “Intrinsic correlation between PBTI and TDDB degradations in nMOS HK/MG dielectrics”, IEEE International Reliability Physics Symposium (IRPS), art. no. 6241855, pp. 5D.4.1-5D.4.7, Anhaeim, CA, USA, 2012

• K. Joshi, S. Mukhopadhyay, N. Goel, and S. Mahapatra, “A consistent physical framework for N and P BTI in HKMG MOSFETs”, IEEE International Reliability Physics Symposium (IRPS), art. no. 6241840, pp. 5A.3.1-5A.3.10, Anhaeim, CA, USA, 2012

• S. Gupta, B. Jose, K. Joshi, A. Jain, M. A. Alam, and S. Mahapatra, “A comprehensive and critical re-assessment of 2-stage energy level NBTI model”, IEEE International Reliability Physics Symposium (IRPS), art. no. 6241933, pp. XT.3.1-XT.3.6, Anhaeim, CA, USA, 2012

• S. Mahapatra, A. E. Islam, S. Deora, V. D. Maheta, K. Joshi, A. Jain and M. A. Alam, “A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery”, IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2011

• (Invited) S. Mahapatra, A. E. Islam, S. Deora, V. D. Maheta, K. Joshi and M. A. Alam, “Characterization and modeling of NBTI stress, recovery, material dependence and AC degradation using R-D framework”, IEEE Int. Symp. on Physics and Failure of Integrated Circuits (IPFA), Korea, 2011

• S. Deora, V. D. Maheta, and S. Mahapatra, “NBTI lifetime prediction in SiON p-MOSFETs by H/H2 reaction diffusion (RD) and dispersive hole trapping model”, in Proc., Int. Rel. Phys. Symp (IRPS), Anaheim, CA, USA,, p.1105, 2010.

• A. E. Islam, S. Mahapatra, S. Deora, V. D. Maheta and M. A. Alam, “On the differences between ultra-fast NBTI measurements and reaction diffusion theory”, in Proc., IEEE Int. Elect. Dev. Meet. (IEDM), Baltimore, MD, USA, 2009.

• (Invited) S. Mahapatra, V. D. Maheta, S. Deora, E. N. Kumar, S. Purawat, C. Olsen, K. Ahmed, A. E. Islam and M. A. Alam, “Material dependence of negative bias temperature instability (NBTI) stress and recovery in SiON p-MOSFETs”, ECS meeting, San Francisco, CA, USA, 2009.

• G. Kapila, N. Goyal, V. D. Maheta, C. Olsen, K. Ahmed and S. Mahapatra, “A comprehensive study of flicker noise in plasma nitrided SiON p-MOSFETs: Process dependence of pre-existing and NBTI stress generated trap distribution profiles”, in Proc., IEEE Int. Elect. Dev. Meet. (IEDM), San Francisco, CA, USA, 2008.

• (Invited) S. Mahapatra and V. D. Maheta, “Gate insulator process dependent NBTI in SiON p-MOSFETs”, in Proc., Int. Conf. on Solid State and Integrated Circuit Technology (ICSICT), Beijing, China, 2008.

• S. Deora and S. Mahapatra, “A study of NBTI in HfSiON/TiN p-MOSFETs using ultra-fast on-the-fly IDLIN technique”, IEEE Int. Symp. on Physics and Failure of Integrated Circuits (IPFA), Singapore 2008.

• S. Mahapatra, K. Ahmed, D. Varghese, A. E. Islam, G. Gupta, L. Madhav, D. Saha and M. A. Alam, “On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy?”, in Proc., Int. Rel. Phys. Symp (IRPS), Phoenix, AZ, USA, p.1, April 2007.

• A.E. Islam, E. N. Kumar, H. Das, S. Purawat, V. Maheta, H. Aono, E. Murakami, S. Mahapatra, and M.A. Alam, “Theory and Practice of Ultra-fast Measurements for NBTI Degradation: Challenges and Opportunities”, Int. Electron Dev. Meet. (IEDM), Washington DC, USA, Dec 2007.

• E. N. Kumar, V. D. Maheta, S. Purawat, A. E. Islam, C. Olsen, K. Ahmed, M. A. Alam and S. Mahapatra, “Material Dependence of NBTI Physical Mechanism in Silicon Oxynitride (SiON) p-MOSFETs: A Comprehensive Study by Ultra-Fast On-The-Fly (UF-OTF) IDLIN Technique”, Int. Elect. Dev. Meet. (IEDM), Washington DC, USA, Dec 2007.

• A. E. Islam, G. Gupta, S. Mahapatra, A. T. Krishnan, K. Ahmed, F. Nouri, A. Oates and M. A. Alam, “Gate leakage vs. NBTI in plasma nitrided oxides: Characterization, physical principles and optimization”, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.403, 2006.

• P. Bharath Kumar, T. R. Dalei, D. Varghese, D. Saha, S. Mahapatra and M. A. Alam, “Impact of Substrate Bias on p-MOSFET Negative Bias Temperature Instability”, Int. Reliability Phys. Symp (IRPS), San Jose, USA, p.700, 2005.

• (Invited) S. Mahapatra, M. A. Alam, P. Bharath Kumar, T. R. Dalei, D. Varghese and D. Saha, “Negative bias temperature instability in CMOS devices”, Microelectronics Engineering, special issue on INFOS, v.80, p.114, 2005.

• D. Varghese, D. Saha, S. Mahapatra, K. Ahmed, F. Nouri and M. Alam, “On the dispersive versus arrhenius temperature activation of NBTI time evolution in plasma nitrided gate oxides: Measurements, theory and implications”, International Electron Devices Meeting (IEDM), Washington, DC, USA, p.684, Dec 2005.

• (Invited) S. Mahapatra, M. A. Alam, P. Bharath Kumar, T. R. Dalei and D. Saha, “Mechanism of Negative Bias Temperature Instability in CMOS Devices: Degradation, Recovery and Impact of Nitrogen”, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.105, 2004.

• S. Mahapatra, P. Bharath Kumar and M. A. Alam, “A new observation of enhanced bias temperature instability in thin gate oxide p-MOSFET”, Tech. Digest, International Electron Devices Meeting (IEDM), Washington, DC, USA, p.337, 2003.

• S. Mahapatra and M. A. Alam, “A predictive reliability model for PMOS bias temperature degradation”, Tech. Digest, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.505, 2002.

• Uma Sharma, Meng Duan, Himanshu Diwakar, Karansingh Thakor, Hiu Yung Wong, Steve Motzny, Denis Dolgos and Souvik Mahapatra, “TCAD Framework for HCD Kinetics in Low VD Devices Spanning Full VG/VD Space,” in IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4749-4756, November 2020

• S. Mahapatra and U. Sharma, “A Review of Hot Carrier Degradation in n-Channel MOSFETs—Part I: Physical Mechanism,” in IEEE Transactions on Electron Devices, vol. 67, no. 7, pp. 2660-2671, July 2020

• S. Mahapatra and U. Sharma, “A Review of Hot Carrier Degradation in n-Channel MOSFETs—Part II: Technology Scaling,” in IEEE Transactions on Electron Devices, vol. 67, no. 7, pp. 2672-2681, July 2020

• U. Sharma, N. Parihar and S. Mahapatra, “Modeling of HCD Kinetics for Full VG/VD Span in the Presence of NBTI, Electron Trapping, and Self Heating in RMG SiGe p-FinFETs,” in IEEE Transactions on Electron Devices, vol. 66, no. 6, pp. 2502-2508, June 2019

• U. Sharma and S. Mahapatra, “A SPICE Compatible Compact Model for Hot-Carrier Degradation in MOSFETs Under Different Experimental Conditions,” IEEE Transactions on Electron Devices, vol. 66, no. 2, pp. 839–846, Feb. 2019.

• S. Mahapatra and R. Saikia, “On the Universality of Hot Carrier Degradation: Multiple Probes, Various Operating Regimes, and Different MOSFET Architectures,” IEEE Transactions on Electron Devices, vol. 65, no. 8, pp. 3088–3094, Aug. 2018.

• D. Saha, D. Varghese and S. Mahapatra, “On the Generation and Recovery of Hot Carrier Induced Interface Traps: A critical examination of the 2D Reaction Diffusion model”, IEEE Electron Devices Lett., v.27, p.188, 2006.

• D. Saha, D. Varghese and S. Mahapatra, “The role of Anode Hole Injection and Valence Band Hole Tunneling on interface trap generation during hot carrier injection stress”, IEEE Electron Devices Lett., p.585, 2006.

• S. Mahapatra, D. Saha, D. Varghese and P. Bharath Kumar, “On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN and HCI stress”, IEEE Trans. Electron Devices, p.1583, 2006.

• K. G. Anil, S. Mahapatra and I. Eisele, “A detailed experimental investigation of impact ionization in n-channel metal-oxide-semiconductor field-effect-transistors at very low drain voltages”, Solid State Electron, v.47, p.995, 2003.

• K. G. Anil, S. Mahapatra and I. Eisele, “Electron-electron interaction signature peak in the substrate current vs gate voltage characteristics of n-channel silicon MOSFETs”, IEEE Trans. Electron Devices v.49, p.1283, 2002.

• K. G. Anil, S. Mahapatra, V. R. Rao and I. Eisele, “Comparison of sub-bandgap impact ionization in deep-submicron conventional and lateral asymmetric channel n-MOSFETs”, Jpn. J. Appl. Phys., v.40, p-I, no.4B, p.2621, April 2001.

• K. G. Anil, S. Mahapatra and I. Eisele, “Observation of double peak in the substrate current versus gate voltage characteristics in n-channel MOSFETs”, Appl. Phys. Lett., v.78, no.15, p.2238, April 2001.

• K. G. Anil, S. Mahapatra and I. Eisele, “Experimental verification of the nature of the high energy tail in the electron energy distribution in n-channel MOSFETs”, IEEE Electron Devices Lett., v.22, p.478, Oct. 2001.

• S. Mahapatra, V. R. Rao, B. Cheng, M. Khare, C. D. Parikh, J. C. S. Woo and J. Vasi, “Performance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor Deposited Si3N4 MNSFETs”, IEEE Trans. Electron Devices, v.48, p.679, April 2001.

• S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S. Woo, “A study of hot-carrier induced interface trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping technique”, Solid State Electron, v.45, p.1717, 2001.

• S. Mahapatra, C. D. Parikh, V. R. Rao, C. R. Viswanathan and J. Vasi, “A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique”, IEEE Trans. Electron Devices, v.47, p.171, Jan 2000.

• S. Mahapatra, C. D. Parikh, V. R. Rao, C. R. Viswanathan and J. Vasi, “Device scaling effects on hot-carrier induced interface and oxide trapped charge distributions in MOSFETs”, IEEE Trans. Electron Devices, v.47, p.789, April 2000.

• S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S. Woo, “A study of 100 nm channel length asymmetric channel MOSFET by using charge pumping”, Microelectronics Engineering, v.48, p.193, Sept 1999.

• S. Mahapatra, C. D. Parikh, J. Vasi, V. R. Rao and C. R. Viswanathan, “A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs”, Solid State Electron, v.43, p.913, June 1999.

• S. Mahapatra, C. D. Parikh and J. Vasi, “A new 'multifrequency' charge pumping technique to profile hot-carrier induced interface-state density in n-MOSFETs”, IEEE Trans. Electron Devices, v.46, p.960, May 1999.

• U. Sharma and S. Mahapatra, “A TCAD Framework for Assessing NBTI Impact Under Drain Bias and Self-Heating Effects in Replacement Metal Gate (RMG) p-FinFETs,” 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kobe, Japan, 2020, pp. 121-124

• W. Chakraborty, U. Sharma, S. Datta and S. Mahapatra, “Hot Carrier Degradation in Cryo-CMOS,” 2020 IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA, 2020, pp. 1-5,

• U. Sharma and S. Mahapatra, “A SPICE Compatible Compact Model for Process and Bias Dependence of HCD in HKMG FDSOI MOSFETs,” 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Udine, Italy, 2019, pp. 1-4,

• N. R. Mohapatra, S. Mahapatra and V. R. Rao, “The study of damage generation in n-channel MOS transistors operating in the substrate enhanced gate current regime”, Proceedings, 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p. 27, 2002.

• N. R. Mohapatra, S. Mahapatra, V. R. Rao, ““Study of Degradation in Channel Initiated Secondary Electron Injection Regime”, Proceedings, 31st European Solid-State Device Research Conference (ESSDERC), 11 - 13 September 2001, Nuremberg, Germany, p. 2001.

• N. R. Mohapatra, S. Mahapatra and V. R. Rao, “A Comparative Study of Degradation for n-MOSFET's in CHE and CHISEL Injection Regime”, Proceedings, 11th International Workshop on The Physics of Semiconductor Devices, New Delhi, India, p., 2001

• G. Shrivastav, S. Mahapatra, V. R. Rao, J. Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele, “Performance Optimization of 60 nm Channel Length Vertical MOSFETs Using Channel Engineering”, Proceedings, 14th IEEE VLSI Design Conference, Bangalore, India, p.475, 2001.

• Anil K. G., S. Mahapatra and I. Eisele, “Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETs”, Tech. Digest, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.675, 2000.

• S. Mahapatra, V. R. Rao, J. Vasi, B. Cheng, and J.C.S. Woo, “Reliability Studies on Sub 100 nm SOI-MNSFETs”, International Integrated Reliability Workshop (IRW), Stanford, CA, USA, 2000.

• V. R. Rao, S. Mahapatra, J. Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele, “Hot-carrier performance of 60 nm channel length delta-doped vertical MOSFETs with high-pressure grown oxide as a gate dielectric”, 30th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, California, USA, 2000.

• Anil K. G., S. Mahapatra, I. Eisele, V. R. Rao and J. Vasi, “Drain bias dependence of gate oxide reliability in conventional and asymmetrical channel MOSFETs in the low voltage regime”, Proceedings, 30th European Solid State Device Research Conference (ESSDERC), Cork, Ireland, p.124, 2000.

• S. Mahapatra, V. R. Rao, K. N. ManjulaRani, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo, “100 nm channel length MNSFETs using a Jet Vapor Deposited ultra-thin silicon nitride gate dielectric”, Tech. Digest, International Symposium on VLSI Technology, Kyoto, Japan, p.79, 1999.

• S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo, “Hot-carrier induced interface degradation in Jet Vapor Deposited SiN MNSFETs as studied by a novel charge pumping technique”, Proceedings, 29th European Solid State Device Research Conference (ESSDERC), Leuven, Belgium, p.592, 1999.

• S. Mahapatra, K. N. ManjulaRani, V. R. Rao and J. Vasi, ‘ULSI MOS transistors with Jet Vapor Deposited (JVD) silicon nitride for the gate insulator”, Proceedings, 10th International Workshop on Physics of Semiconductor Devices (IWPSD), New Delhi, India, p., 1999.

• S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S. Woo, “Hot-carrier induced interface trap distributions in conventional and asymmetric channel MOSFETs as determined by a novel charge pumping technique”, 29th IEEE Semiconductor Interface Specialists Conf. (SISC), South Carolina, USA, 1999.

• S. Mahapatra, C. D. Parikh and J. Vasi, “A reliable approach to determine hot-carrier induced interface state distribution in n-MOSFET using charge pumping”, Proceedings, International Conference on Computers and Devices for Communication (CODEC), Calcutta, India, p. 373, 1998.

• S. Mahapatra, C. D. Parikh and J. Vasi, “A new technique to profile hot-carrier induced interface-state generation in n-MOSFETs using charge pumping”, Proceedings, 9th International Workshop on Physics of Semiconductor Devices (IWPSD), New Delhi, India, p. 1030, 1997.

• A. Thirunavukkarasu, H. Amrouch, J. Joe, N. Goel, N. Parihar, S. Mishra, C. K. Dabhi, Y. S. Chauhan, J. Henkel, and S. Mahapatra, “Device to Circuit Framework for Activity-Dependent NBTI Aging in Digital Circuits,” IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 316–323, Jan. 2019.

• S. Mishra, H. Amrouch, J. Joe, C. K. Dabhi, K. Thakor, Y. S. Chauhan, J. Henkel, and S. Mahapatra, “A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications: Device Degradation to Circuit-Level Interaction,” IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 271–278, Jan. 2019.

• S. Salamin, V. M. Van Santen, H. Amrouch, N. Parihar, S. Mahapatra and J. Henkel, “Modeling the Interdependences Between Voltage Fluctuation and BTI Aging”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 7, pp. 1652-1665, 2019

• S. Mishra, N. Parihar, A. R, C. K. Dabhi, Y. S. Chauhan, and S. Mahapatra, “NBTI-Related Variability Impact on 14-nm Node FinFET SRAM Performance and Static Power: Correlation to Time Zero Fluctuations,” IEEE Transactions on Electron Devices, vol. 65, no. 11, pp. 4846–4853, Nov. 2018.

• S. Mishra and S. Mahapatra, “On the Impact of Time-Zero Variability, Variable NBTI, and Stochastic TDDB on SRAM Cells”, IEEE Trans. Electron Devices, p.2764, v.63, 2016

• U. Sharma, C. Pasupuleti, N. Gangwar, A. Thirunavukkarasu and S. Mahapatra, “A Cycle-by-Cycle HCD and BTI Compact Model to Calculate FinFET Based RO Ageing Using SPICE,” 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Penang, Malaysia, 2020, pp. 1-4

• V. M. van Santen et al., “BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array – including Sense Amplifiers and Write Drivers – under Processor Activity,” 2020 IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA, 2020, pp. 1-7

• H. Amrouch, S. Mishra; V. van Santen, S. Mahapatra and J. Henkel, “Impact of BTI on dynamic and static power: From the physical to circuit level”, IEEE International Reliability Physics Symposium (IRPS), p.CR-3.1, 2017

• V. M. van Santen, H. Amrouch; N. Parihar, S. Mahapatra and J. Henkel, “Aging-aware voltage scaling”, Design, Automation & Test in Europe Conference & Exhibition (DATE), p.576, 2016.

• N. Goel, P. Dubey, J. Kawa and S. Mahapatra, “Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages”, IEEE International Reliability Physics Symposium (IRPS), p.CA.5.1, Monterey, CA, USA, 2015

• S. Mahapatra, V. Huard, A. Kerber, V. Reddy, S. Kalpat and A. Haggag, “Universality of NBTI - From devices to circuits and products”, IEEE International Reliability Physics Symposium (IRPS), Kona, HI, USA, pp.3B.1.1-3B.1.8, 2014

• T. Naphade, P. Verma, N. Goel and S. Mahapatra, “DC / AC BTI variability of SRAM circuits simulated using a physics-based compact model”, IEEE International Reliability Physics Symposium (IRPS), Kona, HI, USA, pp.CA.2.1-CA.2.8, 2014

• T. Naphade, K. Roy and S. Mahapatra, “A novel physics-based variable NBTI simulation framework from small area devices to 6T SRAM”, IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, p.33.6.1, 2013

• Y. N. Chen, K. E. J. Goh, X. Wu, Z. Z. Lwin, P. K. Singh, S. Mahapatra, and K. L. Pey, “Temperature-dependent relaxation current on single and dual layer Pt metal nanocrystal-based Al2O3/SiO2 gate stack”, Journal of Applied Physics, 112 (10), art. no. 104503, 2012

• Z. Z. Lwin, K. L. Pey, Q. Zhang, M. Bosman, Q. Liu, C. L. Gan, P. K. Singh, and S. Mahapatra, “Study of charge distribution and charge loss in dual-layer metal-nanocrystal-embedded high-κ/SiO2 gate stack”, Applied Physics Letters, 100 (19), art. no. 193109, 2012

• Z. Z. Lwin, K. L. Pey, N. Raghavan, Y. Chen and S. Mahapatra, “New leakage mechanism and dielectric breakdown later detection in metal nanocrystal embedded dual layer memory gate stack”, IEEE Electron Dev. Lett., v.32, no.6, pp.800-802, 2011

• Y. N. Chen, K. L. Pey, K. E. J. Goh, Z. Z. Lwin, P. Singh and S. Mahapatra, “Study of automatic recovery on the metal nanocrystal based Al2O3/SiO2 gate stack”, Appl. Phys. Lett., v.98, 083504, 2011

• Z Z Lwin, K. L. Pey, C. Liu, Q. Zhang, Y. N. Chen, P. K. Singh and S. Mahapatra, “Localized charge trapping and lateral charge diffusion in metal nanocrystal embedded High-k/SiO2 stack”, Appl. Phys. Lett., v.99 (22), 222102-222102-3, 2011

• P. K. Singh, G, Bisht, K. Auluck, M. Shivatheja, R. Hofmann, K. K. Singh and S. Mahapatra, “Performance and reliability study of single layer and dual layer Platinum nanocrystal Flash memory devices under NAND operation”, to appear, IEEE Trans. Electron Devices, 2010.

• Y. N. Chen, K. L. Pey, K. E. J. Goh, Z. Z. Lwin, P. K. Singh and S. Mahapatra, “Tri-level resistive switching in metal nanocrystal based Al2O3/SiO2 gate stack”, IEEE Trans. Electron Devices, v.57, no.11, pp.3001-3005, 2010

• C. Sandhya, A. B. Oak, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, “Study of P/E cycling endurance induced degradation in SANOS memories under NAND (FN/FN) operation”, IEEE Trans. Electron Devices, v.57, p.1548, 2010.

• C. Sandhya, A. B. Oak, N. Chattar, A. S. Joshi, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, “Impact of SiN composition variation on SANOS memory performance and reliability under NAND (FN/FN) operation”, IEEE Trans. Electron Devices, v.56, p.3123, 2009.

• P. K. Singh, R. Hofmann, G. Bisht, K. K. Singh, N. Krishna and S. Mahapatra, “Performance and reliability of Au and Pt single layer metal nanocrystal flash memory under NAND (FN/FN) operation”, IEEE Trans. Electron Devices, v.56, p.2065, 2009.

• C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, “Effect of SiN on performance and reliability of charge trap flash (CTF) under Fowler-Nordheim tunneling program/erase operation”, IEEE Electron Dev. Lett., v.30, p.171, 2009.

• P. K. Singh, G. Bisht, R. Hofmann, K. Singh, N. Krishna, and S. Mahapatra, “Metal nanocrystal memory with Pt single and dual layer NC with low leakage Al2O3 blocking dielectric”, IEEE Electron Dev. Lett., v.29, p.1389, 2008.

• P. Singh, C. Sandhya, K. Auluck, G. Bisht, M. Shivatheja, R. Hofmann, G. Mukhopadhyay and S. Mahapatra, “Applicability of dual layer metal nanocrystal flash memory for NAND 2 or 3-bit/cell operation: Understanding the anomalous breakdown and optimization of P/E conditions”, in Proc., Int. Rel. Phys. Symp, p.981, Anaheim, USA, p.981, 2010.

• Z. Z. Lwin, K. L. Pey, Y. N. Chen, P. K. Singh and S. Mahapatra, “Charging and discharging characteristics of metal nanocrystals in degraded dielectric stack”, in Proc., Int. Rel. Phys. Symp, p.981, Anaheim, USA, p.89, 2010.

• (Invited) S. Mahapatra and P. K. Singh, “Metal/high-k/metal nanocrystal gate stacks for NAND flash applications”, ECS meeting, Vienna, Austia, 2009.

• P. K. Singh, G. Bisht, M. Sivatheja, C. Sandhya, R. Hofmann, K. Singh, N. Krishna, G. Mukhopadhyay, and S. Mahapatra, “Reliability of SL and DL Pt NC devices for NAND Flash applications: A 2 region model for endurance defect generation”, in Proc., Int. Rel. Phys. Symp, p. 301, Montreal, Canada, 2009.

• P. K. Singh, G. Bisht, R. Hofmann, K. Singh and S. Mahapatra, “Dual layer Pt metal NC Flash for MLC NAND application”, in Proc., Int. Memory Workshop, p. 78, Monterey, CA, USA, 2009.

• P. K. Singh, K. K. Singh, R. Hofmann, K. Armstrong, N. Krishna and S. Mahapatra, “Au nanocrystal flash memory reliability and failure analysis”, Int. Phys. Failure Analysis conf., Singapore 2008.

• Sandhya C, U. Ganguly, K.K. Singh, C. Olsen, S. M. Seutter, G. Conti, K. Ahmed, N. Krishna, J. Vasi and S. Mahapatra, “The Effect of Band Gap Engineering of the Nitride Storage Node on Performance and Reliability of Charge Trap Flash”, Int. Phys. Failure Analysis conf., Singapore 2008.

• Sandhya C, U. Ganguly, K.K. Singh, P.K. Singh, C. Olsen, S. M. Seutter, R. Hung, G. Conti, K. Ahmed, N. Krishna, J. Vasi, and S. Mahapatra, “Nitride engineering and the effect of interfaces on charge trap flash performance and reliability”, Int. Rel. Phys. Symp. (IRPS), Phoenix, AZ, USA 2008.

• A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, “Development of A 3D Simulator for Metal Nanocrystal (NC) Flash Memories under NAND Operation”, Int. Elect. Dev. Meet. (IEDM), Washington DC, USA, Dec 2007.

• A. Paul, Ch. Sridhar, S. Gedam and S. Mahapatra, “Comprehensive simulation of program, erase and retention in charge trapping flash memories”, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.393, Dec 2006.

• A. Datta and S. Mahapatra, “A comprehensive analysis on scaling prospects of dual-bit channel engineered SONOS NOR-flash EEPROM cells”, Solid State Electron., v.54, p.397, 2010.

• A. Datta, R. Asnani and S. Mahapatra, “A novel gate assisted reverse read scheme to control bit coupling and read disturb for multibit/cell operation in deeply scaled split-gate SONOS flash EEPROM cells”, IEEE Electron Dev. Lett., v.30, p.885, 2009.

• P. Bharath Kumar, R. Sharma, P. R. Nair and S. Mahapatra, “Investigation of drain disturb in SONOS Flash EEPROMs”, IEEE Trans. Electron Devices, v.54, p.98, 2007.

• A. Datta, P. Bharath Kumar and S. Mahapatra, “Dual-bit/Cell SONOS Flash EEPROMs: Impact of Channel Engineering on Programming Speed and Bit Coupling Effect”, IEEE Electron Dev. Lett., p.446, v.28, 2007.

• P. Bharath Kumar, D. Nair and S. Mahapatra, “Using Soft Secondary Electron Programming to reduce Drain Disturb in Floating Gate NOR Flash EEPROMs”, IEEE Trans. Device and Materials Reliability, v.6, p.81, 2006.

• P. Bharath Kumar, P. R. Nair, R. Sharma, S. Kamohara and S. Mahapatra, “Lateral profiling of trapped charge in SONOS Flash EEPROMs programmed using channel hot electron injection”, IEEE Trans. Electron Devices, v.53, p.698, 2006.

• P. Bharath Kumar, E. Murakami, S. Kamohara, and S. Mahapatra, “Endurance and Retention Characteristics of SONOS EEPROMs operated using BTBT Induced Hot Hole Erase”, Int. Reliability Phys. Symp (IRPS), San Jose, USA, p., 2006.

• P. Bharath Kumar, Ravinder Sharma, Pradeep R. Nair, Deleep R. Nair, S. Kamohara, S. Mahapatra, and J. Vasi, “Mechanism of drain disturb in SONOS Flash EEPROMs”, Int. Reliability Phys. Symp (IRPS), San Jose, USA, p.186, 2005.

• P. Bharath Kumar, D. R. Nair, and S. Mahapatra, “Soft Secondary Electron Programming for Floating Gate NOR Flash EEPROMs”, International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p.146, 2005.

• K. Sridhar, P. Bharath Kumar, S. Mahapatra, E. Murakami , and S. Kamohara, “Controlling Injected Electron and Hole Profiles for Better Reliability of Split Gate SONOS “, International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p.190, 2005.

• P. Bharath Kumar, Ravinder Sharma, E. Murakami , S. Kamohara, and S. Mahapatra, “Effect of Compensation Implant in SONOS Flash EEPROMs”, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, p.644, 2005.

• P. R. Nair, P. Bharath Kumar, R. Sharma, S. Kamohara and S. Mahapatra, “A Comprehensive Trapped Charge Profiling Technique for SONOS Flash EEPROMs”, Proceedings, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.403, 2004.

• D. R. Nair, S. Mahapatra, S. Shukuri and J. Bude, “Explanation of P/E Cycling Impact on Drain Disturb in Flash EEPROMs under CHE and CHISEL Programming Operation”, IEEE Trans. Electron Devices, v.52, p.534, 2005.

• D. R. Nair, N. R. Mohapatra, S. Mahapatra, S. Shukuri and J. Bude, “Effect of P/E cycling on drain disturb in Flash EEPROMs under CHE and CHISEL operation”, IEEE Trans. Device and Materials Reliability, v.4, p.32, 2004.

• D. R. Nair, S. Mahapatra, S. Shukuri and J. Bude, “Drain disturb during CHISEL programming of NOR Flash EEPROMs – Physical mechanisms and impact of technological parameters”, IEEE Trans. Electron Devices, v.51, p.701, 2004.

• D. R. Nair, S. Mahapatra and S. Shukuri, “Cycling endurance of NOR Flash EEPROM cells under CHISEL programming operation - Impact of technological parameters and scaling”, IEEE Trans. Electron Devices, v.51, p.1672, 2004.

• N. R. Mohapatra, D. R. Nair, S. Mahapatra, V. R. Rao, S. Shukuri and J. Bude, “CHISEL programming operation of scaled NOR Flash EEPROMs – Effect of voltage scaling, device scaling and technological parameters”, IEEE Trans. Electron Devices, v.50, p.2104, 2003.

• S. Mahapatra, S. Shukuri and J. Bude, “CHISEL flash EEPROM part-I: performance and scaling”, IEEE Trans. Electron Devices, v.49, p.1296, 2002.

• S. Mahapatra, S. Shukuri and J. Bude, “CHISEL flash EEPROM part-II: reliability”, IEEE Trans. Electron Devices, v.49, p.1302, 2002.

• D. R. Nair, S. Mahapatra, S. Shukuri and J. Bude, “Multi-Level Programming of NOR Flash EEPROMs by CHISEL Mechanism”, Proceedings, Int. Reliability Phys. Symp (IRPS), Phoenix, USA, p.635, 2004.

• S. Mahapatra, S. Shukuri and J. Bude, “Substrate bias effect on cycling induced performance degradation of scaled flash EEPROMs”, Proceedings, 16th IEEE VLSI Design Conference, New Delhi, India, p.223, 2003.

• N. R. Mohapatra, S. Mahapatra, V. R. Rao, S. Shukuri and J. Bude, “Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs”, Proceedings, Int. Reliability Phys. Symp (IRPS), Dallas, USA, p.518, 2003.

• D. R. Nair, N. R. Mohapatra, S. Mahapatra, S. Shukuri and J. Bude, “The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMs”, Proceedings, 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p.164, 2003.

• N. R. Mohapatra, D. R. Nair, S. Mahapatra, V. R. Rao and S. Shukuri, “The Impact of Channel Engineering on the Performance Reliability and Scaling of CHISEL NOR Flash EEPROMs”, Proceedings, 33rd European Solid State Device Research Conference (ESSDERC), Lisbon, Portugal, p.541, 2003.

• D. R. Nair, N. R. Mohapatra, S. Mahapatra and S. Shukuri, “The Impact of Technology Parameters and Scaling on the Programming Performance and Drain Disturb in CHISEL Flash EEPROMs”, Proceedings, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, p.644, 2003.

• N. R. Mohapatra, S. Mahapatra and V. R. Rao, “Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors”, 2002 MRS Spring Meeting, San Francisco, CA, USA, April 1-5, 2002.

• S. Mahapatra, S. Shukuri and J. Bude, “Performance and reliability of high-density flash EEPROMs under CHISEL programming operation”, Proceedings, 32nd European Solid-State Device Research Conference (ESSDERC), Florence, Italy, p., 2002.

• S. Dongaonkar, S. Mahapatra and M. A. Alam, “Physics and statistics of non-ohmic shunt conduction and metastability in amorphous silicon p-i-n solar cells”, IEEE Journal of Photovoltaics, 1 (2), 111-117, 2011

• S. Dongaonkar, Y. Karthik, D. Wang, M. Frei, S. Mahapatra and M. A. Alam, “On the nature of shunt leakage in amorphous silicon pin solar cells”, IEEE Electron Dev. Lett., v.31, no.11, pp.1266-1268, 2010

• S. Dongaonkar, M. A. Alam, Y. Karthik, S. Mahapatra, D. Wang and M. Frei, “Identification, characterization and implications of shadow degradation in thin film solar cells”, IEEE International Reliability Physics Symposium (IRPS), p. 3.1-6A, Monterey, CA, USA, 2011

• S. Dongaonkar, S. Mahapatra and M. A. Alam, “A physical model for non ohmic shunt conduction and metastability in amorphous silicon pin solar cells”, IEEE Photovoltaic Specialists Conference, 2011