Udayan Ganguly

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Citation Indices

Udayan's Google Scholar Citation Index
h-index: 18
i10-index: 33

Current Research Interests

My overall interest is in experimental device physics with modeling/design

  • Resistance Random Access Memory RRAM- materials, devices - fabrication, characterization and modeling (with S. Lodha, B. Rajendran, N. Venkataramani)
  • Advanced Logic Device Engineering - FinFET devices - design, fabrication, characterization and modeling (with S. Lodha, S. Ganguly, A. Laha, and S. Mahapatra)
  • Neuromorphic Engineering (with B. Rajendran)

Academic Background

  • Ph.D. Materials Science and Engineering Cornell University, 2006
  • M.S., Materials Science and Engineering Cornell University, 2005
  • B. Tech., Metallurgical Engineering Indian Institute of Technology Madras (IITM), 2000

Independent News Coverage

  • 21st Aug 2017: https://indiaeducationdiary.in: IIT Bombay SCL develops BJT for 180nm CMOS baseline to enable BiCMOS link
  • 25th Sept 2017: The Telegraph India Home Remedies: The first indigenous smartchip — used to power the Internet of Things — has been designed in IIT Bombay. Prasun Chaudhuri on its implications link
  • 24th Oct 2017: Deccan Herald Applications of a new semiconductor device - High-frequency circuits: Researchers have developed a BJT that can work with Bi-CMOS link
  • 24th Oct 2017: Research Matters @ Gubbilabs “A made-in-India transistor that can make India’s IoT technology a reality” link
  • 28th Oct 2017: The Hindu “IIT Bombay makes analog device that mimics neurons link

Awards

  • Dr. P. K. Patwardhan Technology Development Award 2017 - for Development of Strategic Semiconductor Technologies (Team Members: S Sadana, P. Bhatt, A. Lele, S. Ganguly, and U. Ganguly)
  • Intel Ph.D. Fellowship awarded to Sandip Lashkare for the proposal titled “Spiking Neural Network Architecture Hardware Design with Nanoscale Synapse for Supervised and Unsupervised Learning” in 2018.
  • Intel India Ph. D. Fellowship to Vinay Sangwan based on the proposal “Neuromorphic computing architecture based low power, high-density CMOS-compatible device” in 2015
  • Best Paper (IEEE INDICON 2013, Mumbai)
  • Employee of the Quarter, Front End Products, Applied Materials 2010
  • Outstanding Paper Award at IEEE Intl. Workshop on Electron Devices and Semiconductor Technology (IEDST) 2009
  • MRS Trophy Award for best manuscript in Symposium D (MRS Fall 2004, Boston)

Courses Taught

  • 2010 Fall EE236 Electronic Devices Lab
  • 2011 Spring EE214 Digital Circuits Lab
  • 2011 Fall EE236 Electronic Devices Lab
  • 2012 Spring EE620 Physics of Transistors
  • 2012 Fall EE101 Introduction to Electrical Engineering
  • 2013 Spring EE620 Physics of Transistors
  • 2013 Fall EE101 Introduction to Electrical Engineering
  • 2014 Spring EE620 Physics of Transistors
  • 2014 Fall EE101 Introduction to Electrical Engineering
  • 2015 Spring EE620 Physics of Transistors
  • 2015 Spring EE669 VLSI Technology
  • 2016 Spring EE620 Physics of Transistors
  • 2016 Spring EE669 VLSI Technology
  • 2017 Spring EE620 Physics of Transistors
  • 2017 Spring EE746 Neuromorphic Engineering
  • 2018 Spring EE620 Physics of Transistors
  • 2018 Spring EE746 Neuromorphic Engineering

Books and Book Chapters

U Ganguly, B Rajendran, “Novel Biomimetic Si Devices for Neuromorphic Computing Architecture” in Advances in Neuromorphic Hardware Exploiting Emerging Nanoscale Devices Editors: Suri, Manan (Ed.), Springer 2017

Journal Publications

  1. S. Dutta, T. Bhattacharya, N. Moha patra, M.Suri, U. Ganguly “Transient Variability in SOI based LIF Neuron and Impact on Unsupervised Learning”, IEEE Transaction of Electron Devices, 2018
  2. Amita, S. Mittal, U.Ganguly, “The First Compact Model to Determine VT-distribution for DG-FinFET due to LER” IEEE Transaction of Electron Devices, 2018
  3. S. Lashkare, P. Kumbhare, V. Saraswat, U. Ganguly “Transient Joule Heating based Oscillator Neuron for Neuromorphic Computing”IEEE Electron Devices Letters 2018 link
  4. B. Das, J. Schulze, U. Ganguly “Transient Phenomena in Sub-Band Gap Impact Ionization in Si NIPIN Diode” IEEE Transactions on Electron Devices 2018 link
  5. P. Harsha Vardhan, S. Mittal, S. Ganguly, U. Ganguly, “Analytical Modeling of Metal Gate Granularity based Threshold Voltage Variability in NWFET” Solid State Electronics 2018 link
  6. S. Sadana, A. Lele, S. Tsundus, P. Kumbhare, U. Ganguly”A Highly Reliable and Unbiased PUF based on Differential OTP memory” IEEE Electron Devices Letters 2018 link
  7. A. Shukla, U. Ganguly, " An On-chip Trainable and Clock-less Spiking Neural Network with 1R Memristive Synapses,” IEEE Transactions on Biomedical Circuits and Systems (TBioCAS) 2018 link.
  8. P. Kumbhare, U Ganguly “Ionic Transport Barrier Tuning by Composition in Pr1-xCaxMnO3-Based Selector-less RRAM and its Effect on Memory Performance” IEEETrans on Electron Devices 2018 link
  9. S. Lashkare, S. Chouhan, T. Chavan, A. Bhat, P. Kumbhare, U. Ganguly”PCMO RRAM for Integrate-and-Fire Neuron in Spiking Neural Networks” IEEE Electron Devices Letters 2018 link 34th most popular papers in IEEE TED in March 2018
  10. S. Dutta, V. Kumar, A. Shukla , N. R. Mohapatra, and U. Ganguly, “Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET” Scientific Reports 2017, link
  11. P. Kumbhare, I. Chakraborty, A. Khanna, U. Ganguly “Memory Performance of a Simple Pr0.7Ca0.3MnO3 Based Selectorless RRAM” IEEE Transactions on Electron Device, 2017 link
  12. S. Lashkare, N. Panwar, P. Kumbhare, B. Das and U. Ganguly “PCMO based RRAM and NPN Bipolar Selector as Synapse for Energy Efficient STDP” IEEE Electron Devices Letters, 2017 (accepted) link 30th most popular papers in IEEE TED in Jun 2017
  13. P Harsha Vardhan, S. Mittal, S. Ganguly, and U. Ganguly “Analytical Estimation of Threshold Voltage Variability by Metal Gate Granularity in FinFET” IEEE Transactions on Electron Device, 2017 link 17th most popular papers in IEEE TED in Jun 2017
  14. S. Mittal, Amita, S. Ganguly, U. Ganguly, “Analytical Model to estimate FinFET’s ION, IOFF, SS and VT distribution due to FER” IEEE Transactions on Electron Device, 2017 (accepted) link
  15. N. Panwar, B. Rajendran, and U. Ganguly,”Arbitrary Spike Time Dependent Plasticity (STDP) in Memristor by Analog Waveform Engineering” IEEE Electron Devices Letters, 2017 link 27th most popular papers in IEEE TED in Jun 2017
  16. Amita, S. Mittal, U. Ganguly, “An Analytical Model to Estimate VT Distribution of Partially Correlated Fin Edges in FinFETs due to Fin-Edge Roughness” IEEE Transactions on Electron Device, 2017 link
  17. N. Panwar, A. Khanna, I. Chakraborty, P. Kumbhare, and U. Ganguly, “Self-Heating during submicrosecond Current Transients in Pr0.7Ca0.3MnO3 (PCMO) Based RRAM” IEEE Transactions on Electron Device, 2017 link Top 25 most popular papers in IEEE TED in Jan 2017
  18. B. Das, Sushama, J. Schulze, U. Ganguly, “Sub-0.2V Impact Ionization in Si NIPIN Diode” IEEE Transactions on Electron Device, 2016 link .Top 40 most popular papers in IEEE TED in Nov 2016
  19. Anmol Biswas, Sidharth Prasad, Sandip Lashkare, Udayan Ganguly “A simple and efficient SNN and its performance & robustness evaluation method to enable hardware implementation” ArXiv 2016 pre-print link
  20. S. Kurude, S. Mittal, U. Ganguly, “Statistical Variability Analysis of SRAM Cell for Emerging Transistor Technologies” IEEE Transactions on Electron Device, 2016 link Top 2 most popular papers in IEEE TED in Aug 2016
  21. S. Mittal, A. Shekhawat, U. Ganguly “An Analytical Model to estimate FinFET’s VT distribution due to Fin Edge Roughness” IEEE Transactions on Electron Device, 2016 link
  22. R.Mandapati, S. Shrivastava, S. Vatsa, B. Saha, J. Schulze, U. Ganguly, “Improved Off-Current and Modeling in sub-430°C Si p-i-n Selector for Unipolar Resistive Random Access Memory” IEEE Electron Devices Letters, pp. 1310 - 1313, 2015 link
  23. S. Mittal, S. Gupta, A. Nainani, M.C. Abraham, K. Schuegraf, S. Lodha, and U. Ganguly “Epitaxially Defined (ED) FinFET: Variability Resistant and High Performance Technology”, IEEE Trans. Elec. Dev., 2014 link Among top 8 most accessed papers in IEEE TED in Aug 2014
  24. Rajashree Nori, S. N. Kale, U. Ganguly, N. R. C. Raju, D. S. Sutar, R. Pinto and V. R Rao, Morphology and Curie temperature engineering in crystalline La0.7Sr0.3MnO3 films on Si by pulsed laser deposition, J. Appl. Phys. 115, 033518 (2014). link
  25. R. Mandapati, A. Borkar, V. S. S. Srinivasan, P. Bafna, P. Karkare, S. Lodha, B. Rajendran, and U. Ganguly, “On Pairing of Bipolar RRAM Memory with NPN Selector based on Set/Reset Array Power Considerations”, IEEE Trans. Nanotechnology (2013) link
  26. R. Mandapati, A. Borkar, V. S. S. Srinivasan, P. Bafna, P. Karkare,S. Lodha, U. Ganguly, “The Impact of n-p-n Selector-Based Bipolar RRAM Cross-Point on Array Performance”, IEEE Transactions on Electron Device 2013 link
  27. S. Sant, S. Lodha, U. Ganguly, S. Mahapatra, F. O.Heinz, L. Smith, V. Moroz and S. Ganguly, “Band gap bowing and band offsets in relaxed and strained Si1-x Gex alloys by employing a novel nonlinear interpolation scheme”, Journal of Applied Physics 113, 033708 (2013). link
  28. P. Paramhans, R. K. Mishra, V. P. Kishore, P. Ray, A. Nainani, Y.-C. Huang, M. C. Abraham, U. Ganguly and S. Lodha, “Fermi-level unpinning and low resistivity in contacts to n-type Ge with a thin ZnO interfacial layer”, to appear in Applied Physics Letters, 2012 link
  29. V. S. S. Srinivasan, S. Chopra, P. Karkare, P. Bafna, S. Lashkare, P. Kumbhare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, U. Ganguly, “Punch-through Diode based Bipolar RRAM Selector by Si Epitaxy”, IEEE Electron Devices Letters, v. 33 , pp. 1396, 2012 link.
  30. V. P. Kishore, P. Paramahans, S. Sadana, U. Ganguly, and S. Lodha, “Nanocrystal-based Ohmic contacts on n and p-type germanium”, Appl. Phys. Lett. 100, 142107, 2012 link
  31. U. Ganguly, T. Guarini, D. Wellekens, L. Date, Y. Cho, A. Rothschild, J. Swenberg, “Impact of Top-Surface Tunnel Oxide Nitridation on Flash Memory Performance and Reliability,” IEEE Electron Device Letters , v.31, pp.123-125, 2010 link.
  32. C. Sandhya, A. B. Oak, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, ‘Study of Endurance Induced Degradation Mechanism in SANOS Memories under NAND (FN/FN) Operation’, IEEE Transactions on Electron Devices link.
  33. C. Sandhya, A. B. Oak, A.S. Joshi, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, ‘Impact of SiN Composition Variation on SANOS Memory Performance and Reliability under NAND (FN/FN) Operation’, IEEE Transactions on Electron Devices. v. 56, pp. 3123-3132, 2009.
  34. C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, “Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler Nordheim Tunneling Program/Erase Operation” IEEE Electron Device Letters v.30, No.2 pp. 171-173, 2009.
  35. U. Ganguly, T.-H. Hou, E. C. Kan, ‘Enhanced Electrostatics for Low-Voltage Operations in Nanocrystal based Nanotube/Nanowire Memories’, IEEE Trans. Nanotechnology, 6, 22, 2007.
  36. T.-H. Hou, U. Ganguly, and E. C. Kan, ‘Fermi-Level Pinning in Nanocrystal Memories’, IEEE Electron Device Letters, 28, 103, 2007.
  37. T.-H. Hou, U. Ganguly, and E. C. Kan, ‘Programmable Molecular Orbital States of C60 from Integrated Circuits,’ Applied Physics Letters, 89, 253113, 2006.
  38. U. Ganguly, V. Narayanan, C. Lee, T.-H. Hou, E. C. Kan, ‘Three dimensional analytical modeling of nanocrystal memory electrostatics’, Journal of Applied Physics, 99, 114516 2006.
  39. T. -H. Hou, C. Lee, V. Narayanan, U. Ganguly, E. C. Kan, ‘Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering’, IEEE Transactions on Electron Devices, 53, 3103, 2006.
  40. T. -H. Hou, C. Lee, V. Narayanan, U. Ganguly, E. C. Kan, ‘Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering’, IEEE Transactions on Electron Devices, 53, 3095, 2006.
  41. U. Ganguly, E.C. Kan, Y. Zhang, ‘Carbon nanotube FET memory with charge storage in metal nanocrystal’, Applied Physics Letters, 87, 043108 (2005).
  42. C. Lee, U. Ganguly, V. Narayanan, T.-H Hou, and E. C. Kan, ‘Asymmetric Electric Field Enhancement in Nanocrystal Memories’, IEEE Electron Device Letters, 26, 879, 2005.
  43. J. Guo, E. C. Kan, U. Ganguly, Y. Zhang, ‘High Sensitivity and Non-Linearity of Carbon-Nanotube-Based Charge Sensors’, Journal of Applied Physics, 99, 084301 2006.
  44. U. Ganguly, J. P. Krusius, “Fabrication of Ultra-Planar Aluminum Mirror Array by Novel Encapsulation CMP for Micro-optics and MEMS applications” Journal of Electrochemical Society, 151, H232, 2004.
  45. U. Ganguly, J. P. Krusius, “Novel compensation CMP for low dishing and high global planarity for ultra-planar die applications in micro-optics and MEMS”, Thin Solid Films, 460,306, 2004.

Refereed Conferences

  1. S. Lashkare, P. Kumbhare, V. Saraswat, S. Chatterjee and U. Ganguly “A Compact PrMnO3 Based Oscillator As an Alternative to CMOS Ring Oscillator in a Smart Temperature Sensor” IEEE Sensors 2018 (accepted)
  2. S. Lashkare, A. Bhat, P. Kumbhare and U. Ganguly “Transient Joule Heating in PrMnO 3 RRAM enables ReLU type Neuron” Non Volatile Memory Technology Symposium (NVMTS), 2018 (accepted)
  3. V. Bhat, U. Ganguly “Sparsity Enables Data and Energy Efficient Spiking Convolutional Neural Networks” 27th International Conference on Artificial Neural Networks (ICANN) 2018
  4. S. Shukla, S. Dutta, U. Ganguly “Design of Spiking Rate Coded Logic Gates for C. elegans Inspired Contour Tracking” 27th International Conference on Artificial Neural Networks (ICANN) 2018
  5. Amita, K. R. Khiangte, S. Mahapatra, and U. Ganguly, “Epitaxial Gd2O3 on Si (111) Substrate by Sputtering to Enable Low Cost SOI” Device Research Conference 2018
  6. T. Chavan, S. Dutta, N.R. Mohapatra, U. Ganguly, “An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS Technology,” Device Research Conference 2018.(Accepted)
  7. Aditya Shukla, Sidharth Prasad, Sandip Lashkare and Udayan Ganguly “A case for multiple and parallel RRAMs as synaptic model for training SNNs” International Joint Conference on Neural Networks (IJCNN) 2018 (Accepted)
  8. S. Dutta, T. Chavan, S. Shukla, A. Shukla, V. Kumar, N. Mohapatra, U. Ganguly, “Dynamics, Design and Application of a Silicon-on-Insulator Technology Based Neuron” Materials Research Society Spring Meeting EP06.03.04 (2018) invited talk link
  9. Piyush Bhatt, Amit Kumar Singh, Monika Gupta, B.Umapathi, HS Jatana and U.Ganguly “Technology development of CMOS compatible high gain BJT to enable 180nm BiCMOS technology” International Workshop on The Physics of Semiconductor Devices (IWPSD 2017).
  10. V. Saraswat, P Harsha Vardhan, U. Ganguly “Signs of Unconventional Physics in Long Channel Vertical InAs Nanowire MOSFETs” International Workshop on The Physics of Semiconductor Devices (IWPSD) 2017
  11. S. Lashkare, P. Kumbhare, U. Ganguly, “Delaying the Self-Heating Timescale of PCMO based RRAM to Improve Conductance Linearity for Neuromorphic Application”, International Workshop on The Physics of Semiconductor Devices (IWPSD) 2017
  12. P. Kumbhare, S. Chouhan, U. Ganguly, “PrMnO3-Based Scaled (<300 nm) Nonlinear RRAM Device for Selector-less Array Application”, International Workshop on the Physics of Semiconductor Devices (IWPSD) 2017.
  13. S. Sadana, A. Singh, D. Sehgal, B. Umapathi, H.S. Jatana, U. Ganguly “One Time Programmable (OTP) Memory based on MIM dielectric breakdown for 180nm CMOS” International Workshop on The Physics of Semiconductor Devices (IWPSD) 2017.
  14. S.Dutta, N. R. Mohapatra, U. Ganguly “ Bio-mimetic SOI MOSFET based Leaky Integrate & Fire Neuron ” International Workshop on The Physics of Semiconductor Devices (IWPSD) 2017
  15. B. Das, J. Schulze, U. Ganguly, “Effect of Delta-p Doping and i-region Length Scaling on Ion/Ioff in Si NIPIN Diode for Selector Application”, International Workshop on The Physics of Semiconductor Devices (IWPSD) 2017.
  16. S.Shrivastava, U. Ganguly “Array Programming Scheme to enable Improved Transient based Non-linearity in Impact Ionization based Si-NIPIN selector for Low Power” Non-Volatile Memory Tech Symp (NVMTS) 2017 link
  17. S. Rajarathinam, N. Panwar, P. Kumbhare, U Ganguly and N. Venkataramani, “Forming Free and Bipolar Resistance Switching Behavior in Zinc Ferrite Thin Films” on-Volatile Memory-Tech Symp (NVMTS) 2017 (Accepted)
  18. S. Prasad, A. Biswas, A. Shukla, U Ganguly, “A Highly Efficient Performance and Robustness Evaluation Method for a SNN based Recognition Algorithm” International Conference on Artificial Neural Networks (ICANN) 2017 (accepted).
  19. A. Biswas, S. Prasad, A. Shukla, U Ganguly, “SNN Model for Highly Energy and Area Efficient On-Chip Classification” International Conference on Artificial Neural Networks (ICANN) 2017 (accepted).
  20. A. Lele, S. Sadana, A. Singh, H.S. Jatana, U. Ganguly “A simple PECVD SiO2 OTP Memory based PUF for 180nm Node for IoT ” 75th Device Research Conference, 2017. link
  21. S. Chouhan, P. Kumbhare, A. Khanna, N. Panwar, U. Ganguly, “Effect of Thermal Resistance and scaling on dc-IV Characteristics of PCMO based RRAM Devices” 75th Device Research Conference, 2017. link
  22. A. Shukla, V. Kumar, U. Ganguly “A Software-equivalent SNN Hardware using RRAM-array for Asynchronous Real-time Learning” International Joint Conference on Neural Networks (IJCNN) 2017 link
  23. P. Kumbhare, S. Chouhan, U. Ganguly “Pr1-xCaxMnO3 Based Selector, RRAM and Self-selecting Selectorless RRAM: A Composition Study” 74th Device Research Conference, 2016. link
  24. P Harsha Vardhan1, Sushant Mittal, A. S. Shekhawat, S. Ganguly and U.Ganguly “Analytical modeling of Metal gate granularity induced Vt variability in NWFETs” 74th Device Research Conference, 2016. link
  25. P. Kumbhare, I.Chakraborty, A. K. Singh, N. Panwar, S. Chouhan, U. Ganguly “A Selector-less RRAM with Record Memory Window and Non-linearity Based on Trap Filled Limit Mechanism” Non-Volatile Memory Tech Symp (NVMTS) 2015 link
  26. V. Ostwal, B. Rajendran, U. Ganguly, “A Circuit Model for a Si-based Biomimetic Synaptic Time-keeping Device”, SISPAD 2015 link
  27. S. Mittal, A. Shekhawat, U Ganguly , “FinFET Scaling Rule Based On Variability Considerations”, 73rd Device Research Conference 2015 link
  28. I. Chakraborty, A. K. Singh, P. Kumbhare, N. Panwar, U. Ganguly, “Materials Parameter Extraction using Analytical Models in PCMO based RRAM”, 73rd Device Research Conference 2015 link
  29. N. Panwar, U Ganguly, “Variability Assessment and Mitigation by Predictive Programming in Pr0.7Ca0.3MnO3 Based RRAM”, 73rd Device Research Conference 2015 link
  30. V. S. Senthil Srinivasan, B. Das, C. Pinto Gómez, M. Oehme, U. Ganguly and J. Schulze, “Low Temperature Epitaxial Germanium P+IN+IP+ Selector for RRAM”, 73rd Device Research Conference 2015 link
  31. V. Ostwal, R. Meshram, R. Rajendran, U. Ganguly , “An Ultra-compact and Low Power Neuron based on SOI platform” VLSI TSA, Taiwan 2015 link
  32. S. Dutta, S. Mittal, J. Schulze, S. Lodha, U. Ganguly, “A Bulk Planar SiGe Quantum-Well based ZRAM with Low VT Variability” International Memory Workshop Monteray USA 2015 link
  33. N. Panwar, P. Kumbhare, A. Singh, N. Venkataramani, U. Ganguly, “Effect of Morphological Change on Unipolar and Bipolar Switching Characteristics in Pr0.7Ca0.3MnO3 Based RRAM” M8.10 MRS Fall 2014 link
  34. P. Kumbhare, P. Meihar, N. Panwar, S. Rajarathinam, U. Ganguly, “A Comprehensive Study of Effect of Composition on Resistive Switching of HfxAl1-xOy Based RRAM Devices by Combinatorial Sputtering” M6.01 MRS Fall 2014 link
  35. R. Mandapati*, B. Das*, V. Ostwal, and U. Ganguly, “Voltage Designability: An Enabler for Selector Technology” 14th Non Volatile Memory Tech Symp., Korea (NVMTS) 2014 link
  36. V. Kumar, U. Ganguly, “Impact of MIM versus NPN Selector on Dynamic Power in Bipolar RRAM Array”, 14th Non Volatile Memory Tech Symp., Korea (NVMTS) 2014 link
  37. SN Chinta, S Mittal, P Debashis, U Ganguly, “A FinFET LER V T variability estimation scheme with 300× efficiency improvement” Simulation of Semiconductor Processes and Devices (SISPAD), 2014 link
  38. B. Das, R. Meshram, V. Ostwal, J. Schulze, U. Ganguly “Observation of impact ionization at sub-0.5V and resultant improvement in ideality in I-NPN selector device by Si epitaxy for RRAM applications” DRC 2014 link
  39. N. Panwar, D. Kumar, N. K. Upadhyay, P. Arya, U. Ganguly, B. Rajendran. “Memristive Synaptic Plasticity in Pr0.7Ca0.3MnO3 RRAM by Bio-mimetic Programming” DRC 2014 2014 link
  40. R. Mandapati, S. Shrivastava, B. Das, Sushama, V. Ostwal, J. Schulze, U. Ganguly “High Performance sub-430°C Epitaxial Silicon PIN Selector for 3D RRAM " DRC 2014 link
  41. S. Mittal, S. Kurude, S. Dutta, P. Debashis, S. Ganguly, S. Lodha, A. Laha, U. Ganguly, “Epitaxial Rare Earth Oxide (EOx) FinFET: a variability-resistant Ge FinFET architecture with multi VT” DRC 2014 link
  42. R. Meshram, B. Rajendran, U. Ganguly “Biomimetic 4F2 synapse with intrinsic timescale for pulse based STDP by I-NPN selection device " DRC 2014 link
  43. Prashanth Paramahans Manik, Ravi Kesh Mishra, Udayan Ganguly, Saurabh Lodha, “Indium tin oxide (ITO) and Al-doped ZnO (AZO) interfacial layers for Ohmic contacts on n-type Germanium " DRC 2014 link
  44. R. Meshram, B. Das, R. Mandapati, S. Lashkare, S. Deshmukh, S. Lodha, J. Schulze, U. Ganguly, “High Performance Triangular Barrier Engineered NIPIN Selector for Bipolar RRAM” International Memory Workshop (IMW) 2014 link
  45. P.Debashis, S. Mittal, S. Lodha and U. Ganguly “Dopant Deactivation: A new challenge in sub-20nm Scaled FinFETs”, IEEE VLSI TSA, 2014 link
  46. S. Mittal, P. Debashis, A. Nainani, M. C. Abraham, S. Lodha and U. Ganguly " Epi Defined (ED) FinFET with Dynamic Threshold: Reduced VT Variability, Enhanced Performance, and a novel Multiple VT”, IEEE INDICON, Mumbai, India 2013 Best Paper Award link
  47. R. K. Mishra, U. Ganguly, S. Ganguly, S. Lodha, A. Nainani, M. Abraham, “Nickel germanide with rare earth interlayers for Ge CMOS applications”, EDSSC, Hong Kong, 2013
  48. P Bhatt, K Chaudhuri, P Maharaja, A Nainani, M Abraham, M Subramaniam, U Ganguly, S Lodha, “Improved Nitridation of GeO2 Interfacial layer for Ge Gate Stack Technology” MRS 2013, link
  49. S. Deshmukh, S. Lashkare, B. Rajendran, U. Ganguly”I-NPN: A sub-60mV/decade, sub-0.6V selection diode for STTRAM”, Device Research Conference 2013 link
  50. S. Lashkare, P. Karkare, P. Bafna, M.V.S. Raju, V.S.S. Srinivasan, J. Schulze, S. Chopra, S. Lodha, U. Ganguly, " A Bipolar RRAM Selector with Designable Polarity Dependent On-Voltage Asymmetry” International Memory Workshop, 2013 link
  51. H. Mehta, S. Lodha, U. Ganguly, S. Ganguly, “Calibration of the Density-Gradient TCAD Model for Germanium FinFETs”, IEEE Regional Symposium on Micro and Nanoelectronics, Malaysia, Sept, 2013
  52. S. Mittal, S. Gupta, A. Nainani, M. Abhraham, K. Schuegraf, S. Lodha, and U. Ganguly, " Epi Defined (ED) FinFET: An alternate device architecture for high mobility Ge channel integration in PMOSFET” 5th IEEE International Nanoelectronics Conference, IEEE INEC 2013 link
  53. R. Mandapati, A. Borkar, S. Srinivasan, P. Bafna, P. Karkare, S. Lodha, and U.Ganguly, “On Pairing Bipolar RRAM memory element with novel punchthrough diode based selector: Compact modeling to array performance” 5th IEEE International Nanoelectronics Conference, IEEE INEC 2013 link.
  54. N. Panwar, G. Rao, N. R. C. Raju, R. Nori, P. Kumbhare, S. Deshmukh, V. S. S. Srinivasan , N. Venkataramani, U. Ganguly, “Thermal Budget Reduction for Back-end Compatibility and Control of Resistance Switching Mechanism (Unipolar to Bipolar) in Pr1-xCaxMnO3 (PCMO) RRAM” MRS Fall, AA9.27, Boston, 2012 link
  55. R. Nori, N. R. C. Raju, N. Thomas, N. Panwar, P. Kumbhare, G. Rao, V. S. S. Srinivasan, N. Venkataramani, U. Ganguly, “Conducting Oxide Electrode to Mitigate Mechanical Instability (Bubble Formation) during Operation of La1-xSrxMnO3 (LSMO) Based RRAM” MRS Fall A12.40, Boston, 2012 link.
  56. S. Lashkare, P. Karkare, P. Bafna, S. Deshmukh, V.S.S. Srivinasan, S. Lodha, U. Ganguly, Design of epitaxial Si punch-through diode based selector for high density bipolar RRAM” Int. Conf. on Emerging Electronics link
  57. S. Deshmukh, R. Mandapati, S. Lashkare, A. Borkar, V.S.S. Srivinasan, S. Lodha, U. Ganguly, “Comparison of novel punch-through diode (NPN) selector with MIM selector for Bipolar RRAM” Non Volatile Memory Technology Symposium, Singapore, 2012 link
  58. S. Chopra, P. Bafna, P. Karkare, S. Srinivasan, S. Lashkare, P. Kumbhare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, and U. Ganguly, “A Two Terminal Vertical Selector Device for Bipolar RRAM”, Pacific Rim Meeting on Electrochemical and Solid State Science (PRiME), Honolulu, Hawaii, USA, October 7-12 2012 link.
  59. P. Bafna, P. Karkare, S Srinivasan, S. Chopra, S. Lashkare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, U. Ganguly, “Epitaxial Si Punch-Through based Selector for Bipolar RRAM”, DRC 2012 link
  60. S. Mittal, S. Gupta, A. Nainani, M.C. Abraham, K. Schuegraf, S. Lodha, U. Ganguly, “Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT”, Device Research Conference 2012 link
  61. P. Paramahans, P. Ray, S. Mane, P. Nyaupane, U. Ganguly, S. Lodha, “Ohmic contacts to n-type Germanium using a thin ZnO interfacial layer” in MRS Spring Meeting, San Francisco 2012.
  62. V. Pavan Kishore, P. Paramahans, S. Sadana, U. Ganguly, S. Lodha, “Contact Resistance Reduction on Germanium through Metal Work Function Engineering” in MRS Spring Meeting, San Francisco 2012
  63. P. Paramahans, S. Gupta, R. K. Mishra, N. Agarwal, A. Nainani, Y. Huang, M.C. Abraham, S. Kapadia, U. Ganguly, S. Lodha, “ZnO: an attractive option for n-type metal-interfacial layer-semiconductor (Si, Ge, SiC) contacts”, VLSI Symp 2012
  64. V. P. Kishore, P. Paramahans, S. Sadana, U. Ganguly, S. Lodha, “Novel Nanocrystal-based contacts to n and p-type Germanium”, Physics and Chemistry of Surfaces and Interfaces (PCSI) 2012
  65. T Guarini, M Bevan, M Ripley, U Ganguly, H Graoui, J Swenberg, “Nitric oxide rapid thermal nitridation for Flash memory applications”, 2010 18th International Conference on Advanced Thermal Processing of Semiconductors (RTP), pp160, 2010 link
  66. U. Ganguly, Y. Yokota, J. Tang, S. Sun, M. Rogers, M. Jin , K. Thadani, H. Hamana, G. Leung, B. Chandrasekaran, S. Thirupapuliyur, C. Olsen, V. Nguyen, S. Srinivasan, “Scalability Enhancement of FG NAND by FG Shape Modification” International Memory Workshop, Seoul 2010.
  67. C. Sandhya, U. Ganguly, B. Apoorva, C. Olsen, S. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, ‘Influence of SiN composition on Program and Erase Characteristics of SANOS-type Flash Memories’, in IEEE Intl. Workshop on Electron Devices and Semiconductor Technology (IEDST) 2009. Received the Outstanding Paper Award
  68. A Rothschild, L Breuil, G Van Den Bosch, O Richard, T Conard, A Franquet, A Cacciato, I Debusschere, M Jurczak, J Van Houdt, JA Kittl, U Ganguly, P Boelen, R Schreutelkamp, “O 2 post deposition anneal of Al 2 O 3 blocking dielectric for higher performance and reliability of TANOS Flash memory” ESSDRC 2006 link
  69. Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, R. Hung, C. Olsen, S. M. Seutter, G. Conti, K. Ahmed,N. Krishna, J. Vasi, and S. Mahapatra, ‘The Effect of Band Gap Engineering of the Nitride Storage Node on Performance and Reliability of Charge Trap Flash’, International Physics of Failure Analysis (IPFA), 2008
  70. Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, R. Hung, C. Olsen, S. M. Seutter, G. Conti, K. Ahmed,N. Krishna, J. Vasi, and S. Mahapatra, ‘Nitride engineering and the effect of interfaces on Charge Trap Flash performance’, International Reliability Physics Symposium (IRPS), 2008
  71. G Van den Bosch, A Furnémont, MB Zahid, R Degraeve, L Breuil, A Cacciato, A Rothschild, C Olsen, U Ganguly, J Van Houdt, “Nitride engineering for improved erase performance and retention of TANOS NAND flash memory” Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 International Conference on Memory Technology and Design. NVSMW/ICMTD 2008. link
  72. A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, ‘Development of A 3D Simulator for Metal Nanocrystal (NC) Flash Memories under NAND Operation’, International Electron Devices Meeting (IEDM) 2007.
  73. U. Ganguly, T.-H. Hou and E. C. Kan, ‘Process Integration of Composite High-k Tunneling Dielectric for Nanocrystal Based Carbon Nanotube Memory’, (MRS) Material Research Symposium, Boston, MA, Dec. 2006.
  74. U. Ganguly, T.-H. Hou and E. C. Kan, ‘Quantum Transport and Trap Effects in Tunneling Rate Measurements of Metal Nanocrystal Based Carbon Nanotube Memory’, (MRS) Material Research Symposium, Boston, MA, Dec. 2005.
  75. U. Ganguly, C. Lee and E. C. Kan, ‘Retention characteristics for nonvolatile memory based on metal nanocrystals and carbon nanotube FET with CVD SiO2 and ALD HfO2 tunneling dielectrics’, (MRS) Material Research Symposium, Boston, MA, Dec. 2005.
  76. U. Ganguly, J. Guo, E. C. Kan and Y. Zhang, ’Carbon nanotubes based non-volatile memory and charge sensors’, Proc. of SPIE Conference, vol. 6003, Oct., 2005. (Invited paper)
  77. U. Ganguly, C. Lee and E. C. Kan , ‘Experimental Observation of Non-Volatile Charge Injection and Molecular Redox in Fullerenes C60 and C70 in an EEPROM Type Device’, (MRS) Material Research Symposium, Boston, MA, Dec. 2004. MRS Trophy Award for best paper in Symposium D
  78. C. Lee, U. Ganguly and E. C. Kan, ‘Characterization of Number Fluctuations in Gate-last Metal Nanocrystal Nonvolatile Memory Array Beyond 90nm CMOS Technology’, (MRS) Material Research Symposium, Boston, MA, Dec. 2004.
  79. U. Ganguly, C. Lee and E. C. Kan, ‘Interface and oxide contamination monitoring in integration of fullerenes and carbon nanotubes with aggressively scaled CMOS gate stacks’, (MRS) Material Research Symposium, Boston, MA, Dec. 2003.

Patents Applied/Granted

  1. Amita, K. Roluhapuia, S. Mahapatra, A. Laha, U Ganguly “Methodology to Produce Semiconductor on Insulator Substrate” (Application No 201821023394)
  2. T. Chavan, S. Dutta, U. Ganguly, “An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS Technology” (Application No. 201821023397)
  3. S. Lashkare, V Saraswat, P Kumbhare, U Ganguly, “Method for fabricating neuron oscillator including thermal insulating device” (Application No 201821019896)
  4. U. Ganguly, A. Shukla “An analog synapse with simultaneous learning and recognition” (Application No. 201821015672)
  5. U. Ganguly, S. Sadana, A. Lele, “Method of generating controllably biased random number by OTP devices” (Application No. 201821010427)
  6. U. Ganguly, S. Dutta, V. Kumar “Leaky Integrate & Fire (LIF) Neuron based on Floating Body Effect” (Application No. 201721027169)
  7. P. Kumbhare, S. Sadana, U. Ganguly “One Time Programmable Memory for Encryption and Reconfigurable Circuits”” (Application No. 201621031483)
  8. P. Kumbhare, U. Ganguly, I. Chakraborty, A. Singh “Selectorless Resistance Random Access Memory (RRAM)” 3866/MUM/2015
  9. U. Ganguly, S. Dutta, S. Mittal, “A bulk planar capacitorless Dynamic Random Access Memory” 1976/MUM/2015
  10. U. Ganguly, V. Ostwal, R. Meshram, B. Rajendran, “A electronic device that mimics a biological neuron and its fabrication” 1545 /MUM/2015
  11. U. Ganguly, S. Deshmukh, B. Rajendran, “An ambipolar two terminal selection device” 2134/MUM/2013.
  12. S. Mittal, S. Gupta, U. Ganguly, A. Nainani, S. Lodha, S. Ganguly, M. Abraham, E.-X. Ping, “Transistor design for improved performance and variability and method of fabrication”, 1750/MUM/2012
  13. S. Lodha, U. Ganguly, V. Pavan Kishore, “Method of forming low resistance metal contacts simultaneously on n and p-type semiconductors”, 532/MUM/2013.
  14. U. Ganguly, S. Lodha, P. Bafna, P. Karkare, P. Kumbhare, S. Srinivasan, “Selector device for bipolar RRAM,” Indian Patent Application, 1727/MUM/2011 and PCT/IN2012/000411 Patent No 2013046217 Patent Office WO
  15. P. Paramhans, S. Lodha, U. Ganguly, A. Nainani, M. Abraham, “Metal-Interfacial Semiconductor Layer-Semiconductor Contact”, 1698/MUM/2012
  16. Udayan Ganguly, Theresa Kramer Guarini, Matthew Scott Rogers, YOShltaka Yokota, Johanes Swenberg Malcolm J. Bevan, “Method and Apparatus for Single Step Selective Nitridation” USPTO 8,748,259
  17. J. Swenberg, D. Chu, T. K. Guarini, Y. Cho, U. Ganguly, L. Date, " Enhancing NAND Flash Floating Gate Performance, " Applied Materials Inc, 20100317186
  18. U. Ganguly, C Olsen, S M Seutter L Date, “Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control” Applied Materials Inc, 20110101442
  19. U. Ganguly, J. M. Ranish, A. M. Hunter, J. Tang, C. S. Olsen, M. D. Scotney-Castle, V. Nguyen, S. Srinivasan, W. Liu, J. F. Swenberg, S. Sun, “Apparatus and Methods for Cyclical Oxidation and Etching,” Applied Materials Inc., 20110065276
  20. U. Ganguly, Y. Yokota, C. S. Olsen, M. D. Scotney-Castle, V. Nguyen, S. Srinivasan, W. Liu, J. F. Swenberg, J. A. Marin, A. Balakrishna, J. Newman, S. C. Hickerson, “Apparatus and Methods for Cyclical Oxidation and Etching,” Applied Materials Inc., 20110061812
  21. U. Ganguly, J. M. Ranish, A. M. Hunter, J. Tang, C. S. Olsen, M. D. Scotney-Castle, V. Nguyen, S. Srinivasan, J. F. Swenberg, A. Wang, N. K. Ingle, M. Hemkar, J. A. Marin, “Apparatus and Methods for Cyclical Oxidation and Etching,” Applied Materials Inc., 20110061810
  22. C. S. Olsen, S. Sun, T. W. Poon, U. Ganguly, J. Swenberg, “Modification of charge trap silicon nitride with oxygen plasma,” Applied Materials Inc., 20100270609
  23. C. S. Olsen, J. Swenberg, U. Ganguly, T. K. Guarini, Y. Cho, “Method of Selective Nitridation,” Applied Materials Inc., US Patent 7972933
  24. U. Ganguly, Y. Yokota, J. Tang, S. Thirupapuliyur, C. S. Olsen, S. Sun, T. W. Poon, W. Liu, J. Swenberg, V. U. Nguyen, S. Srinivasan, J. Newman, “Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof,” Applied Materials Inc., 20100062603
  25. Y. Zhang, U. Ganguly, E. C. Kan " Nanotube- and nanocrystal-based non-volatile memory,” Intel Corp, US 7262991

Selected Invited Talks / Tutorials

  1. Invited Talk “Indigenous One-Time-Programmable Memory based Hardware Encryption on 180 nm CMOS Technology” INTERNATIONAL WORKSHOP on NANO/MICRO 2D-3D FABRICATION, MANUFACTURING of ELECTRONIC – BIOMEDICAL DEVICES & APPLICATIONS (IWNEBD-2018) @ IIT Mandi
  2. Invited Talk “Building a Spiking Neural Network from Neurons to Networks”, ADCOM 2018 @ IIIT Bangalore
  3. CTO Office Invited Speaker Variability from FinFETs to SOI Neurons GlobalFoundries, Bangalore 11, July 2018
  4. Invited talk on Modeling Variability in FinFETs with Dr. Sushant Mittal; Session introduction on “TCAD-Modeling in India” at Synopsys Users Group (SNUG) Meeting, 12 July 2018
  5. Presented a tutorial to college teachers on “Artificial Intelligence using Nanoscale Devices” at Somaiya VidyaVihar Mumbai on 2nd July 2018
  6. Invited talk on Materials, Devices and Systems for Machine Learning and Neuromorphic Computing at Material Research Society (MRS) Conference Spring 2018 ( in Phoenix, Arizona, USA)
  7. Invited talk on Complex Metal Oxide RRAM for Neuromorphic Computing at “XIX International Workshop on the Physics of Semiconductor Devices (IWPSD 2017)”, jointly organized by SSPL and IIT Delhi from December 11th – 15th
  8. Invited talk on Mimicking Biology with Spiking Neural Networks: From Novel Electronic Devices, Asynchronous Hardware to Algorithms at Intel India Research Colloquium 2017 ( 8th October 2017 in Bangalore, India)
  9. Invited talk “Manganite based Non-Filamentary Resistance RAM (RRAM)” NCTU IITB Meeting 27th April 2017
  10. Invited talk On-chip spiking neural networks for classification and pattern recognition 14th June 2017 at SCL, Chandigarh link
  11. Dept. of Computer Science and Engineering IITB “Can Silicon Technology enable biological Spiking Neural Networks?” Sept 14, 2016
  12. Invited talk “Si/Ge based RRAM Selection Device” NCTU, Taiwan, April 28, 2015
  13. Invited talk “Of Synapses and Neurons: Unconventional Si/Ge Electronic Devices” EDS at Cornell University Jun 26, 2015
  14. VLSI Design Tutorial 2015 on “Neuromorphic Computing -Algorithms, Devices and Systems” with B Rajendran (IITB) and M Suri (IITD)
  15. Invited talk “Selector Devices for Future Non-Volatile Memory Technologies” at ICEE 2014 link
  16. “RRAM Technologies” Tutorial INUP Familiarization Workshop Dec 2014
  17. Invited talk “Forum on Nanoelectronic Manufacturing: From Materials to Systems " organized by Semiconductor Research Consortium at TIFR on Oct, 8-10, 2014 (SRC) link
  18. Invited talk “Nanoelectronics in Indian Academia: Present and Future: A policy & implementation perspective” ASSOCHAM National Summit NANO INDIA Policy Regulations and Innovation Excellence Awards June 2014 link to event
  19. Invited talk “Non-volatile memory Engineering- Capabilities and Future Directions at IIT Bombay”, India Research Network Meeting, Organized by Samsung India Software Operations, Bangalore, May 2012.
  20. Invited talk “Floating Gate Scaling Roadmap” Applied Materials Technology Forum 2007

Outreach

  • Presented CEN related research activities at NIT Agartala 2016
  • Presented CEN related research activities at NIT Calicut 2012
  • Presented CEN related research activities at Science College, Calcutta University, 2011
  • Coordinated with Prof S. Lodha for India’s first " Semiconductor Technology and Manufacturing Course” under Continuing Education Program - with Applied Materials Inc 19th-25th Nov 2012
  • Moderated a panel discussion on “Catalyzing & Sustaining Semiconductor Manufacturing in India” organized during International Conference on Emerging Electronics (Jointly organized by IIT Bombay & IISc Bangalore)December 15-17, 2012 on behalf of DeitY; Panelists were Dr Ajay Kumar DeitY; Dr Zarabi (Empowered Committee), Dr. PVG Menon (Indian Semiconductor Association), Dr Subu Iyer (Fellow, IBM), Dr Om Nalamasu (CTO, Applied Materials Inc)

Conference Organization

Present Group Members

Supervised Research Exposition

  1. Ashwin Lele
  2. Shashwat Shukla

M. Tech. students

Ph. D. students

  1. Pankaj Kumbhare
  2. Bhaskar Das
  3. Sangya Dutta
  4. Shalini Shrivastava
  5. Vinay Sangwan
  6. Amita
  7. Sandip Lashkare

Staff

  1. Sunny Sadana

Past Group Members

Bachelors

  1. Sabareesh Nikhil (2014) puruing Ph. D. at UCLA
  2. Anmol Biswas (2016) - Samsung R&D
  3. Nikhil Kodali (2017) pursuing PhD at Insititute for Computational Physics University of Stuttgart
  4. Varun Bhatt (2018) - pursuing Ph.D. in U Alberta Canada in CS
  5. Varunesh Goyal (2018) - pursuing M.S. at U Texas Austin

Masters

  1. Sunny Sadana (2011 with S. Lodha) joined as Process Integration Engineer at Global Foundries, Singapore
  2. Shashank Gupta (2011 with S Lodha) joined as Research Engineer at Applied Materials, India and now in the Stanford Ph.D. program)
  3. Pranil Bafna (2012 with S Lodha) joined as Business Analyst at Inductis, Gurgaon, India
  4. Prateek Karkare (2012 shared with S Lodha) joined as Engineer at NVIDIA, Bangalore, India
  5. Gurudatt Rao (2012 shared with N Venkataramani MEMS) joined as Engineer at TSMC, Taiwan
  6. Sanchit Deshmukh (2013) joined as a Ph. D. student at Stanford
  7. Manjith Bose (2013 shared with S Basu MEMS)- Continuing as project staff
  8. Krishnakali Chaudhuri (2013 shared with S Lodha EE) – pursuing Ph.D. at Purdue
  9. Sandip Lashkare (2013) – joined as ASIC designer in LSI
  10. Ajit Kumar (MEMS 2014) - joined IBM in software development
  11. Priyash Jichkar (2014) - joined Vodafone India
  12. Rajiv Meshram (2014)- took up prep for IAS Exam
  13. Punyashloka Debashis (2014) - joined as Ph. D. student at Purdue University
  14. Vinay Kumar (2014) - continued as Ph. D. student
  15. Priyanka Arya (2014 with B Rajendran as primary advisor)
  16. Vaibhav Ostwal (2015) - joined Ph. D. program at Purdue University * outstanding D.D. thesis award *
  17. Anand Singh (2015) - joined as Product Engineer at Sprinklr
  18. Indranil Chakraborty (2016) - joined as Ph. D. student at Purdue University * outstanding M.Tech. thesis award *
  19. Abhimanyu Shekhawat (2016) - joined as Faculty at NIT Jodhpur
  20. Paritosh Meihar (Physics 2016) - self-employed
  21. Shreyas Mangalgi (2016) - employed as Engineer in Tata Communications
  22. Gaurav Patil (2016) - self-employed
  23. Abhishek Khanna (2016) - continued as research staff for a year, the joined Ph. D. program at U. Notre Dame.
  24. Sainath Kurude (2016) - joined Intel in circuit design
  25. Shikhar Chouhan (2017) - Digital IC Design Engineer at Texas Instruments
  26. Shankar Prasad (2017) - Digital IC Design Engineer at Marvell Semiconductors.
  27. Aditya Shukla (2017) - continued as Research Staff for 1 year; Joined Ph.D. at U Michigan *Outstanding M.Tech. Thesis award*
  28. Sidharth Prasad (2017) - pursuing Masters in C.S. at Columbia University *Outstanding D.D. Thesis award*
  29. Tanmay Chavan (2018) - continuing as Staff *Outstanding M.Tech. Thesis award*
  30. Vivek Saraswat (2018) - continuing as Ph.D. student with prestigious PMRF Fellowship *Outstanding D.D. Thesis award*
  31. Ashwin Bhat (2018) - pursuing Ph.D. in Georgia Tech

Ph. D.

  1. Rajashree Nori - Thesis “Integration of La1-xSrxMnO3 (LSMO)on Si for Logic and Memory Applications” 2014 - Self-employed pursuing science writing (V. R. Rao - Advisor; U. Ganguly- Co-Advisor )
  2. Raju Mandapati - Thesis “Selector Device Engineering for RRAM Technology” 2016 - Yield Engineer at GlobalFoundries (U. Ganguly - Advisor; S. Lodha- Co-Advisor)
  3. Piyush Bhatt - Thesis “Gate Stack and Junction Engineering for High-Performance Ge MOSFETs”, 2016 - continued as staff for SCL Tech Dev Project; Sr. Engineer at Applied Materials (S. Lodha - Advisor; U. Ganguly- Co-Advisor)
  4. Prashanth Paramhans - Thesis “Experimental and Modeling Studies of Low Resistance Metal/Interfacial Layer/n-Ge contacts” ( S. Lodha - Advisor, U. Ganguly- Co-Advisor)
  5. Sushant Mittal - Thesis “Challenges in FinFETs: Analytical Modelling and Structural Solutions”, 2016- R&D at Micron (U. Ganguly - Advisor; S. Lodha- Co-Advisor)
  6. Neeraj Panwar - Thesis “Development of Pr0.7Ca0.3MnO3 based RRAM and Synapse”, 2017, (U. Ganguly - Advisor);

Post Doc

  1. Dr. V. S. Senthil Srinivasan (Ph. D. from DRDO Jodhpur)- presently at U. of Stuttgart
  2. Dr. Ravichandra Raju (Ph. D. from IIT Madras ) – presently in University of Queensland

Research Experience

  • April 2010-June 2010 Member of Technical Staff, FEP- Applied Materials
  • Sept 2006- April 2010 Senior Application Development Engineer, FEP- Applied Materials,

• Technical Lead for Non-Volatile Flash Memory program
• Floating gate Flash gate-stack process integration and device engineering
• Process optimization for Charge Trap Flash Gate Stack for sub-40nm node NAND
• Technical Lead for NVM Joint Development Program with IMEC
• Technical Lead for university collaborations with IIT Bombay for NVM performance and reliability

  • May 2007- Oct 2007 Visiting Assistant Professor, Electrical Engineering, IIT Bombay

• Nitride engineering (SiN-SiON-SiN) in Charge Trap Flash for endurance enhancement
• Simulation of number and position fluctations metal nanocrystal impact on memory scalability.

  • May 2006- Aug 2006 Post Doctoral Scholar, NASA Ames Research Center

• NW based electronics (high mobility materials for logic, phase change memory and systems)

  • Fall, 2004, Graduate Research Intern, Intel Research, Manager: Dr. Yuegang Zhang

• Carbon Nanotube based Flash memory based on metal nanocrystal charge storage

  • 2003-2006 Research Assistant, Ph.D. program, Advisor: Prof. Edwin C. Kan, ECE

• Memory device using fullerenes (e.g. C60) for charge storage in molecular orbitals in Flash
• Carbon nanotube as gate of MOSFET for CMOS scaling study and molecular sensor applications
• Charge injection and transport study between a 1D to a 0D mesoscopic electronic system
• Integration of CVD SiO2 and ALD HfO2 for room temperature devices using nanotubes and fullerenes in CMOS

  • 2000-2002 Research Assistant, Ph.D. program, Advisor: Prof. J. Peter Krusius, ECE

• Seamlessly tiled microdisplay assembly technology for LCoS microdisplay
• Novel CMP based metallization process development for ultra-flat die for micro-optics
• Novel scheme for the fabrication ultra-planar, zero-dishing, large area aluminum micro-mirror array

  • 1999-2000 Research Assistant, IIT Madras, India Advisor: Prof. P.K. Nair, Metallurgy

• Design and fabrication of electric arc chamber for the large scale production of single walled carbon nanotubes

Contact Information

Udayan Ganguly
Associate Professor
Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email: udayan[AT]ee.iitb.ac.in
Phone: (O) +91 22 2576 7698
Office room no: Nanoelectronics Bldg Rm 605
Fax:

Biographical Sketch

Udayan Ganguly received the B.Tech. degree in Metallurgical Engineering from the IIT Madras, in 2000 and the M.S. and Ph.D. degrees in Materials Science and Engineering at Cornell University, Ithaca, NY, in 2005 and 2006 respectively. In 2006, Udayan joined Applied Materials to serve as the technical lead for Flash Memory Applications Development at Applied Materials’ Front End Product Division, Sunnyvale, CA. He has joined Dept. of Electrical Engineering in 2010. He has authored/ co-authored 45+ journal, 75+ conference and 25+ patents (applied/granted). His research interests are in semiconductor device physics and processing technologies for advanced memory, computing, and neuromorphic systems. He likes to experiment with teaching/learning methods like "Think-Pair-Share". He has contributed to the TIFAC National Vision for ICT 2035. He works to augment national semiconductor manufacturing capability at Semi-Conductor Labs, Chandigarh.

IIT Bombay Campus Service

Professional maintenance and tracking in a critical need for Indian Govt. institutions. We have established an online campus maintenance tracking system that was initiated in 2012 at the lab level, demonstrated at various levels including institute wide AC maintenance till 2015 in a voluntary mode. This shows the commitment of campus service groups to improve services. From 2015 it is now officially constituted / recognized as part of the IITB administration.

Scheduling an Appointment

To schedule appointments please check my Google Calendar for a free slot and send me an email

Various Job Openings

  • I request interested M.Tech and Ph.D. students to contact me after they have secured admission at IIT Bombay.
  • I presently do not need project staff.
  • I accept interns through two standard processes only given below.

Assorted Thoughts & Writings

Practice - A Path from Memorization to Creativity

Goals and Roadmap of Ph.D. Program at IIT Bombay- A Desiderata
As the Ph.D. Desiderata document may require further clarifications, please provide Feedback
A related talk by Prof. Sridhar Iyer ET @ IITB on Why should IIT give you a Ph.D.?

Seminar, BTP, DDP, MTP Goals and Evaluation - A guideline for students and faculty in Microelectronics Group @EE (EE4). For further clarifications, please provide Feedback
DD MTP Evaluation procedure based on the above guidelines is present.

Faculty Advisors Guideline - to provide a uniform mode of interactions for Faculty and their student Advisees. Also, link to EE@IITB Faculty Advisor Page

IITBNF: Key to the Future A short article co-authored with Swaroop Ganguly- based on chapter contributed to TIFAC Vision 2035

Department of Electrical Engineering: Vision The first vision document for the Department of Electrical Engineering, IIT Bombay - where I was proud to serve as the Committee Chair.

 
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