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Juzer Vasi

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Research Interests:

  • Reliability of solar modules
  • Deployment of solar PV in India
  • Global deployment of solar PV
  • Nanocrystal based solar cells
  • Nanoelectronics

Courses Offered (2010-2017)

  • EE661 Physical Electronics
  • EE620 Physics of Transistors
  • EE733 Introduction to Solid State Devices
  • EE112 Introduction to Electronics

Academic Background

  • B.Tech., Indian Institute of Technology Bombay, 1969.
  • Ph.D., The Johns Hopkins University, Baltimore, USA, 1973.

Work Experience

  • Professor Emeritus, Indian Institute of Technology Bombay, 2017-present
  • Emeritus Fellow, Indian Institute of Technology Bombay, 2015-2017
  • Professor, Indian Institute of Technology Bombay, 1983-2015
  • Deputy Director, Indian Institute of Technology Bombay, 2006-2009
  • Head, Department of Electrical Engineering, Indian Institute of Technology Bombay, 1992-1994
  • Assistant Professor, Indian Institute of Technology Bombay, 1981-1983
  • Lecturer & Assistant Professor, Indian Institute of Technology Delhi, 1974-1981
  • Visiting Assistant Professor, The Johns Hopkins University, Baltimore, 1973-1974

Awards and Honours

  • Fellow, IEEE
  • Fellow, INAE
  • Fellow, IETE
  • Elected to The Johns Hopkins Society of Scholars, 1993
  • Sreenivasan Memorial Award of IETE, for distinguished contributions to teaching of electronics in India, 1997
  • Award for Excellence in Teaching, Indian Institute of Technology Bombay, 2000, 2009, 2013
  • Mathur Award for Excellence in Research, Indian Institute of Technology Bombay, 2006
  • TechnoVisionary Award, India Semiconductor Association, 2008
  • Lifetime Achievement Award, Indian Institute of Technology Bombay, 2013
  • Lifetime Contribution Award, Indian National Academy of Engineering (INAE), 2018

Other Information

Technical and Professional Contributions

  • Over 170 papers published in journals and presented at international conferences
  • Editor, IEEE Transactions on Electron Devices, 1996-2003
  • Associate Editor, Frontiers in Energy Research, 2015-
  • Principal Investigator, National Centre for Photovoltaic Research & Education (NCPRE), 2010-2012
  • Research Thrust Co-Lead for India, Solar Energy Research Institute for India and the US (SERIIUS), 2012-2018
  • Co-Principal Investigator, Centre of Excellence in Nanoelectronics (CEN), 2006-2011
  • Co-Principal Investigator, Indian Nanoelectronics Users Programme (INUP), 2008-2012
  • Investigator/co-investigator in funded projects from microelectronics industries like Motorola (USA), Siemens AG (Germany), National Semiconductor Corp. (USA), Renesas (Japan), Indian Telephone Industries, Bharat Electronics Ltd. (India), Semiconductor Complex Ltd. (India), etc.
  • Member, Working Group on Technology of the National Microelectronics Council, Govt. of India, 1988-1994
  • Member, Program Advisory Committee on Electrical, Electronics and Computer Engineering, Department of Science & Technology, Govt. of India, 1998-2003
  • Member, Solar Energy Research Advisory Council, Ministry of New and Renewable Energy, Govt. of India, 2011-2015
  • Member, Scientific Advisory Committee to the Cabinet (SAC-C), 2008-2018

Professional Society Activities

  • Editor, IEEE Transactions on Electron Devices, 1996-2003
  • Distinguished Lecturer of the IEEE Electron Devices Society, 2001-2005
  • Founding Chair, IEEE APS/EDS Bombay Chapter, 1999-2000
  • Chair, IEEE Bombay Section, 2001-2002
  • Chair, IEEE Asia-Pacific Regions/Chapters Subcommittee, 2005-2006
  • Chair, IEEE EDS Technical Committee on Photovoltaic Devices, 2017-2020
  • Associate Editor, Frontiers in Energy Research, 2015-

Research Projects Undertaken

Microelectronics Project (1983-1995)
Funded by MHRD
This was the first project in the area of Microelectronics in the EE Department. It resulted in setting up of the “Microelectronics Laboratory” in the EE Annexe Ground Floor. In a sense it the 'mother' of all microelectronics and VLSI based activities and projects at IIT Bombay. It was extremely successful, and established IITB as a major - even leading - player in this emerging area in the early 1980's. It also resulted in the launch of the M.Tech. specialization 'Microelectronics', which focused on both MOS devices/technology and the newly emerging VLSI design. This programme went on to become one of the most popular programmes at IIT Bombay, and its graduates were highly sought out by the emerging VLSI design companies in India. The programme was replicated at many other IITs. Professor A. N. Chandorkar, Professor Rakesh Lal and I were the three faculty members intimately associated with this project. We were fortunate to have many excellent Ph.D. and M.Tech. students who worked on several aspects of Microelectronics. Some of the outstanding achievements of this project were: fabrication of high-quality SiO2 for the gate oxide of MOS transistors, detailed studies on the reliability of such oxides, fabrication of the first MOS transistors at IIT Bombay, development of novel measurement techniques for MOS devices, and design of MOS based circuits and programmable gate arrays.
Some publications related to this work:
1. C. Parikh and J.Vasi, “Accurate modelling of a depletion-mode MOSFET,” 3rd International Workshop on the Physics of Semiconductor Devices, Madras (1985).
2. R.Lal and J.Vasi, “Profiling generation lifetime in a MOS capacitor using a multistep constant capacitance technique,” Solid-St. Electron. 30, 801 (1987).
3. 2. S.S.Moharir, A.N.Chandorkar and J.Vasi, “An interface reaction mechanism for the dry oxidation of silicon,” J. Appl. Phys. 65, 2171 (1989).
4. K.Ramesh, A.N.Chandorkar and J.Vasi, “Electron trapping and detrapping in thermally nitrided silicon dioxide,” J. Appl. Phys. 65, 3958 (1989).
5. K.Ramesh, A.N.Chandorkar and J.Vasi, “Process dependence of breakdown field in thermally nitrided silicon dioxide,” J. Appl. Phys. 70, 2299 (1991).
6. R.M.Patrikar, R.Lal and J.Vasi, “Power law model for positive charge buildup in silicon dioxide due to high-field stressing,” Solid-St. Electron. 36, 723 (1993).
7. R.M.Patrikar, R.Lal and J.Vasi, “Net positive charge buildup in various MOS insulators due to high-field stressing,” IEEE Electron Device Lett. 14, 530 (1993).

VLSI Design Centre (Phase 1) (1987-1992)
Funded by Department of Electronics
The Microelectronics Project initiated research in the area of VLSI Design. This was followed by a major project by the Department of Electronics (later re-christened Ministry of Electronics and Information Technology) involving several IITs and IISc to promote research and manpower training in this area. This was an important initiative of DOE, and eventually led to the setting up of many multinational chip design companies in India during the 1990s and 2000s. This project was led at IIT Bombay by Prof. S.S.S.P. Rao of CSE Department, and included several persons from EE Department, including Prof. A. N. Chandorkar, Prof. H. Narayanan, Prof. K. V. V. Murthy and myself. The focus of the activities was to design MOS-based chips, to develop the design tools needed for automated chip design, and to develop new and fast circuit simulators. The VLSI Design Centre continued for one more phase (1993-1998), before morphing into the highly successful Special Manpower Development Programme (SMDP) of MeitY. However, in order to focus my interest on devices and technology, I did not participate further in the VLSI design activities, except as an interested onlooker. Professor Chadorkar continued to play a major role in this project and established strong links with VLSI companies in India and globally.

Radiation Effects in MOS Devices (1988-1994)
Funded by Department of Electronics
This was one of the most exciting and productive projects during my years at IIT Bombay. Four faculty members from EE Department were involved: Prof. A. N. Chandorkar, Prof. Rakesh Lal (they were the PIs), Prof. Dinesh Sharma and myself, plus a large number of students over the years. It was a highly goal-directed project – to develop a rad-hard technology for India during the ‘technology denial’ years of the 1980’s and 1990’s. But it also resulted in a plethora of publications, since a lot of basic physics and technology was involved. Indeed, it was a classic example of a project where attempts to develop a state-of-the-art technology for national requirements results in high-quality research papers as well. Some of the outcomes of this project included the development of a 1 Mrad rad-hard technology using ‘reoxidized nitrided oxide’ (RNO), detailed understanding of trap and interface state generation due to radiation, and a methodology to prevent radiation-induced leakage in CMOS circuits. Our expertise in rad-hard MOS technology developed during this project allowed us to take up several more projects in the area of radiation effects.
Some publications related to this work:
1. V.Ramgopal Rao and J.Vasi, “Radiation-induced interface-state generation in reoxidized nitrided SiO2,” J. Appl. Phys. 71, 1029 (1992).
2. N.Bhat and J.Vasi, “Interface-state generation under radiation and high-field stressing in RNO MOS capacitors,” IEEE Trans. Nucl. Sci. 39, 2230 (1992).
3. A. Mallik, J.Vasi and A.N.Chandorkar, “A study of radiation effects on reoxidized nitrided oxide MOSFETs, including effects on mobility,” Solid-St. Electron. 36, 1359 (1993).
4. A.Mallik, A.N.Chandorkar and J.Vasi, “Electron trapping during irradiation in RNO,” IEEE Trans. Nucl. Sci. NS-40, 1380 (1993).
5. A. Mallik, A.N. Chandorkar and J. Vasi, “Capture cross-section of hole traps in reoxidized nitrided oxide measured by irradiation,” Solid-St. Electron. 38, 1851 (1995).
6. V. Ramgopal Rao, D.K. Sharma and J. Vasi, “Neutral electron trap generation under irradiation for RNO gate dielectrics,” IEEE Trans. Electron Devices 43, 1467 (1996).

Process Simulation for CMOS Technology (1992-1995)
Funded by Department of Electronics
This was an important ‘national’ project whose goal was to come out with an indigenous process simulator (surpassing the capabilities of SUPREM). It was undertaken as a joint project by several institutions and laboratories in India. Besides IIT Bombay, these included IIT Kharagpur, IIT Madras, NPL, ITI, TIFR, University of Pune, and University of Calcutta, among others. IIT Bombay’s main role was to write the simulator code (in Fortran!) for oxidation, especially including new models for thin oxides. Others from the Microelectronics Group who participated in this project were Prof. A. N. Chandorkar and Prof. Dinesh Sharma. The most interesting part of this project was that it required all the teams to meet together twice a year (rotating through the different locations of the participating organizations), and therefore gave all of us an opportunity to get to know each other, and build up what might be called an Indian Microelectronics community. This project was ably guided by Dr. K. S. Chari, a passionate scientist at DOE (now MeitY).
Some publications related to this work:
1. S.S.Moharir, A.N.Chandorkar and J.Vasi, “An interface reaction mechanism for the dry oxidation of silicon,” J. Appl. Phys. 65, 2171 (1989).
2. S.S.Moharir, J.Vasi and A.N.Chandorkar, “Numerical simulation of silicon oxidation kinetics involving diffusion of oxygen into the silicon substrate,” Proceedings of NASECODE VI, Boole Press Limited, Dublin, Ireland (1989).
3. S.S. Moharir, J. Vasi and A.N. Chandorkar, “Data and modelling for HCl oxidation of silicon,” Journal of the Institution of Engineers (India) 76, 29 (1995).

2-D Device Simulation for MOS Devices (1995-1998)
Funded by Department of Electronics
This project continued the pan-India simulation activity undertaken earlier. The focus now shifted to 2-D device simulation, and the goal was to develop a 2-D MOS simulator, surpassing the capabilities of the then well-known MOS device simulator MINIMOS. IIT Bombay’s part was to include in the device simulator aspects which would enable it to be used to model and simulate radiation effects (this would build upon and complement the earlier project of radiation effects in MOS devices, which was primarily experimental). This aspect was very challenging (and pioneering when it was initiated), since it required modelling and simulation of transport in the oxide as well. We started with a 1-D MOS capacitor simulator, and then moved on to a 2-D MOSFET simulator. This project continued the semi-annual meetings initiated during the process simulation project, and further cemented the well-knit semiconductor community in India, with IIT Bombay’s Microelectronics Group emerging as a leader. Prof. Dinesh Sharma and Prof. Amitava Das, besides myself, contributed to this project.
Some publications related to this work:
1. V.Vasudevan and J.Vasi, “A numerical simulation of hole and electron trapping due to radiation in silicon dioxide,” J. Appl. Phys. 70, 4490 (1991).
2. A.Phanse, D.Sharma, A.Mallik and J.Vasi, “Carrier mobility degradation in MOSFETs due to oxide charge,” J. Appl. Phys. 74, 757 (1993).
3. V.Vasudevan and J.Vasi, “A simulation of the multiple trapping model for CTRW transport,” J. Appl. Phys. 74, 3224 (1993).
4. V.Vasudevan and J.Vasi, “A two-dimensional numerical simulation of oxide charge build up in MOS transistors due to radiation,” IEEE Trans. Electron Devices 41, 383 (1994).
5. N. Talwalkar, A. Das and J. Vasi, “Dispersive transport of carriers under non-uniform electric field,” J. Appl. Phys. 76, (1995).
6. P.Zaman, S.J.Patrikar, M.Goel, V.Bharadwaj, D.K.Sharma and J.Vasi, “RADCAP : A MOS capacitor simulator for radiation effects,” 8th International Workshop on the Physics of Semiconductor Devices, New Delhi (1995).
7. S.Ekbote, D. Tambe, P. Zaman, H.K. Dangat, M.Khare, P.Sinha, S.Rodd, N.Bhukhanwala, J.Vasi, D.K. Sharma and A.Das, “Simulation of radiation effects in MOSFETs,” 8th International Workshop on the Physics of Semiconductor Devices, New Delhi (1995).
8. S. Subbaraman, D. K. Sharma, J. Vasi and A. Das, “A Monte Carlo approach for incorporation of memory effect in switched gate bias experiments,” J. Appl. Phys. 83, 3419 (1998).

Radiation Effects in HBTs (1996-1998)
Funded by DST
This was a project which brought together the complementary expertise of radiation effects at IIT Bombay and bipolar HBTs at University of Twente in Netherlands. It provided, for me, a stimulating and informative digression away from MOS, which had been (and continued to be for many more years) the main focus of my research. The devices were fabricated at Twente, and extensive measurements and modelling done at IIT Bombay. Interestingly, it turned out that the major cause for radiation damage in HBTs also was the build-up of charge and interface states in the silicon dioxide layer which sits atop the HBT, which was already well understood by us. Prof. Rakesh Lal and I were involved in this project, together with Prof. L. Nanver from Twente.
Some publications related to this work:
1. A.Topkar, T. Mathew, R. Lal, J. Vasi and L. Nanver, “Radiation induced degradation of bipolar transistors,” 9th International Workshop on the Physics of Semiconductor Devices, New Delhi (1997).
2. A. Topkar, S. Lodha, A. T. Mahfooz, R. Lal, J. Vasi and L. Nanver, “Ionizing radiation induced degradation of SiGe HBTs,” 10th Int. Workshop on Physics of Semiconductor Devices, New Delhi (1999).

Compact Modelling for MOS Devices (1996-1998)
Funded by National Semiconductor (USA)
As IIT Bombay’s reputation in MOS device research came to be recognized internationally, we received funding from a number of international semiconductor companies. The first of these was National Semiconductor Corp. of USA, which funded a project to develop specific compact models. Indeed, we believe this was the first project at IIT Bombay sponsored by a major international company. This project was the Microelectronics Group’s first foray into the type of compact modelling used for SPICE simulation. Due to confidentiality and IP concerns, no publications resulted from this project.

Research and Manpower Training in Scaled MOS Devices (1996-1999)
Funded By Siemens AG (Germany)
In the late 1990’s, Siemens was the leading European company working on semiconductors (they later spun off this business as Infineon). Siemens set up a tripartite collaboration between Siemens AG, IIT Bombay and Universität der Bundeswehr in Munich. Since one of the goals of this project was manpower training, this project resulted in several students from the Microelectronics Group at IITB going to Germany. Prof. Dinesh Sharma and I were the main faculty members from the Group to be involved.
Some publications related to this work:
1. V.R. Rao, I. Eisele, R.M. Patrikar, D.K. Sharma, J. Vasi and T. Grabolla, “High-field stressing of LPCVD gate oxides,” IEEE Electron Device Lett. 18, 84 (1997).
2. V. Ramgopal Rao, W. Hansch, S. Mahapatra, D. K. Sharma, J. Vasi, T. Grabolla and I. Eisele, “Low Temperature-High Pressure Grown Thin Gate Dielectrics for MOS Applications,” Microelectronic Engineering 48, 223 (1999).

Manpower Training in Microelectronics and VLSI Design (1998-2010)
Funded by Tata Consultancy Services (TCS)
This consequential project between TCS and the Microelectronics Group at IIT Bombay arose from an initiative by the legendary Mr. F. C. Kohli of TCS. As the importance of embedded software became increasingly apparent, many software companies realized that they needed to have a presence in hardware aspects as well. The lead was taken by the visionary Mr. Kohli, through an interesting IEEE connection. Mr. Kohli, the founder of IEEE in India, requested Prof. K. Shankar to put him in touch with the Microelectronics group at IIT Bombay. Prof. Shankar contacted me (IEEE connections!), and four of us from IITB – Prof. Shankar, Prof. Dinesh Sharma, Prof. Chandorkar and myself – met Mr. Kohli in his office at Nariman Point. Mr. Kohli came to know that the total number of post-graduates being trained in the areas of microelectronics and VLSI in India was around 200-300, and was shocked at this number. He felt the number should run into several thousands. One outcome of this was a TCS sponsored activity in the EE Department, where TCS supported 15-20 M.Tech. students every year with full stipends. TCS also supported the purchase of equipment to be used by the students. The students had no commitment to join TCS (nor did TCS guarantee jobs for them), as Mr. Kohli believed that this was something necessary for India, not just TCS. This activity was co-ordinated for all the years by Prof. Dinesh Sharma and Prof. A. N. Chandorkar, and enabled IIT Bombay to establish a pre-eminent position in Microelectronics and VLSI education by the 2000’s. Another wider outcome, led by Mr. Kohli, was to increase the number of post-graduate programmes in many universities and colleges all over India. Mr. Kohli and Prof. Sharma were the authors of an influential report, “Promoting Microelectronics Education: The Indian Imperative”, which was used by MeitY in their SMDP programmes.

Models for Scaled MOS Transistors (2000-2002)
Funded by Motorola Inc. (USA)
This was another project by a leading US-based semiconductor company to develop models for advanced MOS devices. One important focus in this case was the development of non-quasi-static (NQS) models, which became necessary as MOS transistors started entering the high-speed and high-frequency regimes, where the traditional quasi-static approximations would not apply. Prof. Mahesh Patil and I worked on this project with several students.
Some publications related to this work:
1. A. S. Roy, J. Vasi, and M. B. Patil, “A new approach to model Non-Quasi-Static (NQS) effects in MOSFET’s Part I: Large-signal analysis,” IEEE Trans. Electron Devices 50, 2393 (2003).
2. A. S. Roy, J. Vasi, and M. B. Patil, “A new approach to model Non-Quasi-Static (NQS) effects in MOSFET’s Part II: Small-signal analysis,” IEEE Trans. Electron Devices, 50, 2401 (2003).

Design and Technology of Rad-hard MOS Circuits (2000-2004)
Funded by IITB-ISRO Cell
Following up on the work done on rad-hard MOS technology, this project included some aspects of design approaches for rad-had circuits. CMOS circuits which flew into space not only required use of a radiation-hard technology, but also special circuit design techniques, both for ‘total-dose’ hardness as well as to prevent radiation-induced single-event upsets (SEUs). The total dose radiation-hardness-by design methods include the use of annular-gate MOSFETs and enclosed source/drain MOSFETs. This project involved Prof. Sharma, Prof. Lal and myself.
Some publications related to this work:
1. P. Jain, J. Vasi and R. Lal, “SEU reliability analysis of advanced deep submicron transistors,” IEEE Trans. Device and Materials Reliability 5, 289 (2005).
2. P. Jain, J. Vasi and R. Lal, “Single-event-induced barrier lowering in deep sub-micron CMOS devices and circuits,” 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2004), Taiwan (2004).

Centre of Excellence in Nanoelectronics (Phase 1) (2005-2010)
Funded by Ministry of Electronics and Information Technology (MeitY)
This project changed the trajectory of microelectronics research at IIT Bombay. In 2003, we were approached by Dr. Chidambaram, Principal Scientific Adviser to the Government of India and Chairman of the Scientific Advisory Committee to the Cabinet (SAC-C) through Prof. S. P. Sukhatme, ex-Director of IIT Bombay (1995-2000) to discuss the possibility of a national Nanoelectronics Project. Some of us from the Microelectronics Group – Prof. Rakesh Lal, Prof. A. N. Chadorkar, Prof. Ramgopal Rao, Prof. Dinesh Sharma and myself – went to meet Dr. Chidambaram at his Mumbai BARC office. Dr. Chidambaram said that India had missed the microelectronics bus, but with fundamentally new science and technology emerging at the nano scale, India should take advantage of the nanoelectronics revolution. He proposed to visit several universities and R&D labs in India to see how best this could be done. Later that year, he called a meeting of all stake-holders in Delhi, and during discussions there, he expressed the opinion that this venture should be taken up by academic institutions so that they could involve a large number of research students. He further said that in his opinion IIT Bombay and IISc were best suited to take this up, based on their existing broad-based activities, focusing respectively on the technology and science parts of the nanoelectronics. He stated that it would be good to fund only two institutions, and give each the critical funding required. Accordingly, IIT Bombay and IISc submitted proposals to MeitY for funding for the “Centres of Excellence in Nanoelectronics”. An important and critical facet of this proposal was that it was a single joint proposal, not two separate ones. Another important facet was that at both IIT Bombay and IISc, the project was highly multi-disciplinary. The proposal was submitted to MeitY in 2004, with myself and Prof. Ramgopal Rao as the PIs from IIT Bombay and having 19 other investigators from 6 Departments. The funding was approved and received in late 2005 (I was on sabbatical then), and Prof. Rao took stewardship of the project, and went on do an outstanding job. The activities envisaged under this project included the development of nanoscale CMOS devices, nanosystems and sensors, and new techniques for characterization and modelling. The sensors work, in particular, was an extremely successful interdisciplinary activity, and Prof. Rao and others were able to launch 2 successful start-ups arising from this work. The CEN project resulted in setting up the IITB Nanofabrication Facility, with state-of-the-art equipment. Prof. Richard Pinto, Adjunct Professor (recently retired from TIFR) played a critical role in setting up the facility. Mention must also be made here of the extremely positive engagement by two of MeitY’s personnel, Dr. U. P. Phadke and Dr. S. P. Uttam, whose advice and experience were invaluable in steering the proposal through the MeitY hierarchy.
This project naturally resulted in many publications and patents from all the investigators and their students. Some in which I was personally involved were:
1. V. Hariharan, J. Vasi and V. R. Rao, “Drain current model including velocity saturation for symmetric double-gate MOSFETs,” IEEE Transactions on Electron Devices 55, 2173 (2008).
2. V. Hariharan, J. Vasi and V. Ramgopal Rao, “An Improvement to the Numerical Robustness of the Surface Potential Approximation for Double-Gate MOSFETs,” IEEE Transactions on Electron Devices 56, 529 (2009).

Applied Materials Nanomanufacturing Laboratory (2006-2011)
Funded by Applied Materials, Inc.
With the establishment of the Centre of Excellence in Nanoelectronics (CEN) at IIT Bombay, and the consolidation of IIT Bombay as a leading centre for nanoelectronics research, several international companies expressed interest in setting up connections and collaborations with IIT Bombay. Applied Materials from USA was one of the major such companies. The initiation of this activity came through Prof. Souvik Mahapatra, who had interacted with them during his stay at Bell Labs. My initial role in this was to visit Applied Materials in Santa Clara in early 2006 (when I was on sabbatical) to discuss possibilities of a wider collaboration. After my return to IIT Bombay (and when I was Deputy Director), IIT Bombay and Applied Materials embarked on detailed negotiations for Applied to set up the endowed Applied Materials Nanomanufacturing Laboratory. They would donate three major industry-scale tools, support several research projects, and station at least 4 engineers and technicians at IIT Bombay. Applied would have 33% time on usage of the equipment, and IIT Bombay would initially purchase and stock some of the essential spares. The support and forward-looking approach by the IIT Bombay Director, Prof. Ashok Misra, played a crucial role in getting the MOU for this project approved. The Laboratory was inaugurated in 2007 by the Applied Materials CEO Mr. Michael Splinter and Prof. Misra, and so set the stage for extensive interactions between Applied Materials and IIT Bombay over the next 5 years and beyond. Through this activity, our students and faculty had access to and exposure to professional industry-scale equipment, and Applied Materials had access to the expertise and students from IIT Bombay. Of the many projects which Applied Materials separately funded at IIT Bombay was one on charge trap flash memories, which was led by Prof. Mahapatra, and in which I was involved.
Some publications related to this work:
1. C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, “Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler Nordheim Tunneling Program/Erase Operation,” IEEE Electron. Device Lett. 30, 171 (2009).
2. C. Sandhya, A. B. Oak, N. Chattar, A. S. Joshi, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, “Impact of SiN composition variation on SANOS memory performance and reliability under NAND (FN/FN) operation,” IEEE Trans. Electron Devices, 56, 3123 (2009).
3. C. Sandhya, A. B. Oak, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, “Study of P/E cycling endurance induced degradation in SANOS memories under NAND (FN/FN) operation,” IEEE Trans. Electron Devices, 57, 1548 (2010).

Indian Nanoelectronics Users Programme (Phase 1) (2008-2013)
Funded by Ministry of Electronics and Information Technology (MeitY)
This was a project which gave many of us at IIT Bombay great internal satisfaction. The origin of this project lay in the hope expressed by Dr. Chidambaram (ardently supported by some of us at IIT Bombay) that the Government of India, while setting up the two CENs at IIT Bombay and IISc, would expect that these Centres with state-of-the-art equipment would be accessible to researchers from all over the country. The broad contours of the Indian Nanoelectronics Users Programme (INUP) were conceptualised by Prof. Rakesh Lal and me in 2004 itself, and inserted as follow-up project in the proposal for CEN. However, the INUP proposal was formally submitted in 2008, after the CEN facilities were up and available for other users. The PIs for this were Prof. Ramgopal Rao and Prof. Contractor, and I and Prof. Kottantharayil were the co-PIs. We proposed that the funding for the usage of the CEN facilities be given directly to IIT Bombay, rather than to the users, which would allow us to obtain consumables for the users, as well as to fund their travel and stay at IIT Bombay. Further, review and approval of the proposals received from users would be done by the IIT team, so as to ensure a prompt turn-around of 4 weeks or less. These rather radical proposals were, amazingly, agreed to by the visionary MeitY team, led by Dr. Uttam. We also proposed that all IP arising out of the work would be solely held by the external users, and IIT Bombay have no part in the IP (but conversely, also, IIT Bombay would not have any responsibility for the failure of a project). The implementation of this project went in several phases. First, we held ‘Familiarization Workshops’ both at IITB and outstation locations to inform students of the programme, the potential for nanoelectronics as well as facilities available. Next, intensive ‘Hands-on Workshops’ were held for researchers intending to come to CEN to pursue their projects. The students also submitted their proposals, which were approved (or not) within 3-6 weeks. The students could then plan their visit to IITB by booking the tools required by them through an on-line portal. Finally, the students would arrive at IITB, with all logistics being taken care of by INUP, and mentorship being provided by IITB faculty and peer assistance by IITB students and research staff. The activity was carefully nurtured and co-ordinated by Dr. K. Nageswari who became the face of INUP for hundreds of students across the country. The project was a stunning success, and the number of students who benefited from the programme exceeded not only the promised deliverable, but also our wildest dreams. During this Phase I of the INUP project, over 1500 students from 300+ institutions benefited from the Familiarization Workshops, and 500 students from 200 institutions participated in 28 Hands-on Workshops. Over 200 actual projects were undertaken at the nano facility at IITB, with the research students spending from 1 week to more than 6 months here. This work resulted in over 170 publications and 11 patents, and the work done under INUP contributed to 60 Ph.D. and 45 M.Tech. theses at various universities all over India. This torrent of activity attested to the great interest in experimental research at even the smaller universities and colleges in India.
As mentioned, this project did not result in any publications for IITB (all IP being held the users), except one which explained the methodology of the programme for wider dissemination:
1. V. Mishra, G. K. Ananthasuresh, N. Bhat, H. S. Jamadagni, S. Mohan, T. Murthy, R. Pratap, S. A. Shivashankar, V. Venkataraman, K. J. Vinoy, K. Nageswari, A. Q. Contractor, A. Kottantharayil, R. Pinto, V. R. Rao, and J. Vasi, “Indian Nanoelectronics Users Program: An outreach vehicle to expedite nanoelectronics research in India,” 18th Biennial University/Government/Industry Micro/Nano Symposium (UGIM), W.Lafayette, USA (2010).

Centre of Excellence in Nanoelectronics (Phase 2) (2011-2016)
Funded by Ministry of Electronics and Information Technology (MeitY)
Upon successful completion of Phase 1 of CEN, MeitY was ready to support Phase 2. This proposal was submitted in 2010, again as a joint single proposal of IITB and IISc, and was sanctioned in 2011. The PIs from IITB were now Prof. Ramgopal Rao and Prof. A. Q. Contractor. I continued to be involved as one of the Investigators, though, as my interest shifted to photovoltaics with the establishment of NCPRE, my involvement in pure nano-based research diminished gradually. Interestingly, my early work in PV focused on silicon nano-crystal based solar cells, affording me a smooth transition from nano to photovoltaics. One signal development, which started during Phase 1, and continued into Phase 2, was that the state-of-the-art facilities which were set up enabled the EE Department to recruit some outstanding young faculty members in the area of nanoelectronics, including Profs. Swaroop Ganguly, Saurabh Lodha, Udayan Ganguly, Subhananda Chakrabarti, Ashwin Tulapurkar, Dipankar Saha, Pradeep Nair and Apurba Laha, all of whom got involved in Phase 2 of CEN. It could now be argued that the Department now hosted the most talented group of faculty members in the area of nanoelectronics in India, and perhaps anywhere in the world.
Some publications related to this work:
1. N. R. Mavilla, C. S. Solanki, and J. Vasi, “Raman spectroscopy of silicon-nanocrystals fabricated by inductively coupled plasma chemical vapor deposition,” Physica E: Low-dimensional Systems and Nanostructures 52, 59 (2013).
2. N. R. Mavilla, C. S. Solanki, and J. Vasi, “Optical Bandgap Tunability of Silicon Nanocrystals Fabricated by Inductively Coupled Plasma CVD for Next Generation Photovoltaics,” IEEE Journal of Photovoltaics 3, 1279 (2013).

Indian Nanoelectronics Users Programme (Phase 2) (2014-2019)
Funded by Ministry of Electronics and Information Technology (MeitY)
Phase 1 of INUP was completed with great success, and created a tremendous impact all over India. MeitY requested us to continue this project for another 5 years. This was the genesis of INUP Phase 2. This phase of the project had as the PIs and Co-PIs Profs. Anil Kottantharayil, Soumyo Mukherji, Saurabh Lodha, Swaroop Ganguly and Ashwin Tulapurkar. I continued to be involved as an Investigator, and played a role in encouraging solar cell fabrication to become a part of INUP. As in Phase 1 of INUP, Dr. Nageswari continued to play a crucial role in this phase as well.

National Centre for Photovoltaic Research and Education (Phase 1) (2010-2015)
Funded by Ministry of New and Renewable Energy (MNRE)
This project proved to be a turning point in my research career. Its origin has an interesting story. Dr. R. Chidambaram, whose brainchildren CEN and INUP were, had witnessed with satisfaction the progress of CEN and INUP at IIT Bombay and IISc. With the impending launch of the Jawaharlal Nehru National Solar Mission, Dr. Chidambaram approached me in mid-2009, saying that in his opinion, IIT Bombay had the necessary capability to set up a major centre to pursue research and education in solar photovoltaics (PV), which would support the national mission. He was, of course, aware of the capabilities we had built up in semiconductor (and especially silicon) processing, which could play a major role in solar cells. He was also aware that IITB had recently set up the Department of Energy Science and Engineering. For me, this was an attractive option – I had begun to feel that my work on ultra-scaled CMOS was becoming increasingly exotic, and had little connection to the ground requirements in India. Solar energy, on the other hand, had immediate and direct relevance. I discussed this with the Director who was very supportive of this initiative. One problem for us at IITB was that very few faculty members at IITB (myself included) had any background in PV. One exception was Prof. Chetan Singh Solanki who had recently joined the Department of Energy Science and Engineering. I believed strongly that that our initiative should cover a broad area of solar PV, including silicon solar cells, new materials, power electronics, storage, reliability and policy. We accordingly contacted many faculty members in various Departments, to gauge interest, and persuade some to shift their research focus. This effort was moderately successful, and we submitted a proposal for the ‘National Centre for Photovoltaic Research and Education’ (NCPRE) to the Ministry of New and Renewable Energy (MNRE) in January 2010. In the meantime, MNRE had published an excellent mission document for the JNNSM, in which it was already mentioned that one of the facets would be “Setting up of a National Centre for Photovoltaic Research and Education at IIT Mumbai …”. The project was approved in September 2010, with myself and Chetan as the PIs, Prof. B. G. Fernandes as a co-PI, and 44 other investigators from 10 Departments (though it turned out that only about 30 contributed to any extent). Two of the investigators who deserve special mention are Prof. B. M. Aroa and Prof. K. L. Narasimhan, who had retired recently from TIFR after distinguished careers there, and has joined IIT Bombay as Visiting/Adjunct Professors, and contributed significantly to several aspects of the project. The main areas of research of NCPRE were c-Si solar cells, new materials and devices like dye-sensitized and organic solar cells, PV systems and modules (including power electronics and storage), and modelling and characterization. Education and training was also given much importance. One important deliverable of this project was to study the reliability of PV modules. It turned out that no one in our team was willing to take this up, so (given my prior experience with MOS reliability), I decided to do so myself. This turned out to be, for me, a far-reaching decision, and we were able to establish a leading group at NCPRE in the area of PV module reliability, which undertook the biannual ‘All-India Surveys of PV Module Reliability’. Phase 1 of NCPRE was very successful, and resulted in 344 journal and conference papers and 13 patents.
Some publications related to this project in which I was involved:
1. S. Chattopadhyay, R. Dubey, V. Kuthanazhi, J. J. John, C. S. Solanki, A. Kottantharayil, B. M. Arora, K.L. Narasimhan, V. Kuber, J. Vasi, A. Kumar, O.S. Sastry, “Visual Degradation in Field-aged Crystalline Silicon PV Modules in India and Correlation with Electrical Degradation,” IEEE Journal of Photovoltaics 4, 1470, (2014).
2. N. R. Mavilla, V. Chavan, C. S. Solanki, and J. Vasi, “Study of temperature-dependent charge conduction in silicon-nanocrystal/SiO2 multilayers,” Thin Solid Films 612, 41 (2016).
3. R. Dubey, S. Chattopadhyay, V. Kuthanazhi, A. Kottantharayil, C. S. Solanki, B. M. Arora, K.L. Narasimhan, J. Vasi, B. Bora, Y. K. Singh and O.S. Sastry, “Comprehensive study of performance degradation of field-mounted PV modules in India,” Energy Science and Engineering 5, 51 (2017).
4. C. S. Solanki, B. G. Fernandes, B. M. Arora, P. Sharma, V. Agarwal, M. B. Patil, J. Vasi, D. B. Phatak, Mukta Atrey, K. Moudgalya and K. Bijlani, “Teach a 1000 Teachers: A methodology for the rapid ramp-up of photovoltaics manpower required for India’s National Solar Mission”, 38th IEEE Photovoltaic Specialists Conference, Austin, USA (2012).
5. V. Kuthanazhi, S. Chattopadhyay, R. Dubey, J. J. John, C. S. Solanki, A. Kottantharayil, B. M. Arora, K.L. Narasimhan, J. Vasi, A. Kumar, O. S. Sastry, “Linking Performance of PV Systems in India with Socio-Economic Aspects of Installation,” 40th IEEE Photovoltaic Specialists Conference, Denver, USA (2014).
6. R. Dubey, S. Chattopadhyay, V. Kuthanazhi, J. J. John, J. Vasi, A. Kottantharayil, B. M Arora, K.L. Narsimhan, C. S. Solanki, A. Kumar, O.S. Sastry, “Performance Degradation in Field-aged Crystalline Silicon PV Modules in Different Indian Climatic Conditions,” 40th IEEE Photovoltaic Specialists Conference, Denver, USA (2014).
7. Shashwata Chattopadhyay, Rajiv Dubey, Vivek Kuthanazhi, Jim Joseph John, Chetan Singh Solanki, Anil Kottantharayil, Brij M. Arora, K.L. Narasimhan, Juzer Vasi, Arun Kumar, O.S. Sastry, “Visual Degradation in Field-aged Crystalline Silicon PV Modules in India and Correlation with Electrical Degradation,” 40th IEEE Photovoltaic Specialists Conference, Denver, USA (2014).
8. R. Dubey, S. Chattopadhyay, J.J. John, B.M. Arora, A. Kottantharayil, C. S. Solanki, K. L. Narasimhan, and J. Vasi, “Daylight Electroluminescence Imaging by Image Difference Technique,” 6th World Conference on Photovoltaic Energy Conversion and 41st IEEE Photovoltaic Specialists Conference, Kyoto, Japan (2014).
9. Shashwata Chattopadhyay, Rajiv Dubey, Vivek Kuthanazhi, Jim Joseph John, Chetan Singh Solanki, Anil Kottantharayil, Brij M. Arora, K.L. Narasimhan, Juzer Vasi, Birinchi Bora, Yogesh Kumar Singh and O.S. Sastry, “All India Survey of Photovoltaic Module Degradation 2014: Survey Methodology and Statistics,” 42nd IEEE Photovoltaic Specialists Conference, New Orleans, USA (2015).
10. Rajiv Dubey, Shashwata Chattopadhyay, Vivek Kuthanazhi, Jim Joseph John, Chetan Singh Solanki, Anil Kottantharayil, Brij M. Arora, K.L. Narasimhan, Juzer Vasi, Birinchi Bora, Yogesh Kumar Singh and O.S. Sastry, “Correlation of Electrical and Visual Degradation seen in Field Survey in India,” 43rd IEEE Photovoltaic Specialists Conference, Portland, USA (2016).

Solar Energy Research Institute for India and the US (SERIIUS) (2012-2018)
Funded by DST (India) and Department of Energy (USA)
In late 2010, a major collaborative Indo-US programme – the ‘Joint Clean Energy Research and Development Centers’ was announced. At IITB, having just established NCPRE, we felt we would be in a good position to bid for the solar energy centre. The funding available was $ 50 million for a 5-year period, of which half would be for US entities and half for Indian. Further, half of the amount would have to be raised from companies or other internal sources, and DOE (for USA) and DST (for India) would provide matching government funding. We tied up with IISc and other academic institutions in India, as well as some companies; in the USA, our major partner was the National Renewable Energy Laboratory (NREL), as well as several other universities, companies and R&D laboratories. The proposal for SERIIUS (‘Solar Energy Research Institute for India and the US’) was submitted in 2011, and the project was approved in 2012. The project had 24 organizations, over 150 investigators, and as many students. The Project Co-leads were Prof. Kamanio Chattopadhyay (India) and Dr. Larry Kazmerski (USA) (the latter was replaced later by Dr. David Ginley). The project consisted of 3 main parts – photovoltaics, concentrating solar power, and solar energy integration. Each of these sectors had Research Thrust Co-Leads, and I was the Co-Lead for PV. SERIIUS turned out to be a great project, which enabled IIT Bombay to establish deep contacts with the leading PV groups in India and USA. We had semi-annual meetings every year, one in USA and one in India. It was also technically very demanding, with activities on HJT cells, multiscale modelling, reliability and soiling, new materials like CZTS and perovskites, and flexible glass substrates. It was a very successful project, and received plaudits from both DOE and DST. Phase 2 of SERIIUS? It was in preparation, but a change of administration in the US in 2016 caused the plan to be abandoned.
Some joint Indo-US publications related to this work:
1. Xingshu Sun, R. Dubey, S. Chattopadhyay, Mohammad Ryyan Khan, Raghu Vamsi Chavali, Timothy J. Silverman, Anil Kottantharayil, Juzer Vasi, and Muhammad Ashraful Alam, “A novel approach to thermal design of solar modules: Selective-spectral and radiative cooling,” 43rd IEEE Photovoltaic Specialists Conference, Portland, USA (2016).
2. G. Tamizhmani, S. Tatapudi, R. Dubey, S. Chattopadhyay, C. Solanki, J. Vasi, B. Bora, O. S. Sastry and A. Kottantharayil, “Comparative Study of Performance of Fielded PV Modules in Two Countries,” 26th International Photovoltaic Science and Engineering Conference, Singapore (2016).
3. S. Chattopadhyay, C. S. Solanki, A. Kottantharayil, K.L. Narasimhan, J. Vasi, S. Tatapudi, and G. TamizhMani, “Quantification of PV Module Discoloration using Visual Image Analysis,” 44th IEEE Photovoltaic Specialists Conference, Washington DC, USA (2017).
4. David Ginley, William Tumas, Marisa Howe, Pradip Dutta, Clifford Ho, Juzer Vasi, Maikel Van Hest, Aimee Curtright, Parveen Kumar, and Kamanio Chattopadhyay, “Solar Energy Research Institute for India and the US (SERIIUS): A Focused Solar Consortium,” 7th World Conference on Photovoltaic Energy Conversion and 45th IEEE Photovoltaic Specialists Conference, Waikoloa, Hawaii, USA (2018).
5. S. Khatavkar, M. Kulasekaran, C. V. Kannan, V. Kumar, K. L. Narasimhan, P. R. Nair, J. M. Vasi, M. L. Contreras, M. F. A. M. vanHest, and B. M. Arora, “Measurement of Relaxation Time of Excess Carriers in Si and CIGS Solar Cells by Modulated Electroluminescence Technique,” Physica Status Solidi A, 215 (2018).
6. (Book Chapter) D. Ginley at al., “Sustainable Photovoltaics” in Solar Energy Research Institute for India and the United States (SERIIUS): Lessons and Results from a Binational Consortium, David Ginley and Kamanio Chattopadhyay, eds., Springer Lecture Notes in Energy (2020).

National Centre for Photovoltaic Research and Education (Phase 2) (2016-2022)
Funded by Ministry of New and Renewable Energy (MNRE)
With the successful completion of Phase 1 of NCPRE, and through it and SERIIUS, the creation of a major centre in the area of solar PV, we felt that we should continue with Phase 2. Accordingly, we submitted a proposal for Phase 2 in late 2015, and this was approved in June 2016. This Phase of NCPRE built upon the strengths of Phase 1, and had 5 major areas of R&D: PERC silicon solar cells, Thin film materials and devices (especially perovskites and perovskite-on-silicon tandems), energy storage, power electronics, and module reliability. The PIs of Phase 2 were Profs. B. G. Fernandes and Chetan Singh Solaki, and the co-PIs were Profs. Anil Kottantharayil and Sagar Mitra. I continued my involvement in the module reliability aspect. Prof. Narendra Shiradkar, who joined in 2017, took over leadership of NCPRE's Reliability Group, and created an extremely dynamic environment, with many outstanding new initiatives. In Phase 2, we also looked at some policy-related matters, including solar manufacturing in India. In this we were helped by two Distinguished Visiting Professors, Prof. Larry (Kaz) Kazmerski and Prof. Rajiv Arya, who visited IITB for 2 months a year for several years.
Some publications related to this project in which I was involved:
1. S. Chattopadhyay, R. Dubey, S. Bhaduri, S. Zachariah, H. K. Singh, C. S. Solanki, A. Kottantharayil, N. Shiradkar, B. M. Arora, K. L. Narasimhan, and J. Vasi, “Correlating Infra-red Thermography with Electrical Degradation of PV Modules Inspected in All-India Survey of Photovoltaic Module Reliability 2016,” IEEE Journal of Photovoltaics 8, 1800 (2018).
2. Y. Golive, S. Zachariah, R. Dubey, S. Chattopadhyay, S. Bhaduri, H.K. Singh, B. Bora, S. Kumar, A.K. Tripathi, A. Kottantharayil, J. Vasi and N. Shiradkar, “Analysis of Field Degradation Rates Observed in All-India Survey of Photovoltaic Module Reliability 2018,” IEEE Journal of Photovoltaics 10, 560 (2020).
3. Hemant K. Singh, R. Dubey, S. Zachariah, K. L. Narasimhan, B. M. Arora, A. Kottantharayil, and J. Vasi, “Modified STC Correction Procedure for Assessing PV Module Degradation in Field Surveys,” 44th IEEE Photovoltaic Specialists Conference, Washington DC, USA (2017).
4. R. Dubey, S. Zachariah, S. Chattopadhyay, V. Kuthanazhi, S. Rambabu, S. Bhaduri, H. K. Singh, A. Sinha, C. S. Solanki, A. Kottantharayil, B. M. Arora, K. L. Narasimhan, J. Vasi, B. Bora, R. Kumar, and O. S. Sastry, “Performance of Field-Aged PV Modules in India: Results from 2016 All India Survey of PV Module Reliability,” 44th IEEE Photovoltaic Specialists Conference, Washington DC, USA (2017).
5. R. Dubey, S. Chattopadhyay, S. Zachariah, S. Rambabu, H. K. Singh, A. Kottantharayil, B. M. Arora, K. L. Narasimhan, N. Shiradkar, and J. Vasi, “On-Site Electroluminescence Study of Field-Aged PV Modules,” 7th World Conference on Photovoltaic Energy Conversion and 45th IEEE Photovoltaic Specialists Conference, Waikoloa, Hawaii, USA (2018).
6. R. Dubey, S. Chattopadhyay, S. Zachariah, V. Kuthanazhi, S. Rambabu, S. Bhaduri, H.K. Singh, A. Kottantharayil, B. M. Arora, K.L. Narasimhan, N. Shiradkar, B. Bora, O.S. Sastry and J. Vasi, “Investigation of Poor Performing PV Modules Observed in All-India Survey of PV Module Reliability,” 7th World Conference on Photovoltaic Energy Conversion and 45th IEEE Photovoltaic Specialists Conference, Waikoloa, Hawaii, USA (2018).
7. Y. Golive, S. Zachariah, R. Dubey, S. Chattopadhyay, S. Bhaduri, H.K. Singh, B. Bora, S. Kumar, A.K. Tripathi, A. Kottantharayil, J. Vasi and N. Shiradkar, “Analysis of Field Degradation Rates Observed in All-India Survey of Photovoltaic Module Reliability 2018,” 46th IEEE Photovoltaic Specialists Conference, Chicago, USA (2019).
8. S. Zachariah, R. Dubey, Y. R. Golive, S. Bhaduri, S. Chattopadhyay, C. S. Solanki, A. Kottantharayil, B. M. Arora, K. L. Narasimhan, H. K. Singh, J. Vasi and N. Shiradkar, “Electroluminescence Study of over 700 Fielded PV Modules in All India Survey 2018,” 46th IEEE Photovoltaic Specialists Conference, Chicago, USA (2019).
9. Y. R. Golive, S. Zachariah, S. Bhaduri, R. Dubey, S. Chattopadhyay, H. K. Singh, A. Kottantharayil, N. Shiradkar, and J. Vasi, “Analysis and Failure Modes of Highly Degraded PV Modules Inspected during the 2018 All India Survey of PV Module Reliability,” 4th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia (2020).
10. P. Ghosh, J. Vasi, A. Kottantharayil, N. Shiradkar, S. Kumar, R. Arya and L. L. Kazmerski, “Scaling Sustainable Integrated PV Manufacturing Globally,” 48th IEEE Photovoltaic Specialists Conference, Virtual, On-line (2021).
11. R. Dubey, A.Kottantharayil, N. Shiradkar and J. Vasi, “Effect of Mechanical Loading Cycles’ Parameters on Crack Generation and Power Loss on PV Modules,” 48th IEEE Photovoltaic Specialists Conference, Virtual, On-line (2021).

National Salt Satyagraha Memorial at Dandi (2010-2019)
Funded by Ministry of Culture This was an interesting and unique project in which I was involved. It started initially with a solar energy connection. In July 2010, Dr. R. Chidambaram met Shri Gopalkrishna Gandhi (the Mahatma’s grandson) at the IIT Madras convocation. Shri Gandhi had become Chairman of the High Level Dandi Memorial Committee (HLDMC), which was tasked by the Prime Minister to create a suitable memorial to commemorate Gandhiji’s Salt March in 1930, and was desirous of having the memorial powered by solar energy to reflect Gandhiji’s outlook of local self-sufficiency. Knowing that we were setting up NCPRE, Dr. Chidambaram asked Shri Gandhi to contact me. I talked to Director Khakhar, who enthusiastically agreed that we should get involved. Accordingly, I, together with Prof. Chetan Solanki and Prof. Kirti Trivedi went to Dandi in September 2010 to meet Shri Gandhi and other members of the HLDMC. The inclusion of Prof. Trivedi, a Gandhian himself, proved to be prescient, as further developments would show. While IIT Bombay’s original remit was to design the solar PV for the memorial complex, as things went on, I and others from IIT Bombay got more engaged with HLDMC. In 2011, HLDMC requested IIT Bombay to become the “Design Co-ordinating Agency”, with full responsibility of the overall conception and design of the Dandi Memorial. We agreed to this, with Prof. Trivedi playing a major role in conceptualizing the design in the initial period, and Profs. Chakravarthy and Mohanty taking over later. As it became a wider IITB activity, Deans Venkataramani and Viswanadham took on important co-ordination roles, and many faculty members from different areas contributed their expertise pro bono. The solar energy system was designed to make the memorial a ‘net zero energy’ site, and the solar panels were prominently displayed in aesthetic ‘solar trees’. The memorial was inaugurated in January 2019 by the Prime Minister. It provides an excellent example of what IITB can achieve if the faculty work together in an interdisciplinary manner on a national project. One solar-related publication which resulted from this work was:
1. Pratik Mundle, Shashwata Chattopadhyay, Chetan Singh Solanki, Narendra Shiradkar, Anil Kottantharayil, K.L. Narasimhan, Juzer Vasi, and B. K. Chakravarthy, “Effect of Aluminum Back Plate on PV Module Temperature and Performance,”
7th World Conference on Photovoltaic Energy Conversion and 45th IEEE Photovoltaic Specialists Conference, Waikoloa, Hawaii, USA (2018).

Performance, Reliability and Degradation Evaluation for a MW Scale Solar PV Plant (2016-2019)
Funded by NTPC Ltd.
The National Thermal Power Corporation was tasked with playing a major role in India’s utility-scale solar programme. NTPC was new to solar energy, while they had great expertise in power plant planning, design and operation. Their Director (Technical), Mr. A. K. Jha, contacted me, and this resulted in a very meaningful project in which we undertook to study several aspects of performance and reliability of their newly installed solar power plants, including those at Dadri, Rajgarh, and other places. We also conducted training programmes for their engineers. Prof. Anil Kottantharayil was the PI of this project, and others involved included Prof. Narendra Shiradkar and Prof. B. G. Fernandes. One salient aspect of this project was to come up with a detailed tender document which would lay out the technical specifications of the solar panels in a way as to guarantee good quality and reliability, which had been a lacuna in the existing method of tendering which simply relied on the IEC 61215 standard.

Solar Roadmap for ISA Countries (2020-2021)
Funded by IEEE Electron Devices Society
NCPRE had been interacting with the International Solar Alliance (ISA) since soon after its inception in 2015. ISA was launched at COP-21 in Paris in 2015 jointly by Prime Minister Modi and President Hollande, and was focused on ushering in solar energy to solar-rich countries lying between the tropics. I was invited to give a keynote plenary talk at the 7th World Conference on Photovoltaic Energy Conversion / 45th IEEE Photovoltaic Specialists Conference in Hawaii in 2018. This talk, entitled “Global Co-operation in Photovoltaics through the International Solar Alliance,” attracted a lot of interest. As a result, the General Chair of the 2019 IEEE PVSC suggested that we should support several delegates from ISA countries at the conference, and IEEE agreed to this. This was a successful initiative, and the President of IEEE EDS, who was present at the conference asked us to submit a proposal for enhancing IEEE’s globalization efforts in the area of PV. I, together with Sarah Kurtz and Lawrence Kazmerski, submitted a proposal, which was approved. This project had two main goals, to continue support of ISA delegates at the 2020 IEEE PVSC, and to engage with one or two ISA countries to create a solar roadmap for that country. The first goal was successfully met, with 19 ISA delegates from countries like Togo, Bangladesh, Cuba, Guinea, Namibia, etc. participating. We tied up with IEA for the second goal, and a committee of PV experts representing IEEE, IEA and ISA has been holding frequent meetings to prepare a roadmap for Togo. The project envisaged travel to Togo by some members, but that has had to be postponed due to the pandemic.
The conference paper which initiated this activity was:
1. J. Vasi, “Global Co-operation in Photovoltaics through the International Solar Alliance,” (Invited Keynote Plenary Talk), 7th World Conference on Photovoltaic Energy Conversion and 45th IEEE Photovoltaic Specialists Conference, Waikoloa, Hawaii, USA (2018).

Contact Information

Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email : vasi[AT]ee.iitb.ac.in
Phone (Office) : (91 22) - 2576 7401
Office room no: GG-104
Fax: (91 22) - 25723707

Selected Recent Publications

Journal Publications

  1. Y. Golive, S. Zachariah, R. Dubey, S. Chattopadhyay, S. Bhaduri, H.K. Singh, B. Bora, S. Kumar, A.K. Tripathi, A. Kottantharayil, J. Vasi and N. Shiradkar, “Analysis of Field Degradation Rates Observed in All-India Survey of Photovoltaic Module Reliability 2018,” IEEE Journal of Photovoltaics 10, 560 (2020).
  2. S. Chattopadhyay, R. Dubey, S. Bhaduri, S. Zachariah, H. K. Singh, C. S. Solanki, A. Kottantharayil, N. Shiradkar, B. M. Arora, K. L. Narasimhan, and J. Vasi, “Correlating Infra-red Thermography with Electrical Degradation of PV Modules Inspected in All-India Survey of Photovoltaic Module Reliability 2016,” IEEE Journal of Photovoltaics 8, 1800 (2018).
  3. R. Dubey, S. Chattopadhyay, V. Kuthanazhi, A. Kottantharayil, C. S. Solanki, B. M. Arora, K.L. Narasimhan, J. Vasi, B. Bora, Y. K. Singh and O.S. Sastry, “Comprehensive study of performance degradation of field-mounted PV modules in India,” Energy Science and Engineering 5, 51 (2017).
  4. N. R. Mavilla, V. Chavan, C. S. Solanki, and J. Vasi, “Study of temperature-dependent charge conduction in silicon-nanocrystal/SiO2 multilayers,” Thin Solid Films 612, 41 (2016).
  5. S. Chattopadhyay, R. Dubey, V. Kuthanazhi, J. J. John, C. S. Solanki, A. Kottantharayil, B. M. Arora, K.L. Narasimhan, V. Kuber, J. Vasi, A. Kumar, O.S. Sastry, “Visual Degradation in Field-aged Crystalline Silicon PV Modules in India and Correlation with Electrical Degradation,” IEEE Journal of Photovoltaics 4, 1470, (2014).
  6. N. R. Mavilla, C. S. Solanki, and J. Vasi, “Raman spectroscopy of silicon-nanocrystals fabricated by inductively coupled plasma chemical vapor deposition,” Physica E: Low-dimensional Systems and Nanostructures, 52, 59 (2013).
  7. N. R. Mavilla, C. S. Solanki, and J. Vasi, “Optical Bandgap Tunability of Silicon Nanocrystals Fabricated by Inductively Coupled Plasma CVD for Next Generation Photovoltaics,” IEEE Journal of Photovoltaics 3, 1279 (2013).
  8. C. Sandhya, A. B. Oak, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, “Study of P/E cycling endurance induced degradation in SANOS memories under NAND (FN/FN) operation,” IEEE Trans. Electron Devices, 57, 1548 (2010).
  9. V. Hariharan, J. Vasi and V. Ramgopal Rao, “A CAD-Compatible Closed-form Approximation for the Inversion Charge Areal Density in Double-Gate MOSFETs,” Solid State Electronics 53, 218 (2009).
  10. V. Hariharan, J. Vasi and V. Ramgopal Rao, “An Improvement to the Numerical Robustness of the Surface Potential Approximation for Double-Gate MOSFETs,” IEEE Transactions on Electron Devices 56, 529 (2009).
  11. C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, “Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler Nordheim Tunneling Program/Erase Operation,” IEEE Electron. Device Lett. 30, 171 (2009).
  12. V. Hariharan, R. Thakker, Karmvir Singh, A. B. Sachid, M. B. Patil, J. Vasi and V. Ramgopal Rao, “Drain Current Model for Nanoscale Double-Gate MOSFETs”, Solid State Electronics 53, (2009).
  13. C. Sandhya, A. B. Oak, N. Chattar, A. S. Joshi, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, “Impact of SiN composition variation on SANOS memory performance and reliability under NAND (FN/FN) operation,” IEEE Trans. Electron Devices, 56, 3123 (2009).
  14. V. Hariharan, J. Vasi and V. R. Rao, “Drain current model including velocity saturation for symmetric double-gate MOSFETs,” IEEE Transactions on Electron Devices 55, 2173 (2008).

International Conference Papers

  1. P. Ghosh, J. Vasi, A. Kottantharayil, N. Shiradkar, S. Kumar, R. Arya and L. L. Kazmerski, “Scaling Sustainable Integrated PV Manufacturing Globally,” 48th IEEE Photovoltaic Specialists Conference, Virtual, On-line (2021).
  2. R. Dubey, A.Kottantharayil, N. Shiradkar and J. Vasi, “Effect of Mechanical Loading Cycles’ Parameters on Crack Generation and Power Loss on PV Modules,” 48th IEEE Photovoltaic Specialists Conference, Virtual, On-line (2021).
  3. Y. R. Golive, D. Koshta, K. P. Rane, A. Kottantharayil, J. Vasi and A. Kotatntharayil, “Understanding the Origin of unusual I-V curves seen in Field Deployed PV Modules,” 47th IEEE Photovoltaic Specialists Conference, Virtual, On-line (2020).
  4. Y. R. Golive, S. Zachariah, S. Bhaduri, R. Dubey, S. Chattopadhyay, H. K. Singh, A. Kottantharayil, N. Shiradkar, and J. Vasi, “Analysis and Failure Modes of Highly Degraded PV Modules Inspected during the 2018 All India Survey of PV Module Reliability,” 4th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia (2020).
  5. S. Bhaduri, S. Zachariah, G. Yogeswara Rao, S. Chattopadhyay, R. Dubey, C.S. Solanki, A. Kottantharayil, B.M. Arora, K.L. Narasimhan, H.K. Singh, N. Shiradkar and J. Vasi, “Correlating the Hot Spots and Power Degradation seen in crystalline silicon modules in All India Survey of PV Module Reliability 2018,” 46th IEEE Photovoltaic Specialists Conference, Chicago, USA (2019).
  6. Y. Golive, S. Zachariah, R. Dubey, S. Chattopadhyay, S. Bhaduri, H.K. Singh, B. Bora, S. Kumar, A.K. Tripathi, A. Kottantharayil, J. Vasi and N. Shiradkar, “Analysis of Field Degradation Rates Observed in All-India Survey of Photovoltaic Module Reliability 2018,” 46th IEEE Photovoltaic Specialists Conference, Chicago, USA (2019).
  7. S. Zachariah, R. Dubey, Y. R. Golive, S. Bhaduri, S. Chattopadhyay, C. S. Solanki, A. Kottantharayil, B. M. Arora, K. L. Narasimhan, H. K. Singh, J. Vasi and N. Shiradkar, “Electroluminescence Study of over 700 Fielded PV Modules in All India Survey 2018,” 46th IEEE Photovoltaic Specialists Conference, Chicago, USA (2019).
  8. Y. R. Golive, H. K.. Singh, A. Kottantharayil, J. Vasi and N. Shiradkar, “Investigation of Accuracy of various STC Correction Procedures for I-V Characteristics of PV Modules Measured at Different Temperature and Irradiances,” 46th IEEE Photovoltaic Specialists Conference, Chicago, USA (2019).
  9. J. Vasi, “Global Co-operation in Photovoltaics through the International Solar Alliance,” (Invited Keynote Plenary Talk), 7th World Conference on Photovoltaic Energy Conversion and 45th IEEE Photovoltaic Specialists Conference, Waikoloa, Hawaii, USA (2018).
  10. R. Dubey, S. Chattopadhyay, S. Zachariah, S. Rambabu, H. K. Singh, A. Kottantharayil, B. M. Arora, K. L. Narasimhan, N. Shiradkar, and J. Vasi, “On-Site Electroluminescence Study of Field-Aged PV Modules,” 7th World Conference on Photovoltaic Energy Conversion and 45th IEEE Photovoltaic Specialists Conference, Waikoloa, Hawaii, USA (2018).
  11. R. Dubey, S. Chattopadhyay, S. Zachariah, V. Kuthanazhi, S. Rambabu, S. Bhaduri, H.K. Singh, A. Kottantharayil, B. M. Arora, K.L. Narasimhan, N. Shiradkar, B. Bora, O.S. Sastry and J. Vasi, “Investigation of Poor Performing PV Modules Observed in All-India Survey of PV Module Reliability,” 7th World Conference on Photovoltaic Energy Conversion and 45th IEEE Photovoltaic Specialists Conference, Waikoloa, Hawaii, USA (2018).
  12. Pratik Mundle, Shashwata Chattopadhyay, Chetan Singh Solanki, Narendra Shiradkar, Anil Kottantharayil, K.L. Narasimhan, Juzer Vasi, and B. K. Chakravarthy, “Effect of Aluminum Back Plate on PV Module Temperature and Performance,” 7th World Conference on Photovoltaic Energy Conversion and 45th IEEE Photovoltaic Specialists Conference, Waikoloa, Hawaii, USA (2018).
  13. David Ginley, William Tumas, Marisa Howe, Pradip Dutta, Clifford Ho, Juzer Vasi, Maikel Van Hest, Aimee Curtright, Parveen Kumar, and Kamanio Chattopadhyay, “Solar Energy Research Institute for India and the US (SERIIUS): A Focused Solar Consortium,” 7th World Conference on Photovoltaic Energy Conversion and 45th IEEE Photovoltaic Specialists Conference, Waikoloa, Hawaii, USA (2018).
  14. Hemant K. Singh, R. Dubey, S. Zachariah, K. L. Narasimhan, B. M. Arora, A. Kottantharayil, and J. Vasi, “Modified STC Correction Procedure for Assessing PV Module Degradation in Field Surveys,” 44th IEEE Photovoltaic Specialists Conference, Washington DC, USA (2017).
  15. R. Dubey, S. Zachariah, S. Chattopadhyay, V. Kuthanazhi, S. Rambabu, S. Bhaduri, H. K. Singh, A. Sinha, C. S. Solanki, A. Kottantharayil, B. M. Arora, K. L. Narasimhan, J. Vasi, B. Bora, R. Kumar, and O. S. Sastry, “Performance of Field-Aged PV Modules in India: Results from 2016 All India Survey of PV Module Reliability,” 44th IEEE Photovoltaic Specialists Conference, Washington DC, USA (2017).
  16. S. Chattopadhyay, C. S. Solanki, A. Kottantharayil, K.L. Narasimhan, J. Vasi, S. Tatapudi, and G. TamizhMani, “Quantification of PV Module Discoloration using Visual Image Analysis,” 44th IEEE Photovoltaic Specialists Conference, Washington DC, USA (2017).
  17. S. Chattopadhyay, R. Dubey, V. Kuthanazhi, J. J. John, J. Vasi, A. Kottantharayil, B. M. Arora, K. L. Narsimhan, C. S. Solanki, B. Bora, Y. K. Singh and O.S. Sastry, “Effect of Hot Cells on Electrical Degradation of PV Modules,” Photovoltaic Reliability Workshop, Lakewood, CO, USA (2016).
  18. Rajiv Dubey, Shashwata Chattopadhyay, Vivek Kuthanazhi, Jim Joseph John, Chetan Singh Solanki, Anil Kottantharayil, Brij M. Arora, K.L. Narasimhan, Juzer Vasi, Birinchi Bora, Yogesh Kumar Singh and O.S. Sastry, “Correlation of Electrical and Visual Degradation seen in Field Survey in India,” 43rd IEEE Photovoltaic Specialists Conference, Portland, USA (2016).
  19. Vivek Kuthanazhi, Santhosh Jois, Prachi Jadhav, Kamlesh Kumar, Akhilesh Magal, Ameya Pimpalkhare, Juzer Vasi, Anil Kottantharayil, Krithi Ramamritham, N.C. Narayanan, Vinit Kotak, and R. Dubey, “Estimating Mumbai’s Rooftop PV Potential through Mobilization of IEEE Student Community,” 43rd IEEE Photovoltaic Specialists Conference, Portland, USA (2016).
  20. G. Tamizhmani, S. Tatapudi, R. Dubey, S. Chattopadhyay, C. Solanki, J. Vasi, B. Bora, O. S. Sastry and A. Kottantharayil, “Comparative Study of Performance of Fielded PV Modules in Two Countries,” 26th International Photovoltaic Science and Engineering Conference, Singapore (2016).
  21. R. Dubey, P. Batra, S. Chattopadhyay, A. Kottantharayil, B. M. Arora, K. L. Narasimhan, and J. Vasi, “Measurement of temperature coefficient of Photovoltaic Modules in field and comparison with laboratory measurements” 42nd IEEE Photovoltaic Specialists Conference, New Orleans, USA (2015).
  22. Rajiv Dubey, Shashwata Chattopadhyay, Vivek Kuthanazhi, Jim Joseph John, Juzer Vasi, Anil Kottantharayil, Brij M Arora, K.L. Narsimhan, Chetan S. Solanki, Arun Kumar, O.S. Sastry, “Performance Degradation in Field-aged Crystalline Silicon PV Modules in Different Indian Climatic Conditions,” 40th IEEE Photovoltaic Specialists Conference, Denver, USA (2014).
  23. Shashwata Chattopadhyay, Rajiv Dubey, Vivek Kuthanazhi, Jim Joseph John, Chetan Singh Solanki, Anil Kottantharayil, Brij M. Arora, K.L. Narasimhan, Juzer Vasi, Arun Kumar, O.S. Sastry, “Visual Degradation in Field-aged Crystalline Silicon PV Modules in India and Correlation with Electrical Degradation,” 40th IEEE Photovoltaic Specialists Conference, Denver, USA (2014).
  24. R. Dubey, S. Chattopadhyay, J.J. John, B.M. Arora, A. Kottantharayil, C. S. Solanki, K. L. Narasimhan, and J. Vasi, “Daylight Electroluminescence Imaging by Image Difference Technique,” 6th World Conference on Photovoltaic Energy Conversion and 41st IEEE Photovoltaic Specialists Conference, Kyoto, Japan (2014).
  25. Narasimha Rao Mavilla, C. S. Solanki, and J. Vasi, “Structural, optical and electrical properties of Si nanocrystals fabricated by ICPCVD for next generation photovoltaics,” 39th IEEE Photovoltaic Specialists Conference, Tampa, USA (2013).
  26. J. Vasi, “Research programmes for photovoltaics in SERIIUS” (Plenary Talk), Intersolar India 2013, Mumbai, India (2013).
  27. C. S. Solanki, B. G. Fernandes, B. M. Arora, P. Sharma, V. Agarwal, M. B. Patil, J. Vasi, D. B. Phatak, Mukta Atrey, K. Moudgalya and K. Bijlani, “Teach a 1000 Teachers: A methodology for the rapid ramp-up of photovoltaics manpower required for India’s National Solar Mission”, 38th IEEE Photovoltaic Specialists Conference, Austin, USA (2012).
  28. Narasimha Rao Mavilla, Hemant Kumar Singh, C. S. Solanki, and J. Vasi, “Structural properties of ICPCVD fabricated SiO2/SiOx superlattice for use in beyond Shockley-Queisser-limit solar cells,” 27th European Photovoltaic Solar Energy Conference (EUPVSEC), Frankfurt, Germany (2012).
  29. V. Mishra, G. K. Ananthasuresh, N. Bhat, H. S. Jamadagni, S. Mohan, T. Murthy, R. Pratap, S. A. Shivashankar, V. Venkataraman, K. J. Vinoy, K. Nageswari, A. Q. Contractor, A. Kottantharayil, R. Pinto, V. R. Rao, and J. Vasi, “Indian Nanoelectronics Users Program: An outreach vehicle to expedite nanoelectronics research in India,” 18th Biennial University/Government/Industry Micro/Nano Symposium (UGIM), W.Lafayette, USA (2010).
  30. J. Vasi, “Research and education in support of the JNNSM” (Plenary Talk), Intersolar India 2010, Mumbai, India (2010).
  31. Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, C. Olsen, S. M. Seutter, R. Hung, G. Conti, K. Ahmed, N. Krishna, J. Vasi and S. Mahapatra, “Nitride Engineering and the effect of interfaces on charge trap flash performance and reliability,” International Reliability Physics Symposium (IRPS) (2008).
  32. A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, “Development of a 3D simulator for metal nanocrystal flash memories under NAND operation,” International Electron Devices Meeting (IEDM) (2007).
faculty/vasi.txt · Last modified: 2021/06/14 19:00 by vasi