Other railway projects pursued at IIT Bombay

Many railway timetabling, capacity-utilization and simulation related projects pursued at IIT Bombay have been listed here. This page contains information about other such projects.

Multiple Line Rail Sections: Tiruvallur-Arakkonam case-study

In this work, a simulation-based approach is used to evaluate and determine a strategy for the effective use of third line in a 3-line railway section. The mixed rail-traffic simulator developed at IIT Bombay has been used to experiment with different scheduling strategies. The simulator provides a detailed picture of the running of multiple trains on a rail section, considering timetables of fixed schedule trains, dynamic assignment of paths of unscheduled trains, detailed infrastructure modelling (stations, signals and block sections) and detailed train running characteristics. We describe a typical railway section consisting of two unidirectional lines and one bidirectional line (also called as the third line). Based on the simulation, threshold policies as to how to use the third line effectively, were obtained in this project. More details can be found in the ISCI 2012 paper.

System Headway Study for Suburban Services (Western Railways, Mumbai)

The section capacity of a rail section and the reliability of a planned timetable on the section depends upon the achievable section headway. Section headway in turn depends upon signal locations, signal aspects, train characteristics, platform allocation and turnaround times. Using a combination of analytical and simulation tools, a detailed analysis of section performance along the Churchgate-Borivali slow corridor of Western Railways is pursued in this work. One of the main outcomes was the evaluation of the impact of signal spacing on the automatic signaling section. More details can be found in the Technical-Report.

Contact persons

Prof. Narayan Rangaraj,
Industrial Engineering and Operations Research (IEOR),
IIT Bombay, Powai, Mumbai 400 076
narayan.rangaraj[AT]iitb.ac.in

and/or:

Prof. Madhu N. Belur,
Department of Electrical Engineering,
IIT Bombay, Powai, Mumbai 400 076
belur[AT]iitb.ac.in

Last modified: 1st March 2019