{"id":2056,"date":"2023-01-26T20:28:30","date_gmt":"2023-01-26T20:28:30","guid":{"rendered":"http:\/\/www.ee.iitb.ac.in\/~cadsl\/?page_id=2056"},"modified":"2023-03-10T22:35:46","modified_gmt":"2023-03-10T17:05:46","slug":"publications","status":"publish","type":"page","link":"https:\/\/www.ee.iitb.ac.in\/~cadsl\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"2056\" class=\"elementor elementor-2056\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-6774e45 elementor-section-boxed elementor-section-height-default elementor-section-height-default elementor-invisible\" data-id=\"6774e45\" data-element_type=\"section\" data-settings=\"{&quot;animation&quot;:&quot;fadeIn&quot;}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-20c3ee1\" data-id=\"20c3ee1\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-aa193e0 elementor-widget elementor-widget-heading\" data-id=\"aa193e0\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.10.1 - 17-01-2023 *\/\n.elementor-heading-title{padding:0;margin:0;line-height:1}.elementor-widget-heading .elementor-heading-title[class*=elementor-size-]>a{color:inherit;font-size:inherit;line-height:inherit}.elementor-widget-heading .elementor-heading-title.elementor-size-small{font-size:15px}.elementor-widget-heading .elementor-heading-title.elementor-size-medium{font-size:19px}.elementor-widget-heading .elementor-heading-title.elementor-size-large{font-size:29px}.elementor-widget-heading .elementor-heading-title.elementor-size-xl{font-size:39px}.elementor-widget-heading .elementor-heading-title.elementor-size-xxl{font-size:59px}<\/style><h2 class=\"elementor-heading-title elementor-size-default\">Publications<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-460970c elementor-section-boxed elementor-section-height-default elementor-section-height-default elementor-invisible\" data-id=\"460970c\" data-element_type=\"section\" data-settings=\"{&quot;animation&quot;:&quot;fadeIn&quot;}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-no\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-bc42c60\" data-id=\"bc42c60\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-cf4300a elementor-widget elementor-widget-heading\" data-id=\"cf4300a\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h5 class=\"elementor-heading-title elementor-size-default\">Journal \/ Conference \/ Workshop<\/h5>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-c96d52b elementor-widget elementor-widget-menu-anchor\" data-id=\"c96d52b\" data-element_type=\"widget\" data-widget_type=\"menu-anchor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.10.1 - 17-01-2023 *\/\nbody.elementor-page .elementor-widget-menu-anchor{margin-bottom:0}<\/style>\t\t<div id=\"2019\" class=\"elementor-menu-anchor\"><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-efb0cc8 elementor-widget elementor-widget-heading\" data-id=\"efb0cc8\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2021<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-46709b2 elementor-widget elementor-widget-text-editor\" data-id=\"46709b2\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.10.1 - 17-01-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<ul>\n \t<li>Jaynarayan Tudu, Satyadev Ahlawat, Sonali Shukla, and Virendra Singh, `<em>A framework for configurable for joint-scan design-for-test architecture<\/em>`, Journal of Electronic Testing: Theory and Application (<b>JETTA<\/b>), 2021<\/li>\n \t<li>Abhinish Anand, Winnie Thomas, Suryakant Toraskar, and Virendra Singh, `<em>Predictive warp scheduling for efficient execution in GPGPU<\/em>`, 31<sup>st<\/sup> ACM Great Lake Symposium on VLSI (<b>GLSVLSI`21<\/b>), June 2021.<\/li>\n \t<li>Winnie Thomas, Suryakant Toraskar, and Virendra Singh, `<em>Dynamic optimization in GPU using Roofline model<\/em>`, Proc. of International Symposium on Circuits and Systems (<b>ISCAS`21<\/b>), Daegu, Korea, May 2021<\/li>\n \t<li>Vineesh VS, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, and Virendra Singh, `<em>Enhanced design debugging with assistance from guidance based model checking<\/em>`, IEEE Transaction on Computer Aided Design (<b>TCAD<\/b>), Vol. 14, No. 5, May 2021<\/li>\n \t<li>Arindam Sarkar, Newton, Varun Venkitaraman, and Virendra Singh, `<em>DAM: Deadlock aware migration techniques for STT-RAM based hybrid caches<\/em>`, IEEE Computer Architecture Letters (<b>CAL<\/b>), Vol 20, No. 1, Jan 2021<\/li>\n \t<li>Nirmal Kumar Boran, Shubhankit Rathore, Meet Udeshi, and Virendra Singh, `<em>Fine-grained Scheduling in Heterogeneous-ISA Architectures<\/em>`, IEEE Computer Architecture Letters (<b>CAL<\/b>), Vol. 20, No.1, Jan 2021<\/li>\n \t<li>Harsh Bhargav, Vineesh VS, Binod Kumar and Virendra Singh, `<em>Enhancing testbench quality via genetic algorithm<\/em>`, Proc. of Mid-West Symposium on Circuits and Systems (<b>MWSCAS<\/b>) 2021<\/li>\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-fa4118d elementor-widget elementor-widget-heading\" data-id=\"fa4118d\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2020<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-9c9c1d8 elementor-widget elementor-widget-text-editor\" data-id=\"9c9c1d8\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul>\n<li> Newton, Virendra Singh, and Trevor E. Carlson, `<em>PIM-GraphSCC: PIM-based Graph Processing using Graph&#8217;s Community Structures<\/em>`, IEEE Computer Architecture Letters (<b>CAL<\/b>), 2020 <\/li>\n\n<li>   Vinod Guna, Vineesh V.S, Jaynarayan Tudu, Masahiro Fujita, and Virendra Singh, `<em>LUT-based circuit approximation with targeted error guarantees<\/em>`, 29<sup>th<\/sup> IEEE Asian Test Symposium (<b>ATS20<\/b>), Penang, Malaysia, Nov 2020 <\/li>\n\n<li> Binod Kumar, Jay Adhaduk, Kanad Basu, Masahiro Fujita, and Virendra Singh, `<em>A methodology to capture fine grained internal visibility during multi-session silicon debug<\/em>`, IEEE Transaction on Very Large Scale Integrated Systems (<b>TVLSI<\/b>), vol. 28, No. 4, April 2020 <\/li>\n\n<li> Antara Ganguly, Shankar Balachandran, Anant Nori, Virendra Singh and Sreenivas Subramoney, `<em>Characterization of data generating neural network workloads on x86 server architecture<\/em>`, Workshop on Benchmarking Machine Learning Loads (<b>MLBench20<\/b>), Boston, Massachusetts, USA, April 2020.<\/li>\n\n<li> Antara Ganguly, Shankar Balachandran, Anant Nori, Virendra Singh and Sreenivas Subramoney, `<em>Characterization of data generating neural network application on x86 server architecture<\/em>`, IEEE International Symposium on Performance Analysis of Systems and Software (<b>ISPASS<\/b>), Boston, Massachusetts, USA, April 2020.<\/li>\n\n<li> Jiji Angel and Virendra Singh, `<em>On the DSA key recovery attack with variable partial nonces known<\/em>`, 3<sup>rd<\/sup> ISEA International Conference on Security and Privacy (<b>ISEA-ISAP<\/b>), Guwahati, India, Feb 2020.<\/li>\n\n<li> Binod Kumar, Swapaniel Thakur, Kanad Basu, Masahiro Fujita, and Virendra Singh, `<em>A low overhead methodology for validating memory consistency models in chip multiprocessors<\/em>`, 33<sup>rd<\/sup> International Conference on VLSI Design (<b>VLSID-20<\/b>), Bangalore, India, Jan 2020.<\/li>\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-05a220b elementor-widget elementor-widget-heading\" data-id=\"05a220b\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2019<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-60241e2 elementor-widget elementor-widget-text-editor\" data-id=\"60241e2\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul>\n \t<li>Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita and Virendra Singh, &#8220;<em>A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors<\/em>&#8220;, 33<sup>rd<\/sup> International Conference on VLSI Design 2020, January 4-8, 2020<\/li>\n \t<li>Binod Kumar, Akshay Kumar Jaiswal, Vineesh V S and Rushikesh Shinde, &#8220;<em>Analyzing Hardware Security Properties of Processors through Model Checking<\/em>&#8220;,\n33<sup>rd<\/sup> International Conference on VLSI Design 2020, January 4-8, 2020<\/li>\n \t<li>Raj Kumar Choudhary, Newton Singh, Harideep Nair, Rishabh Rawat and Virendra Singh, &#8220;<em>Freeflow Core: Enhancing Performance of In-order Cores with Energy Efficiency<\/em>&#8220;, 37<sup>th<\/sup> IEEE International Conference on Computer Design (<b>ICCD<\/b>) , Abu Dhabi, UAE, Nov 17-20, 2019<\/li>\n \t<li>Varun Venkitaraman, Ashok Sathyan and Virendra Singh, &#8220;<em>CBIT &#8211; A Synonym Handler for Low-latency and Energy-efficient Cache Hierarchy<\/em>&#8220;, 37<sup>th<\/sup> IEEE International Conference on Computer Design (<b>ICCD<\/b>) , Abu Dhabi, UAE, Nov 17-20, 2019<\/li>\n \t<li>Ayush Agrawal and Virendra Singh, &#8220;<em>O-Factor: Opportunistic Out of Order Scheduling for GP-GPUs<\/em>&#8220;, 37<sup>th<\/sup> IEEE International Conference on Computer Design (<b>ICCD<\/b>) , Abu Dhabi, UAE, Nov 17-20, 2019<\/li>\n \t<li>Binod Kumar, Masahiro Fujita, and Virendra Singh, &#8220;<em>SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement<\/em>&#8220;, Journal of Electronic Testing: Theory and Application (<b>JETTA<\/b>), Oct 2019.<\/li>\n \t<li>Antara Ganguly, Shankar Balachandran, Anant Nori, Virendra Singh and Sreenivas Subramoney, &#8220;<em>Characterization of Data Movement Issues in Generation-based Neural Network Applications on x86 CPU Architecture<\/em>, International Symposium on Memory Systems (<b>MEMSYS<\/b>) 2019, Washington DC, USA, October 2019<\/li>\n \t<li>Antara Ganguly, Rajiv Muralidhar, Virendra Singh and Masahiro Fujita, &#8220;<em>Towards Energy-efficient Architectures for Deep Learning<\/em>&#8220;, European Conference on Machine Learning (<b>ECML-PKDD<\/b>) &#8211; Green Data Mining Workshop, Wurzburg, Germany, September 2019<\/li>\n \t<li>Binod Kumar, Atul Kumar Bhosale, Masahiro Fujita and Virendra Singh, &#8220;<em>Validating Multi-processor Cache Coherence Mechanisms Under Diminished Observability<\/em>&#8221; 28<sup>th<\/sup> IEEE Asian Test Symposium(<b>ATS<\/b>) 2019, Kolkata, India, December 10-13, 2019<\/li>\n \t<li>Vineesh V S, Binod Kumar, Rushikesh Shinde, Akshay Kumar Jaiswal, Harsh Bhargava and Virendra Singh, &#8220;<em>Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification<\/em>&#8221; 28<sup>th<\/sup> IEEE Asian Test Symposium(<b>ATS<\/b>) 2019, Kolkata, India, December 10-13, 2019<\/li>\n \t<li>Satyadev Ahlawat, Jaynarayan Tudu, Masahiro Fujita, and Virendra Singh, &#8220;<em>Securing Scan Architecture through Test Response Encryption<\/em>&#8221; 32<sup>nd<\/sup> IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (<b>DFT<\/b>) 2019, ESA-ESTEC &amp; TU Delft, Netherlands, October 02-04, 2019<\/li>\n \t<li>Nirmal Kumar Boran, Dinesh Kumar Yadav and Rishabh Iyer, &#8220;<em>Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA multi-core Architectures<\/em>&#8221; 25<sup>th<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2019, Indore, India, July 1-3, 2019<\/li>\n \t<li>Vineesh V. S., Jay Adhaduk and Binod Kumar, &#8220;<em>Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods<\/em>&#8220;, 25<sup>th<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2019, Indore, India, July 1-3, 2019<\/li>\n \t<li>Saurabh Gangurde and Binod Kumar, &#8220;<em>A unified methodology for hardware obfuscation and IP watermarking<\/em>&#8220;, 25<sup>th<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2019, Indore, India, July 1-3, 2019<\/li>\n \t<li>Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan Tudu, Masahiro Fujita, and Virendra Singh, &#8220;<em>Securing Scan through Plain-text Restriction<\/em>&#8220;, 25<sup>th<\/sup> IEEE International Symposium on On-Line Testing and Robust System Design (<b>IOLTS<\/b>), 2019, Rhode Island, Greece, July 1-3, 2019<\/li>\n \t<li>Antara Ganguly, Rajeev Muralidhar, and Virendra Singh, &#8220;<em>Towards Energy Efficient non-von Neumann Architectures for Deep Learning<\/em>&#8220;, 20<sup>th<\/sup> International Symposium on Quality Electronic Design (<b>ISQED<\/b>), 2019, Santa Clara, CA, USA, March 6-7, 2019, pp. 335-342<\/li>\n \t<li>Binod Kumar, Kanad Basu, Masahiro Fujita, and Virendra Singh, &#8220;<em>Post-silicon gate-level error localisation with effective &amp; combined trace signal selection<\/em>&#8220;, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (<b>TCAD<\/b>), Vol. xx, No. xx, 2019 (In press)<\/li>\n \t<li>Binod Kumar, Masahiro Fujita and Virendra Singh, &#8220;<em>A Methodology for SAT-based Electrical Error Debugging during Post-silicon Validation<\/em>&#8220;, 32<sup>nd<\/sup> International Conference on VLSI Design (<b>VLSID<\/b>) 2019, Delhi, India, Jan 2019<\/li>\n \t<li>Jaidev Shenoy, Virendra Singh, Kelly Ockunzzi and Kushal Kamal, &#8220;<em>On-chip MISR compaction technique to reduce diagnostic effort and test time<\/em>&#8220;, 32<sup>nd<\/sup> International Conference on VLSI Design (<b>VLSID<\/b>) 2019, Delhi, India, Jan 2010<\/li>\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-e351c88 elementor-widget elementor-widget-menu-anchor\" data-id=\"e351c88\" data-element_type=\"widget\" data-widget_type=\"menu-anchor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div id=\"2018\" class=\"elementor-menu-anchor\"><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-5f8d0cf elementor-widget elementor-widget-heading\" data-id=\"5f8d0cf\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2018<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-0ae0be1 elementor-widget elementor-widget-text-editor\" data-id=\"0ae0be1\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul>\n \t<li>\nAntara Ganguly, Virendra Singh, Rajiv Muralidhar, and Masahiro Fujita, &#8220;<em>Memory system requirements for convolutional neural networks<\/em>&#8220;, International Symposium on Memory Systems (<b>MEMSYS<\/b>) 2018, Washington DC, USA, October 2018 <\/li>\n\n<li>\nSatyadev Ahlawat, Darshit Vaghani, Naveen Bazard, and Virendra Singh, &#8220;<em>Using MISR as countermeasure against scan based side channel attacks<\/em>&#8220;, 16<sup>th<\/sup> IEEE International East-West Design and Test Symposium (<b>EWDTS<\/b>) 2018, Kazan, Russia, September 2018 <\/li>\n\n<li>\nSatyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, and Virendra Singh, &#8220;<em>A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test<\/em>&#8220;,  IEEE Transactions on Device and Materials Reliability (<b>TDMR<\/b>), Vol. 18, No. 2, pp. 321-331, June 2018 <\/li>\n\n\n<li>\nAnkit Jindal, Binod Kumar, Masahiro Fujita, and Virendra Singh, &#8220;<em>Silicon debug with maximally expanded internal observability using nearest neighbour algorithm<\/em>&#8220;, IEEE Computer Society Annual Symposium on VLSI (<b>ISVLSI<\/b>) 2018, Hongkong, SAR, China, July 2018 <\/li>\n\n<li>\nSuhit Pai, Newton, and Virendra Singh, &#8220;<em>AB-Aware: Application Behavior Aware Management of Shared Last Level Caches<\/em>&#8220;, 28<sup>th<\/sup> ACM Great Lakes Symposium on VLSI (<b>GLSVLSI<\/b>) 2018, Chicago, Illinois, USA, May 23-25, 2018 <\/li>\n\n<li>\nDarshit Vaghani, Satyadev Ahlawat, Jaynarayan Tudu, Masahiro Fujita, and Virendra Singh, &#8220;<em>On Securing Scan Design Through Test Vector Encryption<\/em>&#8220;, 51<sup>st<\/sup> IEEE International Symposium on Circuits and Systems (<b>ISCAS<\/b>) 2018, Florence, Italy, May 2018 <\/li>\n\n<li>\nNihar Hage, Satyadev Ahlawat, and Virendra Singh, &#8220;<em>In-situ Monitoring for Slack Time Violation Without Performance Penalty<\/em>&#8220;, 51<sup>st<\/sup> IEEE International Symposium on Circuits and Systems (<b>ISCAS<\/b>) 2018, Florence, Italy, May 2018 <\/li>\n\n<li>\nRohini Gulve and Virendra Singh, &#8220;<em>ATPG Power Guards: On Limiting the Test Power below Threshold<\/em>&#8220;, Proc. of Design Automation and Test in Europe (<b>DATE<\/b>), Dresden, Germany, March 2018\n<\/li>\n\n<li>\nToral Shah, Anzhela Matrosova, Masahiro Fujita, and Virendra Singh, &#8220;<em>Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design<\/em>&#8220;, Journal of Electronic Testing: Theory and Applications (<b>JETTA<\/b>), Vol. 34, No. 1, February 2018\n<\/li>\n\n<li>\nAnkit Jindal, Binod Kumar, Kanad Basu, and Masahiro Fujita, &#8220;<em>ELURA: A Methodology for Post-silicon Gate-level Error Localization using Regression Analysis<\/em>&#8220;, 31<sup>st<\/sup> International Conference on VLSI Design (<b>VLSID<\/b>), Pune, India, Jan 2018\n<\/li>\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-a7a6db8 elementor-widget elementor-widget-menu-anchor\" data-id=\"a7a6db8\" data-element_type=\"widget\" data-widget_type=\"menu-anchor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div id=\"2017\" class=\"elementor-menu-anchor\"><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-9922d05 elementor-widget elementor-widget-heading\" data-id=\"9922d05\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2017<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-29456be elementor-widget elementor-widget-text-editor\" data-id=\"29456be\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul>\n \t<li>\nAnkush Srivastava, Virendra Singh, Adit Singh, and Kewal Saluja, &#8220;<em>A reliability aware methodology to isolate timing critical paths under aging<\/em>&#8220;, Journal of Electronic Testing: Theory and Application (<b>JETTA<\/b>), Vol. 33, No. 6, December 2017\n<\/li>\n\n<li>\nNewton, Sujit Mahto, Suhit Pai, and Virendra Singh, &#8220;<em>DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching<\/em>&#8220;, 35<sup>th<\/sup> International Conference on Computer Design (<b>ICCD<\/b>), Boston Marriot Newton, Boston, MA, USA, November 2017\n<\/li>\n\n<li>\nSatyadev Ahlawat, Darshit Vaghani, Jaynarayan Tudu, and Virendra Singh, &#8220;<em>On Securing Scan Design from Scan-Based Side-Channel Attacks<em>&#8220;, 26<sup>th<\/sup> IEEE Asian Test Symposium (<b>ATS<\/b>) Taipei, Taiwan, Nov 2017\n<\/li>\n\n<li> Ankush Srivastava, Adit Singh, Virendra Singh, and Kewal K. Saluja, &#8220;<em>Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects<\/em>&#8220;, 48<sup>th<\/sup> IEEE International Test Conference (<b>ITC<\/b>) 2017, Fort Worth, Texas, USA, Nov 2017 <\/li>\n\n<li>\nBinod Kumar, Kanad Basu, Masahiro Fujita and Virendra Singh, &#8220;<em>RTL Level Trace Signal Selection and Coverage Estimation During Post-Silicon Validation<\/em>&#8220;, 19<sup>th<\/sup> IEEE International High Level Design Validation and Test Workshop (<b>HLDVT<\/b>) 2017, Santa Cruz, CA, USA, October 2017\n<\/li>\n\n<li>\nSatyadev Ahlawat, Darshit Vaghani, and Virendra Singh, &#8220;<em>Preventing Scan-Based Side-Channel Attacks Through Key Masking<\/em>&#8220;, 30<sup>th<\/sup> IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (<b>DFT<\/b>) 2017, Cambridge, UK, October 2017<\/li>\n\n<li>\nShoba Gopalkrishnan and Virendra Singh, &#8220;<em>REMORA: A Hybrid Low-Cost Soft-Error Reliable Fault Tolerant Architecture<\/em> 30<sup>th<\/sup> IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (<b>DFT<\/b>) 2017, Cambridge, UK, October 2017<\/li>\n\n<li>\nBinod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, and Virendra Singh, &#8220;<em>Improving post-silicon error detection with topological selection of trace signals<\/em>&#8220;, 25<sup>th<\/sup> IEEE\/IFIP International Conference on on Very Large Scale Integratiion (<b>VLSI-SoC<\/b>) 2017, Abu Dhabi, UAE, October 2017<\/li>\n\n<li>\nRohini Gulve, Anshu Goel, and Virendra Singh, &#8220;<em>PHP: Power hungry pattern generation at higher abstraction level<\/em>&#8220;, 15<sup>th<\/sup> IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>), Novi Sad, Serbia, Sep 2017\n<\/li>\n\n<li>\nVineesh VS, Nihar Hage, Kartik B, and Virendra Singh, &#8220;<em>On achieving full functional coverage for forwarding units of pipelined processors<\/em>&#8220;, 15<sup>th<\/sup> IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>), Novi Sad, Serbia, Sep 2017\n<\/li>\n\n<li>\nSatyadev Ahlawat, Darshit Vaghani, Jaynarayan Tudu, and Ashok Suhag, &#8220;<em>A Cost Effective Technique for Diagnosis of Scan Chain Faults<\/em>&#8220;, 21<sup>st<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2017, Roorkee, India, July 2017<\/li>\n\n<li>\nSujit Kr. Mahto and Newton Singh, &#8220;<em>ACAM: Application Aware Adaptive Cache Management for Shared LLC<\/em>&#8220;, 21<sup>st<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2017, Roorkee, India, July 2017<\/li>\n\n<li>\nAnshu Goel and Rohini Gulve, &#8220;<em>Multi-mode Toggle Random Access Scan to Minimize Test Application Time<\/em>&#8220;, 21<sup>st<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2017, Roorkee, India, July 2017<\/li>\n\n<li>\nRohini Gulve and Nihar Hage, &#8220;<em>On Generation of Delay Test with Capture Power Safety<\/em>&#8220;, 21<sup>st<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2017, Roorkee, India, July 2017<\/li>\n\n<li>\nBinod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey and Masahiro Fujita, &#8220;<em>A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection<\/em>&#8220;, 21<sup>st<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2017, Roorkee, India, July 2017<\/li>\n\n<li>\nToral Shah and Virendra Singh, &#8216;<em>Test Pattern Generation to Detect Multiple Faults in ROBDD based Combinational Circuits<\/em>&#8216;, 23<sup>rd<\/sup> IEEE International Symposium on On-Line Testing and Robust System Design (<b>IOLTS<\/b>) 2017, Thessaloniki, Greece, July 2017<\/li>\n\n<li>\nNihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh, &#8216;<em>Instruction-Based Self-Test for Delay Faults Maximizing Operating Temperature<\/em>&#8216;, 23<sup>rd<\/sup> IEEE International Symposium on On-Line Testing and Robust System Design (<b>IOLTS<\/b>) 2017, Thessaloniki, Greece, July 2017<\/li>\n\n<li>\nBinod Kumar, Ankit Jindal, Jaynarayan Tudu, Brajesh Pandey, Virendra Singh, &#8216;<em>Revisiting Random Access Scan for Effective Enhancement of Post-silicon Observability<\/em>&#8216;, 23<sup>rd<\/sup> IEEE International Symposium on On-Line Testing and Robust System Design (<b>IOLTS<\/b>) 2017, Thessaloniki, Greece, July 2017<\/li>\n\n<li>\nSatyadev Ahlawat, Darshit Vaghani, Rohini Gulve, and Virendra Singh, &#8216;<em>A Low Cost Technique for Scan Chain Diagnosis<\/em>`, 50<sup>th<\/sup> IEEE International Symposium on Circuits &#038; Systems (<b>ISCAS<\/b>) 2017, Baltimore, MD, USA, May 2017<\/li>\n\n<li>\nAbhishek Rajgadia, Newton Singh, and Virendra Singh, &#8216;<em>EEAL: Processors&#8217; Performance Enhancement Through Early Execution of Aliased Loads<\/em>`, 27<sup>th<\/sup> ACM Great Lakes Symposium on VLSI (<b>GLSVLSI<\/b>) 2017, Alberta, Canada, May 2017<\/li>\n\n<li> \nBinod Kumar, Ankit Jindal, Masahiro Fujita, and Virendra Singh, &#8216;<em>Combining Restorability and Error Detection Ability for Effective Trace Signal Selection<\/em>` 27<sup>th<\/sup> ACM Great Lakes Symposium on VLSI (<b>GLSVLSI<\/b>) 2017, Alberta, Canada, May 2017<\/li>\n\n<li>\nSatyadev Ahlawat, Darshit Vaghani, Virendra Singh, &#8216;<em>An Efficient Test Technique to Prevent Scan-Based Side-Channel Attacks<em>`, 22<sup>nd<\/sup> IEEE European Test Symposium (<b>ETS<\/b>) 2017, Limassol, Cyprus, May 2017<\/li>\n\n<li>\nToral Shah, Anzhela Matrosova, Binod Kumar, Masahiro Fujita and Virendra Singh,`<em>Testing Multiple Stuck-at Faults of ROBDD Based Combinational Circuit Design<\/em>`, 18<sup>th<\/sup> IEEE Latin American Test Symposium (<b>LATS<\/b>) 2017, Bogota, Colombia, March 2017<\/li>\n\n<li>\nBinod Kumar, Ankit Jindal, Masahiro Fujita and Virendra Singh, `<em>Post-silicon Observability Enhancement with Topology Based Trace Signal Selection<\/em>`, 18<sup>th<\/sup> IEEE Latin American Test Symposium (<b>LATS<\/b>) 2017, Bogota, Colombia, March 2017<\/li>\n<li>\nAnkush Srivastava, Virendra Singh, Adit Singh and Kewal Saluja, `<em>Identifying High Variability Speed-Limiting Paths under Aging<\/em>`, 18<sup>th<\/sup> IEEE Latin American Test Symposium (<b>LATS<\/b>) 2017, Bogota, Colombia, March 2017<\/li> \n\n<li> \nNihar Hage, Rohini Gulve, Masahiro Fujita, and Virendra Singh, `<em>On testing of superscalar processors in functional mode for delay faults<\/em>`, 30<sup>th<\/sup> International conference on VLSI Design (<b>VLSID<\/b>) 2017, Hyderabad, Jan 2017<\/li>\n\n<li>\nBinod Kumar, Ankit Jindal, Virendra Singh, and Masahiro Fujita, `<em>A methodology for trace signal selection to improve error detection in post silicon validation<\/em>`, 30<sup>th<\/sup> International conference on VLSI Design (<b>VLSID<\/b>) 2017, Hyderabad, Jan 2017<\/li>\n\n<li> \nBinod Kumar and Brajesh Pandey, `<em>On Leveraging formal methods to enhance trace mechanisms for efficient post-silicon debug<\/em>`, 8<sup>th<\/sup> IEEE International Workshop on Reliability Aware System Design and Test (<b>RASDAT<\/b>) 2017, Hyderabad, India, Jan 2017<\/li> \n\n<li>\nToral Shah, `<em>Multiple fault testability of BDD based circuit synthesi<\/em>`, 8<sup>th<\/sup> IEEE International Workshop on Reliability Aware System Design and Test (<b>RASDAT<\/b>) 2017, Hyderabad, India, Jan 2017<\/li>\n\n<li>\nBinod Kumar, Ankit Jindal, Jaynarayan Tudu, and Brajesh Pandey, `<em>An Integrated solution for manufacturing testing and post-silicon validation<\/em>`, 8<sup>th<\/sup> IEEE International Workshop on Reliability Aware System Design and Test (<b>RASDAT<\/b>) 2017, Hyderabad, India, Jan 2017<\/li>\n\n<li>\nSatyadev Ahlawat and Darshit Vaghani, `<em>On securing scan chain from side channel attack<\/em>, 8<sup>th<\/sup> IEEE International Workshop on Reliability Aware System Design and Test (<b>RASDAT<\/b>) 2017, Hyderabad, India, Jan 2017<\/li>\n\n<li>\nShoba Gopalkrishnan, `<em>On improving fault tolerance through hardware software techniques<\/em>`, 8<sup>th<\/sup> IEEE International Workshop on Reliability Aware System Design and Test (<b>RASDAT<\/b>) 2017, Hyderabad, India, Jan 2017<\/li>\n \n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-37b585c elementor-widget elementor-widget-menu-anchor\" data-id=\"37b585c\" data-element_type=\"widget\" data-widget_type=\"menu-anchor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div id=\"2016\" class=\"elementor-menu-anchor\"><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-fe7851a elementor-widget elementor-widget-heading\" data-id=\"fe7851a\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2016<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-d2f2d6d elementor-widget elementor-widget-text-editor\" data-id=\"d2f2d6d\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul>\n \t<li>\nBinod Kumar, Ankit Jindal, Jaynarayan Tudu, and Virendra Singh, `<em>A methodology for post silicon debug utilizing progressive random access scan architecture<\/em>`, 17<sup>th<\/sup> IEEE Workshop on RTL and High Level Testing (<b>WRTLT<\/b>) 2016, Hiroshima, Japan, Nov 2016<\/li>\n\n<li>\nRohini Gulve and Virendra Singh, `<em>R-fill: Timing aware capture power reduction using ZOLP<\/em>`, 17<sup>th<\/sup> IEEE Workshop on RTL and High Level Testing (<b>WRTLT<\/b>) 2016, Hiroshima, Japan, Nov 2016<\/li>\n\n<li>\nAnkush Srivastava, Virendra Singh, Adit Singh, and Kewal Saluja, `<em>Path-based approach to identify timing critical paths under aging<\/em>`, 17<sup>th<\/sup> IEEE Workshop on RTL and High Level Testing (<b>WRTLT<\/b>) 2016, Hiroshima, Japan, Nov 2016<\/li>\n\n<li>\nNirmal Kumar Boran, Rameshwar Prasad Meghwal, Kuldeep Sharma, Binod Kumar, and Virendra Singh, `<em>Performance modelling of heterogeneous ISA multicore architecture<\/em>`, 14<sup>th<\/sup> IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2016, Yerevan, Armenia, Oct 2016<\/li>\n\n<li>\nToral Shah, Virendra Singh and Anzhela Matrosova, `<em>ROBDD based path delay fault testable combinational circuit synthesis<\/em>`, 14<sup>th<\/sup> IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2016, Yerevan, Armenia, Oct 2016<\/li>\n\n<li>\nSatyadev Ahlawat, Darshit Vaghani, Rohini Gulve, and Virendra Singh, `<em>Enabling LOS delay test with slow scan enable<\/em>`, 14<sup>th<\/sup> IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2016, Yerevan, Armenia, Oct 2016<\/li>\n\n<li>\nRohini Gulve and Virendra Singh, `<em>ILP Based Don`t Care Bits Filling Technique For Capture Power Reduction<\/em>`, 14<sup>th<\/sup> IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2016, Yerevan, Armenia, Oct 2016<\/li>\n\n<li>\nBinod Kumar, Boda Nehru, Brajesh Pandey, Jaynarayan T Tudu, and Virendra Singh, `<em>A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture<\/em>`, 14<sup>th<\/sup> IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2016, Yerevan, Armenia, Oct 2016<\/li>\n\n<li>\nBinod Kumar, Ankit Jindal and Virendra Singh, `<em>A trace signal selection algorithm for improved post silicon debug<\/em>`, 14<sup>th<\/sup> IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2016, Yerevan, Armenia, Oct 2016<\/li>\n\n<li> \nShoba Gopalkrishnan and Virendra Singh, `<em>REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture<\/em>`, 22<sup>nd<\/sup> IEEE International Symposium on Online Testing and Robust System Design (<b>IOLTS<\/b>) 2016, Catalunya, Spain, July 2016<\/li>\n\n<li>\nSatyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, and Virendra Singh, `<em>A high performance scan flip-flop design for serial and mixed mode scan test<\/em>` 22<sup>nd<\/sup> IEEE International Symposium on Online Testing and Robust System Design (<b>IOLTS<\/b>) 2016, Catalunya, Spain, July 2016<\/li>\n\n<li>\nJaynarayan Tudu and Satyadev Ahlawat, `<em>Guided Shifting of Test Pattern to Minimize Test Time in Multiple Serial Scan<\/em>`,20<sup>th<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2016, Guwahati, India, May 2016<\/li> \n\n<li>\nSatyadev Ahlawat and Jaynarayan T. Tudu, `<em>On Minimization of Test Power through Modified Scan Flip-Flop<\/em>`, 20<sup>th<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2016, Guwahati, India, May 2016<\/li>\n\n<li>\nRohini Gulve, Nihar Hage and Jaynarayan T Tudu, `<em>On Determination of Instantaneous Peak and Cycle Peak Switching using ILP<\/em>`, 20<sup>th<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2016, Guwahati, India, May 2016<\/li>\n\n<li>\nBinod Kumar, Boda Nehru, Brajesh Pandey and Jaynarayan Tudu, `<em>Skip-Scan: A Methodology for Test Time Reduction<\/em>`, 20<sup>th<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2016, Guwahati, India, May 2016<\/li>\n\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-5f8c48b elementor-widget elementor-widget-menu-anchor\" data-id=\"5f8c48b\" data-element_type=\"widget\" data-widget_type=\"menu-anchor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div id=\"2015\" class=\"elementor-menu-anchor\"><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-eb446dc elementor-widget elementor-widget-heading\" data-id=\"eb446dc\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2015<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-e877fbb elementor-widget elementor-widget-text-editor\" data-id=\"e877fbb\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul>\n \t<li> \nAnkush Srivastava, Virendra Singh, Adit Singh, and Kewal Saluja, &#8216;<em>A Methodology for Identifying High Timing Variability Paths in Complex Designs<\/em>&#8216;, 24<sup>th<\/sup> IEEE Asian Test Symposium (<b>ATS<\/b>) 2015, Mumbai, India, Nov 2015<\/li>\n\n<li> \nSatyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, and Virendra Singh, `<em>A New Scan Flip-Flop Design to Eliminate Performance Penalty of Scan<\/em>`, 24<sup>th<\/sup> IEEE Asian Test Symposium (<b>ATS<\/b>) 2015, Mumbai, India, Nov 2015<\/li>\n\n<li> \nAdithyalal P.M, Shankar Balachandran, and Virendra Singh, `<em>A Soft Error Resilient Low Leakage SRAM Cell Design<\/em>`, 24<sup>th<\/sup> IEEE Asian Test Symposium (<b>ATS<\/b>) 2015, Mumbai, India, Nov 2015<\/li>\n\n<li> \nParth Lathigara, Shankar Balachandran, and Virendra Singh, `<em>Application Behavior Aware Re-Reference Interval Prediction for LLC<\/em>`, 33<sup>rd<\/sup> IEEE International Conference on Computer Design (<b>ICCD<\/b>) 2015, New York, USA, October 2015<\/li>\n\n<li> \nToral Shah, Anzhela Matrosova, and Virendra Singh, `<em>PDF Testability of a Combinational Circuit Derived by Covering ROBDD Nodes by Invert-And-Or Graph<\/em>`, 19<sup>th<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2015, Ahmedabad, India, May 2015<\/li>\n\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-5381341 elementor-widget elementor-widget-menu-anchor\" data-id=\"5381341\" data-element_type=\"widget\" data-widget_type=\"menu-anchor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div id=\"2014\" class=\"elementor-menu-anchor\"><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-e2e873d elementor-widget elementor-widget-heading\" data-id=\"e2e873d\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2014<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-29a1ee5 elementor-widget elementor-widget-text-editor\" data-id=\"29a1ee5\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul>\n \t<li>\nD. Nikolov, U. Ingelsson, V. Singh, and E. Larsson, `<em>Evaluation of level of confidence and optimization of roll-back recovery with check pointing for real time systems<\/em>`, Microelectronics Reliability, vol. 54, 2014, pp. 1022-1049.\n\n<li>\nJaynarayan Tudu and Virendra Singh, `<em>Guided shifting of test patterns to minimize the test time in serial scan<\/em>`, 15<sup>th<\/sup> IEEE Workshop on RTL and High Level Testing (<b>WRTLT<\/b>) 2014, Hangzhou, China, Nov 2014<\/li>\n \n<li>\nPrashant Singh, Toral Shah, and Virendra Singh, `<em>An improved single input change based built-in-self-test for delay testing<\/em>`, 15<sup>th<\/sup> IEEE Workshop on RTL and High Level Testing (<b>WRTLT<\/b>) 2014, Hangzhou, China, Nov 2014<\/li>\n\n<li>\nLokesh Siddhu, Amit Mishra, and Virendra Singh, `<em>Operand isolation circuit with reduced overhead for datapath design<\/em>`, 27<sup>th<\/sup> International Conference on VLSI Design (<b>VLSID<\/b>) 2014, Mumbai, India, Jan 2014<\/li>\n\n<li>\nAnzhela Matrosova, Evgenii Mitrofanov, and Virendra Singh, `<em>Fully delay testable sequential circuit design<\/em>`, 5<sup>th<\/sup> IEEE International Workshop on Reliability Aware Stystem Design and Test (<b>RASDAT<\/b>), Mumbai, India, Jan 2014<\/li> \n\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-6a4233a elementor-widget elementor-widget-menu-anchor\" data-id=\"6a4233a\" data-element_type=\"widget\" data-widget_type=\"menu-anchor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div id=\"2013\" class=\"elementor-menu-anchor\"><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-009d7d6 elementor-widget elementor-widget-heading\" data-id=\"009d7d6\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2013<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-9c3fec1 elementor-widget elementor-widget-text-editor\" data-id=\"9c3fec1\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul>\n \t<li> A.Matrosova, E.Mitrofanov, and V.Singh, &#8216;<em>Delay Testable Sequential Circuit Design<\/em>&#8216;, 11<sup>th<\/sup> IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2013, Rostov-on-Don, Russia, Sept 2013<\/li>  \n\n<li> Jaynarayan Tudu, Deepak Malani, and Virendra Singh, `<em>Level Accurate Peak Power Estimation using BILP<\/em>`, 17<sup>th<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2013, Jaipur, India, July 2013<\/li>\n\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-842544a elementor-widget elementor-widget-menu-anchor\" data-id=\"842544a\" data-element_type=\"widget\" data-widget_type=\"menu-anchor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div id=\"2012\" class=\"elementor-menu-anchor\"><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-0b4de19 elementor-widget elementor-widget-heading\" data-id=\"0b4de19\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2012<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-09a499f elementor-widget elementor-widget-text-editor\" data-id=\"09a499f\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul>\n \t<li> Suraj Sindia, Vishwani D. Agrawal, and Virendra Singh, `<em>Parametric fault testing of non-linear analog circuits based on polynomial and v-transform coefficients<\/em>`, Journal of Electronic Testing: Theory and Applications (<b>JETTA<\/b>), Vol. 28, No. 5, pp. 557-571, 2012<\/li>\n\n<li> Suraj Sindia, Vishwani D. Agrawal, and Virendra Singh, `<em>Defect level and fault coverage in coefficient based analog circuit testing<\/em>`, Journal of Electronic Testing: Theory and Applications (<b>JETTA<\/b>), Vol. 28, No. 4, pp. 541-549, 2012<\/li>\n\n<li> Satyadev Ahlawat, Ashok Suhag, Jaynarayan Tudu, and Virendra Singh, `<em>Power aware scan flip-flop design for scan test<\/em>`, 13<sup>th<\/sup> IEEE Workshop on RTL and High Level testing (<b>WRTLT<\/b>) 2012, Niigata, Japan, Nov 2012<\/li>\n\n<li> Pawan Kumar, and Virendra Singh, `<em>Efficient regular expression pattern matching for network intrusion detection system using modified word based automata<\/em>`, 5<sup>th<\/sup> ACM International Conference on Security of Information and Networks (<b>SIN<\/b>) 2012, Jaipur, India, Oct 2012<\/li>\n\n<li> Indira Rawat, M.K. Gupta, and Virendra Singh, `<em>Scheduling test for 3D SOCs with temperature constraints<\/em>`, 10<sup>th<\/sup> IEEE International East West Design and Test Symposium (<b>EWDTS<\/b>) 2012, Kharkov, Ukrain, Sep 2012<\/li>\n\n<li> A. Matrosova, E. Nikolaeva, D. Kudin, and V. Singh, `<em>PDF testability of circuits derived by special covering ROBDDs with gates<\/em>`, 10<sup>th<\/sup> IEEE International East West Design and Test Symposium (<b>EWDTS<\/b>) 2012, Kharkov, Ukrain, Sep 2012<\/li>\n\n<li> A. Matrosova, E. Nikolaeva, D. Kudin, and V. Singh, `<em>PDF testability of circuits derived by special covering ROBDDs with gates<\/em>`, 10<sup>th<\/sup> IEEE International East West Design and Test Symposium (<b>EWDTS<\/b>) 2012, Kharkov, Ukrain, Sep 2012<\/li>\n\n<li> Mohammed Shayan, Virendra Singh, Adit Singh, and Masahiro Fujita, `<em>SEU tolerant robust memory cell design<\/em>`, 18<sup>th<\/sup> IEEE International On-Line Testing Symposium (<b>IOLTS<\/b>) 2012`, Sitges, Spain, June 2012<\/li>\n\n<li> Jaynarayan Tudu, Deepak Malani, and Virendra Singh, `<em>ILP based approach for input vector controlled toggle maximization in combinational circuits<\/em>`, 16<sup>th<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2012, Kolkata, India, July 2012<\/li>\n\n<li>Mohammad Shayan, Virendra Singh, Adit Singh, and Masahiro Fujita, `<em>SEU tolerant robust latch design<\/em>`, 16<sup>th<\/sup> International Symposium on VLSI Design and Test (<b>VDAT<\/b>) 2012, Kolkata, India, July 2012<\/li>\n\n<li>Indira Rawat, M.K. Gupta, and Virendra Singh, `<em>Thermal aware test scheduling of 3D SoCs<\/em>`, 5<sup>th<\/sup> IEEE International Workshop on Impact of Low Power Design on Test and Reliability (<b>LPonTR<\/b>) 2012, Annecy, France, May 2012<\/li>\n\n<li>Suraj Sindia, Vishwani D. Agrawal, and Virendra Singh, `<em>Impact of process variation on computers used for image processing<\/em>`, IEEE International Symposium on Circuits and Systems (<b>ISCAS<\/b>) 2011, Seoul, Korea, May 2012<\/li>\n\n<li>Prasanth V., Rubin Parekhji, and Virendra Singh, `<em>Derating based hardware optimizations in soft error tolerant designs<\/em>`, 30<sup>th<\/sup> IEEE VLSI Test Symposium (<b>VTS<\/b>) 2012, Hawai, USA, April 2012<\/li>\n\n<li>Vijay Sheshadri, Prasanth V., Rubin Parekhji, Vishwani D. Agrawal, and Virendra Singh, `<em>Evaluating impact of soft errors in embedded system<\/em>`, IEEE International Workshop on Reliability Aware System Design and Test (<b>RASDAT<\/b>) 2012, Hyderabad, India, Jan 2012<\/li>\n\n<li>Satyadev Ahlawat, Virendra Singh, Shashidhar Bapat, and Karthik Madhugiri, `<em>Low power scan flip-flop design to eliminate output gating overhead for critical paths<\/em>`, IEEE International Workshop on Reliability Aware System Design and Test (<b>RASDAT<\/b>) 2012, Hyderabad, India, Jan 2012<\/li>\n\n<li>Mohammed Shayan, Virendra Singh, Adit Singh, and Masahiro Fujita, `<em>A highly robust and cost effective SEU tolerant memory cell<\/em>`, IEEE International Workshop on Reliability Aware System Design and Test (<b>RASDAT<\/b>) 2012, Hyderabad, India, Jan 2012<\/li>\n\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-4b2fc31 elementor-widget elementor-widget-menu-anchor\" data-id=\"4b2fc31\" data-element_type=\"widget\" data-widget_type=\"menu-anchor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div id=\"2011\" class=\"elementor-menu-anchor\"><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-8c648d7 elementor-widget elementor-widget-heading\" data-id=\"8c648d7\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2011<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-fd79a10 elementor-widget elementor-widget-text-editor\" data-id=\"fd79a10\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<li>Pramod Subramanyan, Virendra Singh, Kewal Saluja, and Erik Larsson, `<em>Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors<\/em>`, 29<sup>th<\/sup> IEEE International Conference on Computer Design (<b>ICCD<\/b>) 2011, Amherst, MA, USA, October 2011<\/li>\n\n<li>Mohammed Abdul Razzaq, Virendra Singh, and Adit Singh, `<em>SSTKR: Secure and testable scan design through test key randomization<\/em>`, 20<sup>th<\/sup> IEEE Asian Test Symposium (<b>ATS<\/b>) 2011, New Delhi, India, Nov. 2011<\/li>\n\n<li>Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `<em>Test and diagnosis of analog circuits using moment generating functions<\/em>`, 20th IEEE Asian Test Symposium (<b>ATS<\/b>) 2011, New Delhi, India, Nov. 2011<\/li>\n\n<li>Manas Puthal, Virendra Singh, MS Gaur and Vijay Laxmi, `<em>C-Routing: An adaptive hierarchical NoC routing methodology<\/em>`, 19<sup>th<\/sup> IFIP\/IEEE International Conference on Very Large Scale Integration (<b>VLSI-SoC<\/b>) 2011, Hongkong, China, October 2011<\/li>\n\n<li>Harsh Gidra, Israrul Haque, Nitin Kumar, M. Sargurunathan, M.S. Gaur, Vijay Laxmi, Mark Zwolinski, and Virendra Singh, `<em>Parallelizing TUNAMI-N1 using GP-GPU<\/em>`, 13<sup>th<\/sup> IEEE International Conference on High Performance Computing and communication (<b>HPCC<\/b>) 2011, Banff, Canada, September 2011<\/li>\n\n<li>Anzhela Matrosova, Virendra Singh, Alexey Melnikov, and Ruslan Mukhamedov, `<em>Selection of state variables for partially enhanced scan<\/em>`, 9<sup>th<\/sup> IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2011, Sevastopol, Ukraine, September 2011<\/li>\n\n<li>Mohammad Abdul Razzaq, Alok Baluni, Ram Rakesh Jangir, Virendra Singh, and Masahiro Fujita, `<em>On synthesis of degradation aware circuits at higher level of abstraction<\/em>`, 9<sup>th<\/sup> IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2011, Sevastopol, Ukraine, September 2011<\/li>\n\n<li>Pawan Kumar and Virendra Singh, `<em>Efficient regular expression pattern matching using cascaded automata architecture for network intrusion detection system<\/em>`, 9<sup>th<\/sup> IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2011, Sevastopol, Ukraine, September 2011<\/li>\n\n<li>V. Prasanth, Virendra Singh, and Rubin Parekhji, `<em>Reduced overhead soft error mitigation methodology using error control coding technique<\/em>`, 17<sup>th<\/sup> IEEE International On-Line Test Symposium (<b>IOLTS<\/b>) 2011, Athens, Greece, July 2011<\/li>\n\n<li>Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `<em>Level of confidence evaluation and its usage for roll-back recovery and checkpoint optimization<\/em>`, Workshop on Dependable and Secure Nanocomputing (<b>WDSN<\/b>) 2011, Hongkong, China, May 2011<\/li>\n\n<li>Vinutha Konandur, Virendra Singh, MS Gaur, and Anzhela Matrosova, `<em>Fault Grading at Higher Level of Abstraction<\/em>`, IEEE International Workshop on Processor Verification, Test and Debug (<b>IWPVTD<\/b>) 2011, Trondheim, Norway, May 2011<\/li>\n\n<li>A. Matrosova, S. Ostanin, A. Milnikov, and Virendra Singh, `<em>Using AND-OR tree for path delay faults<\/em>`,IEEE International Workshop on Processor Verification, Test and Debug (<b>IWPVTD<\/b>) 2011, Trondheim, Norway, May 2011<\/li>\n\n<li>Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `<em>Study on level of confidence for rollback recovery with check-pointing<\/em>`, Workshop on Dependability Issues in Deep-submicron Technologies (<b>DDT<\/b>) 2011, Trondheim, Norway, May 2011<\/li>\n\n<li>Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `<em>Nonlinear analog circuit test and diagnosisunder process variation using V-transform coefficients<\/em>`, 29<sup>th<\/sup> IEEE VLSI Test Symposium (<b>VTS<\/b>), 2011, California, USA, May 2011<\/li>\n\n<li>Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `<em>Testing linear and non-linear analog circuits using moment generation functions<\/em>`, 12<sup>th<\/sup> IEEE Latin American Test Workshop (<b>LATW<\/b>) 2011, Porto de Galinhas, Brazil, March 2011<\/li>\n\n<li>Chao Han, Adit Singh, and Virendra Singh, `<em>Efficient partial enhanced Scan for high coverage delay testing<\/em>`, 2011 Joint IEEE International Conference on Industrial Technology and 43<sup>rd<\/sup> Southeastern Symposium on System Theory (<b>ICIT-SSST<\/b>) 2011, Auburn, USA, March 2011<\/li>\n\n<li>Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `<em>Distinguishing process variation induced faults from manufacturing defects in analog circuits using V-transform coefficients<\/em>`, 2011 Joint IEEE International Conference on Industrial Technology and 43<sup>rd<\/sup> Southeastern Symposium on System Theory (<b>ICIT-SSST<\/b>) 2011, Auburn, USA, March 2011<\/li>\n\n<li>Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal Saluja, and Masahiro Fujita, `<em>SEU tolerant SRAM cell<\/em>`, International Symposium on Quality Electronic Design (<b>ISQED<\/b>) 2011, Santa Clara, CA, USA, March 2011<\/li>\n\n<li>Naveen Choudhary, M.S. Gaur, Vijay Laxmi, and Virendra Singh, `<em>Traffic aware topology generation methodology for application specific NoC<\/em>`, IEEE International Symposium on Electronic Design, Test and Application (<b>DELTA<\/b>) 2011, Queens Town, New Zealand, Jan 2011<\/li>\n\n<li>Navaneeth Rameshan, Mark Zwolinski, Vijay Laxmi, M.S. Gaur, Virendra Singh, and Lalith P., `<em>Acceleration of functional validation using GPGPU<\/em>`, IEEE International Symposium on Electronic Design, Test and Application (<b>DELTA<\/b>) 2011, Queens Town, New Zealand, Jan 2011<\/li>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-b0d1c52 elementor-widget elementor-widget-menu-anchor\" data-id=\"b0d1c52\" data-element_type=\"widget\" data-widget_type=\"menu-anchor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div id=\"2010\" class=\"elementor-menu-anchor\"><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-744f87d elementor-widget elementor-widget-heading\" data-id=\"744f87d\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2010<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-d51217e elementor-widget elementor-widget-text-editor\" data-id=\"d51217e\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul>\n \t<li>[Book Chapter] Dimitar Nikolov, Mikael Vayrynen, Urban Ingelson, Virendra Singh, and Erik Larsson, `<em>Optimizing Fault Tolerance for Multi-Processor System-on-Chip<\/em>`, Design and Test Technology for Dependable Systems-on-Chip, Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, 2010, Hardcover, ISBN:978-1-6096-0212-3.\n\n<li>Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal Saluja, and Masahiro Fujita, `<em>SEU tolerant SRAM for FPGA application<\/em>`, International Conference on Field Programmable Technology (<b>FPT<\/b>) 2010, Beijing, Dec 2010<\/li>\n\n<li>Amit Mishra, Nidhi Sinha, Satyadev Ahlawat, Virendra Singh, Sreejit Chakravarty, and Adit Singh, `<em>A modified scan flip-flop for test power reduction<\/em>`, 19<sup>th<\/sup> IEEE Asian Test Symposium (<b>ATS<\/b>) 2010, Shanghai, China, Dec 2010<\/li>\n\n<li>Jaynarayan Tudu, Erik Larsson, and Virendra Singh, `<em>Test Scheduling of modular system-on-chip under capture power constraints<\/em>`, 11<sup>th<\/sup> IEEE Workshop on RTL and High Level Test (<b>WRTLT<\/b>) 2010, Shanghai, China, Dec 2010<\/li>\n\n<li>Naveen Choudhary, M.S. Gaur, Vijay Laxmi, and Virendra Singh, `<em>Energy Aware Design Methodologies for Application Specific NoC<\/em>`, 28<sup>th<\/sup> Norchip Conference (<b>NORCHIP<\/b>), 2010, Tampere, Finland, Nov 2010<\/li>\n\n<li>Anzhela Matrosova, Valeriy Lipsky, Aleksey Melnikov, and Virendra Singh, `<em>Path delay faults and ENF<\/em>`, IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2010, St. Petersburg, Russia, Sep 2010<\/li>\n\n<li>Vinay N.S, Indira Rawat, Erik Larsson, M.S. Gaur, and Virendra Singh, `<em>Thermal aware test scheduling for stacked multi-chip modules<\/em>`, IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2010, St. Petersburg, Russia, Sep 2010<\/li>\n\n<li>K.R. Vinutha, Virendra Singh, Anzhela Matrosova, and M.S. Gaur, `<em>Fault grading using instruction-execution graph<\/em>`, IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2010, St. Petersburg, Russia, Sep 2010<\/li>\n\n<li>Adit Kajala, Gayaprasad Sinsinwar, Rahul Choudhary, Jaynarayan Tudu, and Virendra Singh, `<em>On selection of state variables for delay test of identical functional units<\/em>`, IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2010, St. Petersburg, Russia, Sep 2010<\/li>\n\n<li>Gayaprasad Sinsinwar, Rahul Choudhary, Aditi kajala, and Virendra Singh, `<em>Test program generation for simultaneous testing of multiple identical functional units<\/em>`, IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2010, St. Petersberg, Russia, Sep 2010<\/li>\n\n<li>Prasanth V., Virendra Singh, and Rubin Parekhji, `<em>Robust detection of soft errors using delayed capture methodology<\/em>`, IEEE International Online Testing Symposium (<b>IOLTS<\/b>) 2010, Corfu, Greece, July 2010<\/li>\n\n<li>Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `<em>Energy ffficient fault tolerance in chip multiprocessors using critical value forwarding<\/em>`, 40<sup>th<\/sup> IEEE International Conference on Dependable Systems and Networks (<b>DSN<\/b>), Chicago, IL, USA, June 2010<\/li>\n\n<li>Abhishek A., Amanulla Khan, Virendra Singh, Kewal Saluja, and Adit Singh, `<em>Test application time minimization for RAS using basis optimization of column decoder<\/em>`, IEEE International Symposium on Circuits and Systems (<b>ISCAS<\/b>) 2010<\/li>, Paris, France, May 2010<\/li>\n\n<li>Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `<em>Genetic algorithm based topology generation for application specific network-on-chip<\/em>`, IEEE International Symposium on Circuits and Systems (<b>ISCAS<\/b>) 2010, Paris, France, May 2010<\/li>\n\n<li>Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal Saluja, and Adit Singh, `<em>Modified T-FF bases scan cell for RAS<\/em>`, 15th IEEE European Test Symposium (<b>ETS<\/b>) 2010, Prague, Czech Rep., May 2010<\/li>\n\n<li>Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `<em>Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach<\/em>`, 15<sup>th<\/sup> IEEE European Test Symposium (<b>ETS<\/b>) 2010, Prague, Czech Rep., May 2010<\/li>\n\n<li>Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `<em>Power efficient redundant execution for chip multiprocessors<\/em>`, Great Lake Symposium on VLSI (<b>GLSVLSI<\/b>) 2010, Providence, Rhode Island, USA May 2010<\/li>\n\n<li>Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `<em>Graph theoretic approach for scan cell reordering to minimize peak shift power<\/em>`, 20<sup>th<\/sup> ACM Great Lake Symposium on VLSI (<b>GLSVLSI<\/b>) 2010, Providence, Rhode Island, USA May 2010<\/li>\n\n<li>Dimitar Nikolov, Erik Karlsson, Urban Ingelsson, Virendra Singh, and Erik Larsson, `<em>Mapping and scheduling of jobs in homogeneous NoC-based MPSoC<\/em>`, 10<sup>th<\/sup> Swedish System-on-Chip Conference, Kolma<sup>rd<\/sup>en, Sweden, May 2010<\/li>\n\n<li>Pramod Subramanyam, Virendra Singh, Kewal Saluja, and Erik Larsson, `<em>A low cost redundant execution architectures for Chip multiprocessors<\/em>`, Design Automation and Test in Europe (<b>DATE<\/b>) 2010, Dresden, Germany, March 2010<\/li>\n\n<li>L. Suresh, N. Rameshan, A. Narayan, M. Zwolinski, M.S. Gaur, V. Laxmi, and V. Singh, `<em>EDA design flow acceleration by GP-GPU<\/em>`, 2<sup>nd<\/sup> Workshop on Designing for embedded parallel computing plateform: Architectures, design tools, and applications (in conjunction with DATE 2010) 2010, Dresden, Germany, March 2010<\/li>\n\n<li>Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `<em>Fast energy aware application specific network-on-chip topology generator<\/em>`, IEEE International Advanced Computing Conference 2010, Patiala, India, Feb 2010<\/li>\n\n<li>Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `<em>Estimating error probability and its application for optimizing roll-back recovery with checkpointing<\/em>`, IEEE Symposium on Electronic Design, Test &#038; Applications (<b>DELTA<\/b>) 2010, Ho Chi Minh , Vietnam, Jan 2010<\/li>\n\n<li>Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `<em>On-line techniques to adjust and optimize checkpointing frequency<\/em>`, IEEE International Workshop on Reliability Aware System Design and Test (<b>RASDAT<\/b>) 2010, Bangalore, India, Jan 2010<\/li>\n\n<li>Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal Saluja, Hideo Fujiwara, and Adit Singh, `<em>On Minimization of Test Application Time for RAS<\/em>`, 23<sup>rd<\/sup> International Conference on VLSI Design (<b>ICVD<\/b>) 2010, Bangalore, Jan 2010<\/li>\n\n<li>Suraj Sindia, Virendra Singh, and Vishwani D. Agrawal, `<em>Parametric Fault Diagnosis of Nonlinear Analog Circuits using Polynomial Coefficients<\/em>`, 23<sup>rd<\/sup> International Conference on VLSI Design (<b>ICVD<\/b>) 2010, Bangalore, Jan 2010<\/li>\n\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-6820475 elementor-widget elementor-widget-menu-anchor\" data-id=\"6820475\" data-element_type=\"widget\" data-widget_type=\"menu-anchor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div id=\"2009\" class=\"elementor-menu-anchor\"><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-ecbfb32 elementor-widget elementor-widget-heading\" data-id=\"ecbfb32\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">2009<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-d3a48f7 elementor-widget elementor-widget-text-editor\" data-id=\"d3a48f7\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul>\n \t<li>Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `<em>Cojoined Irregular Topology and Routing Table Generation for Network-on-Chip<\/em>`, IEEE INDICON 2009, Gandhi Nagar, India, Dec 2009<\/li>\n\n<li>Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `<em>Designing Application Specific Irregular Topology for Network-on-Chip<\/em>`, 17<sup>th<\/sup> International Conference on Advanced Computing and Communications (<b>ADCOM<\/b>) 2009, Bangalore, Dec 2009<\/li>\n\n<li>Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `<em>Scan Cells Reordering to Minimize Peak Power during Scan Testing of SoC<\/em>`, IEEE WRTLT 09, Hong Kong, Nov. 2009<\/li>\n\n<li>Venkat Rajesh, Erik Larsson, MS Gaur, and Virendra Singh, `<em>An Even Odd DFD Technique for Scan Chain Diagnosis<\/em>`, IEEE WRTLT 09, Hong Kong, Nov. 2009<\/li>\n\n<li>Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `<em>Multi-tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients<\/em>`, IEEE Asian Test Symposium (<b>ATS<\/b>) 2009, Taichung, Taiwan, Nov 2009<\/li>\n\n<li>Deepak K.G., Robinson Reyna, Virendra Singh, and Adit Singh, `<em>Leveraging Partial Enhanced Scan for Improved Observabilty in Delay Fault Testing<\/em>`, IEEE Asian Test Symposium (<b>ATS<\/b>) 2009, Taichung, Taiwan, Nov 2009<\/li>\n\n<li>Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `<em>V-Transform: An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits<\/em>`, IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2009, Moscow, Russia, Sep 2009<\/li>\n\n<li>Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik Larsson, and Virendra Singh, `<em>Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation<\/em>`, IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2009, Moscow, Russia, Sep 2009<\/li>\n\n<li>Viney Kumar, Rahul Raj, and Virendra Singh, `<em>FREP: A Soft-Error Resilient Pipelined RISC Architecture<\/em>`, IEEE East-West Design and Test Symposium (<b>EWDTS<\/b>) 2009, Moscow, Russia, Sep 2009<\/li>\n\n<li>Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Adit Singh, `<em>Capture Power Reduction for Modular System-on-Chip Test<\/em>`, IEEE\/VSI VLSI Design and Test Symposium (<b>VDAT<\/b>), Bangalore, India, July 2009.\n\n<li>Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `<em>Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing<\/em>`, IEEE\/VSI VLSI Design and Test Symposium (<b>VDAT<\/b>), Bangalore, India, July 2009<\/li>\n\n<li>Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `<em>Power Efficient Redundant Execution for Chip Multiprocessor<\/em>`, Workshop on Dependable and Secure Nanocomputing (<b>WDSN<\/b>) 2009, Lisbon, Portugal, June 2009<\/li>\n\n<li>Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Vishwani D. Agrawal, `<em>On Minimization of Peak Power during SoC Test<\/em>`, IEEE European Test Symposium (<b>ETS<\/b>) 2009, Seville, Spain, May 2009<\/li>\n\n<li>Suraj Sindia, Virendra Singh, and Vishwani D. Agrawal, `<em>Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits<\/em>`, 18<sup>th<\/sup> IEEE North Atlantic Test Workshop (<b>NATW<\/b>) 2009, New York, USA, May 2009<\/li>\n\n<li>Reshma Jumani, Niraj Jain, Virendra Singh, and Kewal K. Saluja, `<em>DX-Compactor: Distributed X-Compaction for SoC Test<\/em>`, ACM Annual Great Lake Symposium on VLSI (<b>GLSVLSI<\/b>) 2009, Boston, USA, May 2009<\/li>\n\n<li>Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `<em>Coefficient-Based Parametric Testing of Non-Linear Analog Circuits<\/em>`, ACM Annual Great Lake Symposium on VLSI (<b>GLSVLSI<\/b>) 2009, Boston, USA, May 2009<\/li>\n\n<li>Mikael Vayrynen, Virendra Singh, and Erik Larsson, `<em>Fault-Tolerant Average Execution Time Optimization for General Purpose Multi-Processor System-on-Chips<\/em>`, Intl. Conference on Design Automation and Test in Europe (<b>DATE<\/b>) 2009, Nice, France, Apr 2009<\/li>\n\n<li>Vinay NS, Erik Larsson, and Virendra Singh, `<em>Thermal Aware Test Scheduling of Stacked Multi-Chip Modules<\/em>`, Workshop on 3D Integration (In conjunction with DATE 2009), Nice, France, Apr 2009<\/li>\n\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-4a7085d elementor-widget elementor-widget-menu-anchor\" data-id=\"4a7085d\" data-element_type=\"widget\" data-widget_type=\"menu-anchor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div id=\"2008\" class=\"elementor-menu-anchor\"><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-7ea5af6 elementor-widget elementor-widget-heading\" data-id=\"7ea5af6\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">Selected Publications (Before 2008)<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-794074d elementor-widget elementor-widget-text-editor\" data-id=\"794074d\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul>\n \t<li> Virendra Singh and Erik Larsson, `<em>On Reduction of Capture Power for Modular System-on-Chip Test<\/em>`, 9<sup>th<\/sup> IEEE WRTLT 2008, pp. 35-40, Sapporo, Japan, Nov 2008<\/li>\n\n<li> Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `<em>Instruction-Based Self-Testing of Delay Faults in Pipelined Processors<\/em>`, IEEE Trans. on VLSI Systems, Vol. 14, No. 11, Nov. 2006, pp. 1203-1215<\/li>\n\n<li> Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `<em>Delay Fault Testing of Processor Cores in Functional Mode<\/em>`, IEICE Trans. on Information &#038; Systems, Vol. E-88D, No. 3, March 2005, pp. 610-618<\/li>\n\n<li> Michiko Inoue, Kazuko Kambe, Virendra Singh and Hideo Fujiwara, `<em>Software-Based Self-Test of Processors for Stuck-at Faults and Path Delay Faults<\/em>`, Trans. of IEICE (DI), Vol. J88-D-I, No. 3, June 2005, pp. 1003-1011<\/li>\n\n<li> Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `<em>Program-Based Testing of Superscalar Microprocessor<\/em>`, Proceedings of the IEEE 14<sup>th<\/sup> North Atlantic Test Workshop (<b>NATW<\/b>), May 2005, pp. 79-86, Berlington, VT, USA, May 2005<\/li>\n\n<li> Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `<em>Testing Superscalar Processors in Functional Mode<\/em>`, Proceedings of the 15<sup>th<\/sup> International Conference on Field Programmable Logic and Applications, Aug. 2005<\/li>\n\n<li> Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `<em>Instruction-Based Delay Fault Self-Testing of Pipelined Processor Cores<\/em>`, Proceedings of the IEEE International Symposium on Circuits and Systems (<b>ISCAS<\/b>) 2005, Kobe, Japan, May 2005<\/li>\n\n<li> Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `<em>Instruction-Based Delay Fault Testing of Processor Cores<\/em>`, Proceedings of the International Conference on VLSI Design (<b>VLSID<\/b>) 2004, Mumbai, India Jan. 2004<\/li>\n\n<li> Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `<em>Software-Based Delay Fault Testing of Processor Cores<\/em>`, Proceedings of the IEEE 12<sup>th<\/sup> Asian Test Symposium (<b>ATS<\/b>) 2003, Xian, China, Nov. 2003<\/li>\n\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Publications Journal \/ Conference \/ Workshop 2021 Jaynarayan Tudu, Satyadev Ahlawat, Sonali Shukla, and Virendra Singh, `A framework for configurable for joint-scan design-for-test architecture`, Journal of Electronic Testing: Theory and Application (JETTA), 2021 Abhinish Anand, Winnie Thomas, Suryakant Toraskar, and Virendra Singh, `Predictive warp scheduling for efficient execution in GPGPU`, 31st ACM Great Lake Symposium &hellip;<\/p>\n<p class=\"read-more\"> <a class=\"\" href=\"https:\/\/www.ee.iitb.ac.in\/~cadsl\/publications\/\"> <span class=\"screen-reader-text\">Publications<\/span> Read More &raquo;<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"site-sidebar-layout":"no-sidebar","site-content-layout":"page-builder","ast-global-header-display":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"disabled","ast-breadcrumbs-content":"","ast-featured-img":"disabled","footer-sml-layout":"","theme-transparent-header-meta":"enabled","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":""},"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v20.1 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Publications - CADSL | EE | IITB<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.ee.iitb.ac.in\/~cadsl\/publications\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Publications - CADSL | EE | IITB\" \/>\n<meta property=\"og:description\" content=\"Publications Journal \/ Conference \/ Workshop 2021 Jaynarayan Tudu, Satyadev Ahlawat, Sonali Shukla, and Virendra Singh, `A framework for configurable for joint-scan design-for-test architecture`, Journal of Electronic Testing: Theory and Application (JETTA), 2021 Abhinish Anand, Winnie Thomas, Suryakant Toraskar, and Virendra Singh, `Predictive warp scheduling for efficient execution in GPGPU`, 31st ACM Great Lake Symposium &hellip; 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