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5th IEEE International Workshop on Reliability Aware System Design and Test

(In conjunction with the 27th International Conference on VLSI Design)

IIT Bombay, Mumbai, India January 9-10, 2014





Past Events








Call for Papers (pdf)


Paper Submission

Key Dates


Organizing Committee


Steering Committee


Program Committee


Advance Program




Invited Talks













Submission deadline: 31 October 2013 (Extended)


Keynote/ Invited Talks

Dr. Janusz Rajski, Mentor Graphics, US

Prof. Zebo Peng, Linkoping Univ., Sweden

Prof. Mark Tehranipoor, Univ. of Connecticut, US

Dr. Mahendra Kelkar, NPCL, IN

Prof. Supratik Chakraborty, IITB, IN

Prof. Bernard Menezes, IITB, IN



Even as advances in CMOS technology come up against physical limits of material properties and lithography, raising many new challenges that must be overcome to ensure IC quality and reliability, there appears to be no obvious alternate technology that can replace End-of-Roadmap CMOS over the next decade. However, many reliability challenges from increasing defect rates, manufacturing variations, soft errors, wearout, etc. will need to be addressed by innovative new design and test methodologies if device scaling is to continue on track as per Moore`s Law to 10nm and beyond. The key objective of this annual workshop, planned to be held in conjunction with the International Conference on VLSI Design, is to provide an informal forum for vigorous creative discussion and debate of this area. The aim is to encourage the presentation and discussion of truly innovative and `out-of-the-box` ideas that may not yet have been fully developed for presentation at reviewed conferences to address these challenges. Additionally, the workshop invites embedded talks and tutorials on cutting edge topics related to reliability aware design of CMOS and hybrid nanotechnology systems.

Representative topics include, but are not limited to:


-Design for test,

- Built-in self-test

- ATPG and defect oriented test

- Delay test

- Low power test

- Instruction-based self-test

- On-line test methodology

- Reliability of CMOS circuits

- Self checker circuits

- Self diagnosis methods

- Fault tolerant micro-architecture

- Self-healing system design

- Energy and performance aware fault tolerant micro-architectures

- Device degradation and mitigation

- System validation methodology

- Secure system design

- Design for reliability, dependability, and verifiability

Submissions: Authors are invited to submit previously unpublished technical proposals. The proposals must be full papers not to exceed 6 pages. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and 4 to 6 keywords.  Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address. Submit a copy of your proposal in PDF either online submission or via e-mail to:


Key Dates:

Paper Submission: October 31, 2013 (EXTENDED)

Acceptance Notification: November 10, 2013

Final Paper Due: December 10, 2013

Presentation Due: Jan 1, 2014




General Information


Adit Singh

Auburn University, Auburn, USA


Tel: +1.334.644.1647

Fax: +1.334.844.1809


Virendra Singh

Indian Institute of Technology Bombay


Tel: +91.22.2576.9432

Fax: +91.22.2572.3707



Program Related Information


Erik Larsson

Lund University, Sweden


Tel: +46.709.656619



Rubin Parekhji

Texas Instruments, Bangalore, India



Organizing Committee

General Co-Chairs

Adit Singh (Auburn U., US)

Virendra Singh (IIT-B, IN)

General Vice Co-Chairs

Michiko Inoue (NAIST, JP)

Sreejit Chakravarty (LSI, US)

Program Co-Chairs

Erik Larsson (Lund U. SE)

Rubin Parekhji (TI, IN)

Program Vice Co-Chairs

Ilia Polian (Passau U., DE)

MS Gaur (MNIT, IN)

Organizing Committee Co-Chairs

Bhargab Bhattacharya (ISI, IN)

V. Kamakoti (IITM, IN)

Publication Chair

Vijay Laxmi (MNIT, IN)

Finance Co-Chairs

Pradip Thaker (Maxim, IN)

S. Ramakrishnan (WT, IN)

Publicity Co-Chairs

Susanta Chakravarty (BESU, IN)

Chia Yee Ooi (UTM, MY)

Local Arrangement chair


Website management chair

Sushil Kabra (BSNL, IN)

Registration Chair

Jaynarayan Tudu (IISc, IN)


Steering Committee

Kewal K. Saluja (US) - Chair

Jacob A. Abraham (US)

Vishwani D. Agrawal (US)

Bashir Al-Hashimi (UK)

Bernd Becker (DE)

Abhijit Chatterjee (US)

Hideo Fujiwara (JP)

Masahiro Fujita (JP)

Erik Larsson (SE)

Rubin Parekhji (IN)

Sudhakar M. Reddy (US)

Adit D. Singh (US)

Virendra Singh (IN)


Program Committee