SEQUEL is a general-purpose circuit simulation package developed at IIT Bombay. Its GUI includes a schematic editor for entering the circuit diagram and a graphing utility for viewing the simulation results. Several simulation examples in electronics and power electronics, which are particularly useful for teaching engineering courses, are included in the package.


SEQUEL examples
Note: The documentation files included at the above link are also available in the SEQUEL distribution for linux/windows. There is no need to download them separately.

Using SEQUEL for course work

A large number of ready-made simulation examples are made available with the SEQUEL distribution. These examples can be used in courses on electronics and power electronics in a variety of ways:

Video tutorials: (download and view with VLC media player)

Instructions for running SEQUEL (Windows)

Instructions for running SEQUEL (Linux)

Simulation workshops for teaching electronics
Simulation offers an excellent means to improve one's understading of circuits. A few workshops on "Use of simulation in teaching electronics" will be conducted at IIT Bombay. The schedule can be found here.

course material: slides/notes/animations

Related Publications
  1. "Simulation of Power Electronic Circuits," by M.B. Patil, V. Ramanarayanan, V.T. Ranganathan, Narosa, 2009.
  2. Errata for the above book.
  3. M. B. Patil, "A public-domain program for mixed-signal simulation," IEEE Trans. Education, pp. 187-193, May 2002.
  4. M. B. Patil, S. P. Das, A. Joshi, and M. C. Chandorkar, "A new public-domain simulator for power electronics circuits," IEEE Trans. Education, vol. 45, pp. 79-85, Feb. 2002.
  5. D. Vinay Kumar, R. A. Thakker, M. B. Patil, and V. R. Rao, "Simulation study of non quasi static behaviour of MOS transistors," Proc. 5th Intl. Conf. on Modeling and Simulation of Microsystems, San Juan, Peurto Rico, April 22, 2002. This describes how SEQUEL can be used for "look-up table"-based simulation of submicron MOS transistors.
  6. M. B. Patil, M. C. Chandorkar, B. G. Fernandes, and K. Chatterjee, "Computation of steady-state response in power electronic circuits," IETE J. Research, vol. 48, no. 6, pp. 471-477, Nov. 2002.
  7. Dennis Sasikumar, R. Manchanda, and M. B. Patil, "The role of dendritic spines in EPSP amplification: a computational pilot study using a novel simulation platform," Int. Symp. Neuroscience, Manesar, India, Dec 15-17, 2003. (awarded the best poster prize in the Computational Neuroscience section)
  8. D. Vinay Kumar, K. Narasimhulu, M. Shojaei-Baghini, D. K. Sharma, M. B. Patil, and V. R. Rao, "Evaluation of the impact of layout on device and analog circuit performance with LAC MOSFETs," IEEE Trans. Electron Devices, vol. 52, pp. 1603-1609, 2005.
  9. S. N. Agarwal, A. Jha, D. Vinay Kumar, J. Vasi, M. B. Patil, and S. C. Rustagi, "Look-up table approach for RF circuit simulation using a novel measurement technique," IEEE Trans. Electron Devices, vol. 52, pp. 973-979, 2005.
  10. B. P. Harish, N. Bhat, and M. B. Patil, "Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multile processes," Solid-State Electron., vol. 50, pp. 1252-1260, 2006.
  11. B. P. Harish, N. Bhat, and M. B. Patil, "On a generalized framework for modeling the effects of process variations on circuit delay performance using response surface methodology," IEEE Trans. CAD, vol. 26, pp. 606-614, 2007.
  12. R. R. Sawant and M. C. Chandorkar, "Methods for multi-functional converter control in three-phase four-wire systems," IET Power Electronics, vol. 2, issue 1, pp. 52-66, Jan. 2009.
  13. R. R. Sawant and M. C. Chandorkar, "A Multifunctional Four-Leg Grid-Connected Compensator," IEEE Trans. Industry Applications, vol. 45, pp. 245-259, 2009.
  14. R. A. Thakker, C. Sathe, A. B. Sachid, M. S. Baghini, V. R. Rao, and M. B. Patil, "Automated Design and Optimization of Circuits in Emerging Technologies," Proc. 14th Asia and South Pacific Design Automation Conf., Yokohoma, January 19-22, 2009.
  15. R. A. Thakker, C. Sathe, A. B. Sachid, M. S. Baghini, V. R. Rao, and M. B. Patil, "A Novel Table-based approach for Design of FinFET Circuits ," IEEE Trans. CAD, pp. 1061-1070, July 2009.