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\title[Current Mode Interconnect]
{Current Mode Interconnect}

%\subtitle
%{Include Only If Paper Has a Subtitle}

\author[Marshnil Dave, Supreet Joshi, Dinesh Sharma]
{Marshnil Dave, Supreet Joshi, Dinesh Sharma}
\institute[Department Of Electrical Engineering, IIT Bombay]
{
Department Of Electrical Engineering\\
Indian Institute Of Technology, Bombay
}
\date[\today] % (optional, should be abbreviation of conference name)
{\today}
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\begin{document}

\begin{frame}
  \titlepage
\end{frame}

\section{Scaling}
\begin{frame}
  \frametitle{Scaling}
\begin{itemize}
\item To increase packing density,
we would like to reduce the size of transistors and passive components.
\item In order to decrease lateral sizes, we have to reduce vertical sizes too.
\item If dimensions are scaled down, voltages must also be reduced
to avoid breakdown.
\end{itemize}
This is known as constant field scaling. \vspace{1em}\\
So what price do we have to pay to get denser, more complex circuits?
\end{frame}

\begin{frame}
\frametitle{MOS model}
\begin{columns}
\column{4cm}
\includegraphics[width=4cm]{./Images/mos-model0.eps}
\[ K \equiv \mu C_{ox} \frac{W}{L} \]
\[ C_{ox} \equiv \frac{\epsilon_{ox}}{t_{ox}} \]
\column{8cm}
\begin{itemize}
\item For $V_{gs} \le V_T$,\hspace{0.5em}\\
\( I_{ds} =  0 \) \vspace{1em}\\
\item For $V_{gs} > V_T$ and $V_{ds} \le V_{gs} - V_T$,\hspace{0.5em}\\
$ I_{ds} = K \left[(V_{gs}-V_T) V_{ds} - \frac{1}{2} V_{ds} ^2 \right] $
\vspace{1em}\\
\item For $V_{gs} > V_T$ and $V_{ds} > V_{gs} - V_T$, \hspace{0.5em}\\
$ I_{ds} = \frac{K}{2} (V_{gs} - V_T)^2$\\
\end{itemize}
\end{columns}
(Gate capacitance $C_{ox}$ is {\em per unit area})
\end{frame}
\begin{frame}
  \frametitle{Consequences of Scaling}
All dimensions and voltages divided by the factor S($>1$).\\
\(\begin{array}{|l|l|l|} \hline
\mbox{Device area} & \propto W \times L: (\downarrow S)(\downarrow S) &
\downarrow S^2\\ \hline
C_{ox} & \epsilon_{ox}/t_{ox}:\mbox{const}/(\downarrow S) &
\uparrow S \\ \hline
C_{total} & \epsilon A/t: (\downarrow S^2)/(\downarrow S) &
\downarrow S\\ \hline
V_{DS}, V_{GS}, V_T & \mbox{Voltages}:(\downarrow S) & \downarrow S \\ \hline
I_d & \mu C_{ox}(W/L)(\propto V^2): & \\
    & (\uparrow S)(\mbox{const})(\downarrow S^2) &
\downarrow S\\ \hline
\mbox{Slew Rate } \frac{dV}{dt} &
I/C_{total}: (\downarrow S)/(\downarrow S) &
 const.\\ \hline
\mbox{Delay} & V/\frac{dV}{dt}:(\downarrow S)/(const) & \downarrow S\\ \hline
\mbox{Static Power} & V \times I : (\downarrow S)(\downarrow S) &
\downarrow S^2\\ \hline
\mbox{dynamic power}&C_{total}V^2f :
(\downarrow S)(\downarrow S^2)(\uparrow S) & \downarrow S^2\\ \hline
\mbox{Power delay product} & \mbox {delay} \times \mbox{power}
(\downarrow S)(\downarrow S^2) & \downarrow S^3\\ \hline
\mbox{Power density} & \mbox{power}/\mbox{area}: (\downarrow S^2)/(\downarrow S^2) &
const.\\ \hline
\end{array}
\)
\end{frame}
\begin{frame}
  \frametitle{Impact of scaling}
  \begin{itemize}
  \item Improved packing density: $\uparrow S^2$
  \item Improved speed: delay $\downarrow S$
  \item Improved power consumption: $\downarrow S^2$
  \end{itemize}
However \ldots \\
The above improvements apply to active circuits.
\vspace{1em}\\
What about passive components?
\vspace{1em}\\
Also, reduced voltages imply a lower signal to noise ratio.
\end{frame}

\begin{frame}
  \frametitle{Concern: Interconnect Delay}
  \begin{columns}
  \column{4cm}
  \includegraphics[width=4cm]{./Images/wire.eps}
  \column{8cm}
  \[R = \rho \frac{L}{W t_m},
\mbox{\hspace{2em}} C = \epsilon \frac{L W}{t_i} \]
  \[\mbox{Charge Time }\approx R C  = \rho \epsilon \frac{L^2}{t_m t_i} \]
  \end{columns}
\begin{itemize}
\item Delay is independent of W.
This is because increasing W reduces resistance but increses capacitance
in the same ratio.
\item Unfortunately W is the only parameter that the circuit designer can decide!
(L is fixed by the distance between the points to be connected,
$\rho, \epsilon$, \xx{t}{m} and \xx{t}{i} are decided by the technology).
\end{itemize}
\end{frame}

\begin{frame}
  \frametitle{Concern: Interconnect Delay}
  \begin{columns}
  \column{4cm}
  \includegraphics[width=4cm]{./Images/histo-length.eps}
  \column{8cm}
\begin{itemize}
\item Local interconnects scale with device size.
\item Global interconnects scale with die size.
\end{itemize}
  \end{columns}
\vspace{1ex}
Interconnect Delay = $\frac{\rho \epsilon}{t_m t_i} L^2 = A L^2 $\\
For local interconnects, L scales the same way as $t_m, t_i$,\\
so delay is invariant. \vspace{1ex}\\
For Global Interconnects, L goes {\em up} with die size,
while $t_m$ and $t_i$ scale down.
This leads to a sharp increase in delay.
\end{frame}

\begin{frame}
\frametitle{Buffer Insertion}
Global Interconnect delay can be the determining factor
for the speed of an integrated system.
\vspace{1em} \\
The $L^2$ dependence of interconnect delay is a source of particular concern.
\vspace{1em} \\
This problem can be somewhat mitigated by buffer insertion
in long wires.
\vspace{1em} \\
We define some critical wire length and when a wire segment exceeds this length,
we insert a buffer.
\end{frame}

\begin{frame}
\frametitle{Optimal Repeater Insertion}
We know that Wire Delay = $\rho \epsilon \frac{L^2}{t_m t_i}  \simeq A L^2$\\
Suppose we insert a buffer after every wire segment length = L'.\\
\begin{center}
\includegraphics[width=6cm]{./Images/v-buf.eps}
\end{center}
Then Segment wire delay = $A L'^2$.\\
Let buffer delay = $\tau$\\
For a total wire length of L, (assumed to be a multiple of L')\\
let n = L/L'\\
The wire will have n segments, with n-1 buffers.
\end{frame}

\begin{frame}
\frametitle{Optimal Repeater Insertion}
\begin{center}
\includegraphics[width=8cm]{./Images/v-buf-chain.eps}
\end{center}
What is the optimum wire segment length L'?
\[\Delta = nAL'^2 + (n-1) \tau
 = \frac{L}{L'} A L'^2 + (\frac{L}{L'}-1)\tau
 = ALL' + (\frac{L}{L'}-1)\tau \]
Putting the derivative with respect to L' = 0 for optimisation,
\[
AL - \frac{L}{L'^2} \tau = 0, \mbox{  so } A L'^2 = \tau
\]
{\bf L' should be so chosen that the wire segment delay = $\tau$.\\
Total delay is proportional to n and so, is linear in L.}
\end{frame}

\begin{frame}
  \frametitle{Concern: Signal Integrity}
As interconnect wire separation is reduced \ldots
\begin{itemize}
\item There is a serious signal integrity problem because of
electrostatic coupling between long wires.
\item Inter-signal interference can lead to unpredictable
delay variations.
\item Grounded shielding wires must often be inserted to avoid interference.
\item This leads to extra capacitance and $CV^2f$ power loss.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Concern: Timing closure}
\begin{itemize}
\item Global interconnects are placed {\em after}
active circuit design and layout is complete.
\item One has to anticipate the wire length,
and then design the active circuits to meet total delay specifications.
\item If the actual wire length is different from what was anticipated,
one has to re-design the active circuits after layout.
\item After a fresh layout, wire lengths and hence, delays are changed.
\item This leads to a design-layout-redesign iteration known as Timing Closure.
This iteration becomes longer and longer
when total delays are dominated by interconnect delay.
\end{itemize}
\end{frame}

\subsection{Promise of current signaling}
\begin{frame}
  \frametitle{Promise of current signaling}
  \begin{itemize}
  \item Why not signal with current rather than voltage?
  \item Current rise time is limited by inductance rather than capacitance.
Typically, inductive effects are much smaller than capacitive effects.
(After all, $\epsilon \simeq 4, \mu = 1$ for insulators used in IC's).
So electromagnetic coupling is lower than electrostatic coupling.
  \item Signal voltage swings are limited by scaled down supply voltages:
this does not restrict current swings.
  \item In fact, we can use multiple current values to send more than one bit
down the same wire!
\end{itemize}
\end{frame}
\section{A Proposed Solution}
\subsection{A mixed mode circuit for Interconnects}
\begin{frame}
  \frametitle{A mixed mode circuit for Interconnects}
If we hold the Voltage on the interconnect fixed \\
$ \Delta V = 0$, while $\Delta I \neq 0$
$\Rightarrow$ Need low (near 0) input impedance receiver
\begin{itemize}
\uncover<1->{\item No voltage swing on the wire,\\
\hspace*{5em} $\Rightarrow$ {\bf Dynamic power is negligible.}}
\uncover<2->{\item No charging and discharging of interconnect capacitance\\
\hspace*{5em} $\Rightarrow$ {\bf Latency is much lower.}}
\uncover<3->{\item Multiple current levels to transmit bits simultaneously\\
\hspace*{5em} $\Rightarrow$ {\bf Higher Throughput.}\\
\hspace*{5em} $\Rightarrow$ {\bf Lower interconnect area.}}
\uncover<4>{\item
Advantages in Latency, Throughput and Power simultaneously!}
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Operation}
\centering
\includegraphics[width=3.5in, height=1.0in]{./Images/SystemBlock.eps}
\begin{itemize}
\item Four current levels used to signal two bits.
\item Trade off between Signal to Noise Ratio and Power.
\item No changes in rest of system design
\end{itemize}
\end{frame}

\subsection{Circuit Design}
\begin{frame}
\frametitle{Digital Designers need not panic!}
Only the interface works in current mode.
Rest of the circuit is traditional.\\

Two voltage encoded bits from the circuit
are converted to four current levels
by a fast current mode DAC.
\vspace{0.5em}\\

To put this plan into action, we need a receiver with zero input impedance.
\vspace{0.5em}\\

(If inductive effects are to be taken into account,
we would like to terminate the line into its characteristic impedance.)
\vspace{0.5em}\\

\end{frame}
\begin{frame}
\frametitle{Zero input impedance circuit}
Low $r_{in}$ amps are used for photo-detectors.
{(\small C.-K. Kim et al,
``High Injection Efficiency Readout Circuit for Low Resistance Infrared Detector'',
IEE Electronic Letters, 35, 1507, 1999).}
\begin{columns}
\column{4cm}
\includegraphics[width=4cm]{./Images/beta-mult.eps}
\column{8cm}
$
\begin{array}{lclcl}
i_1 & = & g_{mn1}v_1 & = & g_{mp1}(v - v_2)\\
i_2 & = & g_{mn2}v_1 & = & - g_{mp2} v_2\\
v_2 & = & -\frac{g_{mn2}}{g_{mp2}} v_1 &
= & -\frac{g_{mn2}}{g_{mp2}} \frac{i_1}{g_{mn1}}\\
\end{array}
$
\[ i_1 = g_{mp1} v + \frac{g_{mn2}/g_{mn1}}{g_{mp2}/g_{mp1}} i_1\]
\end{columns}
\[\mbox{define } \Gamma \equiv \frac{g_{mn2}/g_{mn1}}{g_{mp2}/g_{mp1}}
\mbox{\hspace{3em} then, } i_1 (1 - \Gamma) = g_{mp1} v\]
\[\mbox{This gives  } r_{in} = (1 - \Gamma)/g_{mp1} \]
\end{frame}

\begin{frame}
  \frametitle{Robustness of design}
In saturation,
\[ I_d = \frac{1}{2} \mu C_{ox}\frac{W}{L} (V_g - V_T)^2 \]
\[\mbox{So, } g_m = \mu C_{ox}\frac{W}{L} (V_g - V_T) =
\sqrt{2 \mu C_{ox}\frac{W}{L} I_d} \]
\[g_{mn2}/g_{mn1} = \sqrt{\frac{(W/L)_{n2}}{(W/L)_{n1}} \frac{I_2}{I_1}}\]
\[g_{mp2}/g_{mp1} = \sqrt{\frac{(W/L)_{p2}}{(W/L)_{p1}} \frac{I_2}{I_1}}\]
\[\mbox{Therefore } \Gamma \equiv \frac{g_{mn2}/g_{mn1}}{g_{mp2}/g_{mp1}}
= \sqrt{\frac{(W/L)_{n2}/(W/L)_{n1}}{(W/L)_{p2}/(W/L)_{p1}} }\]
\end{frame}

\begin{frame}
  \frametitle{Receiver Design - Input stage}
  \begin{figure}
  \centering
  \includegraphics[width=6cm]{./Images/Impedance.eps}
  \end{figure}

  \begin{itemize}
	\item Input resistance controlled by geometry of transistors	
  	\item Interconnect voltage held fixed 
	\item Input resistance insensitive to process variations
	\end{itemize}
		
\end{frame}

\begin{frame}
\frametitle{receiver using Current comparators}
	\begin{columns}
	\column{6cm}
  	\includegraphics[width=6cm]{./Images/Comparator.eps}
	
	\column{6cm}
	\begin{itemize}
  	\item
$I_{T1}= k_1\cdot I_{int}$; $I_{T2}= k_2\cdot I_{int}$; $I_{T3}= k_3\cdot I_{int}$ 
    \begin{center}
    \begin{tabular}{|c|c|c|c|}
    \hline
    Current & O1 & O2 & O3\\
    \hline
    0 & 1 & 1 & 1\\
    \hline
    I & 0 & 1 & 1\\
    \hline
    2I & 0 & 0 & 1\\
    \hline
    3I & 0 & 0 & 0\\
    \hline
    \end{tabular}
    \end{center}

	\item
$0 < I_{ref} < k_{1}I$; $k_{2}I < I_{ref} < 2k_{2}I$; $2k_{3}I < I_{ref} < 3k_{3}I$
	 
  	\end{itemize}
	\end{columns}
\end{frame}

\begin{frame}
	\frametitle{Decoder Circuit}
	\begin{columns}
	\column{6cm}
	\hspace{1cm}
	\includegraphics[width=4cm]{./Images/Dec_rx0.eps}
	\column{6cm}
	$ Rx1 = O2 $\\
	$ Rx0 = O3 \cdot  (O1 + O2) $
	\end{columns}
\vspace{1em}
This circuit may produce glitches if comparators don't settle simultaneously.
\end{frame}

\begin{frame}
\frametitle{A to D based receiver}
\begin{columns}
\column{6cm}
        \includegraphics[width=6cm]{./Images/CMRx.eps}
\vspace{1em}\\
\column{6cm}
Mp15 and Mn15 form the comparator which determines the MSB.
When MSB = `1', $2I_0$ flows through Mp20 and Mpsw.
\end{columns}
The interconnect current is mirrored in Mn20.\\
Hence, the residual current $I_{int} - 2I_0$
flows through the transistors Mpx1 and Mpx2.\\
This residual current is mirrored in Mp05.
\end{frame}

\begin{frame}
\frametitle{A to D based receiver}
\begin{columns}
\column{6cm}
        \centering
        \includegraphics[width=6cm]{./Images/CMRx.eps}
\vspace{1em}\\
\column{6cm}
The residual current is mirrored in Mp05
for comparison with $0.5 I_0$ (carried by Mn05).\\
This determines Rx0 (LSB).
\end{columns}
When MSB is `0', no current flows through Mp20-Mpsw branch and
the entire interconnect current is replicated in Mp05 for comparison.
\vspace{1em}\\
This A-to-D style receiver can be designed to be glitch free.
\end{frame}

\begin{frame}
  \frametitle{Current Steering Transmitter}
  \begin{columns}
  \column{6cm}
  \includegraphics[width=6cm]{./Images/tx-steer.eps}
  \column{6cm}
  \begin{itemize}
  \item Essentially a 2bit current mode D to A.
  \item b0 controls the steering of current $I_0$
into the wire or into the ground.
  \item Similarly b1 steers $2I_0$ into the wire or into the ground.
  \item Consumes a constant current of $3I_0$.
  \end{itemize}
  \end{columns}
\vspace{1em} Current steering is fast. (Like an ECL circuit).
\end{frame}

\begin{frame}
  \frametitle{Current Switching Transmitter}
\begin{columns}
\column{4cm}
  \includegraphics[width=4cm]{./Images/tx-switch.eps} 
\column{8cm}
This design is marginally slower - but consumes less power.\vspace{1em}\\
Average current = $\frac{0+1+2+3}{4}I_0 = \frac{3}{2}I_0$
\end{columns}
\end{frame}

\subsection{Performance Analysis }
\begin{frame}
  \frametitle{power modeling}
\begin{eqnarray*}
R_0 &\equiv& \mbox{Resistance of the wire per unit length}\\
C_0&\equiv& \mbox{Capacitance per unit length.}\\
L & \equiv& \mbox{length of the wire.}\\
R_{int} &\equiv & \mbox{Total wire Resistance}  = R_0 L\\
C_{int} &\equiv & \mbox{Total wire Capacitance}  = C_0 L\\
\end{eqnarray*}
\end{frame}

\begin{frame}
\frametitle{Power dissipation in the transmitter}
\begin{columns}
\column{6cm}
\begin{center}
  \includegraphics[width=4cm]{./Images/tx-steer.eps}
\end{center}
Current steering transmitter consumes $3V_{dd}.I_0$.
This is inclusive of the static and dynamic power in the wire
as well as in the left half of input receiver.\\

\column{6cm}
\begin{center}
  \includegraphics[width=4cm]{./Images/tx-switch.eps} 
\end{center}
Current switching transmitter consumes $\frac{3}{2}V_{dd}.I_0$
inclusive of the static and dynamic power in the wire
as well as in the left half of input receiver.
\end{columns}
\end{frame}
\begin{frame}
\frametitle{Static power dissipation in the wire}
  \begin{columns}
  \column{4cm}
  \includegraphics[width=4cm]{./Images/line-model.eps}
  \column{8cm}
\begin{itemize}
\item
The static power is given by $R_{int} I^2$.
\item
If all logic states are equally likely,\\
Average $I^2$ =
$\frac{0^2 + 1^2 + 2^2 + 3^2}{4} I_0^2 = \frac{7}{2} I_0^2$\\
where $I_0$ is the unit current step.
\end{itemize}
  \end{columns}
\vspace{1em}Therefore the static power dissipation is
\[P_{static} = \frac{7}{2} R_{int}I_0^2 = \frac{7}{2} L R_0 I_0^2 \]
\end{frame}

\begin{frame}
\frametitle{Beta multiplier Power Dissipation}
\begin{columns}
\column{4cm}
\includegraphics[width=4cm]{./Images/Impedance.eps}
\column{8cm}
The left arm of the beta-multiplier (Mp1-Mn1)
has already been accounted for in the transmitter power loss.\\
\end{columns}
The right arm carries a current $I_{int}$ (the wire current),
whose average value is $1.5I_0$.\\
Also the generation of the reference voltage at source of Mp2
requires an additional current of $I_{ref}$\\
Hence, the power loss in the beta multiplier is :
\[V_{dd}\cdot(1.5I_{0} + I_{ref})\]
\end{frame}

\begin{frame}
\frametitle{Current comparator decoder}
Comparators carry the smaller of the currents being compared.
\begin{columns}
\column{4cm}
\includegraphics[width=4cm]{./Images/Comparator.eps}
\column{8cm}
\begin{itemize}
\item Wire current = $3I_0$:\\
Comparators currents are:\\
$0.5I_0$, $1.5I_0$ and $2.5I_0$.\\
Power loss = $V_{dd}\cdot4.5I_0$.
        \item Wire current = $2I_0$:\\
Comparator currents are:\\
$0.5I_0$, $1.5I_0$ and $2I_0$.\\
Power loss = $V_{dd}\cdot4I_0$.
\end{itemize}
\end{columns}
\end{frame}
\begin{frame}
\frametitle{Current comparator decoder}
Comparators carry the smaller of the currents being compared.
\begin{columns}
\column{4cm}
\includegraphics[width=4cm]{./Images/Comparator.eps}
\column{8cm}
        \begin{itemize}
        \item Wire current = $I_0$:\\
Comparators currents are:\\
$0.5I_0$, $I_0$ and $I_0$.\\
Power loss = $V_{dd}\cdot2.5I_0$.
        \item Wire current = $0$:\\
No current flows in any comparator.\\
Hence, there is no static power loss.
        \end{itemize}
\end{columns}
\end{frame}
\begin{frame}
\frametitle{Current comparator decoder}
The average power consumption (assuming equal likelihood of all states)
is given by
\[ \frac{4.5 + 4 + 2.5 + 0}{4} I_0 \cdot V_{dd} = 2.75I_0\cdot V_{dd} \]

The decoder following this current comparator
does not consume any static power loss, being a digital CMOS circuit.

\end{frame}

\begin{frame}
\frametitle{A to D type decoder}
\begin{center}
\includegraphics[height=4cm]{./Images/CMRx.eps}
\end{center}
Mn20 always carries $I_{int}$\\

The power loss in residue generating section
(Mp20, Mpsw, Mpx1, Mpx2 and Mn20)
is always $I_{int}\cdot V_{dd}$.\\
\end{frame}
\begin{frame}
\frametitle{A to D type decoder}
\begin{columns}
\column{6cm}
\includegraphics[width=6cm]{./Images/CMRx.eps}
\vspace{1em}\\
\column{6cm}
\begin{itemize}
\item Wire current = $3I_0$\\
Comparators:$1.5I_0$ and $0.5I_0$.\\
Residue generator: $3I_0$\\
Total power = $5I_0\cdot V_{dd}$.
\item Wire current = $2I_0$ :\\
Comparators: $1.5I_0$ and $0$.\\
Residue generator: $2I_0\cdot V_{dd}$.\\
Total power = $3.5I_0\cdot V_{dd}$.
\end{itemize}
\end{columns}
\end{frame}

\begin{frame}
\frametitle{A to D type decoder}
\begin{columns}
\column{6cm}
        \includegraphics[width=6cm]{./Images/CMRx.eps}
\vspace{1em}\\
\column{6cm}
\begin{itemize}
\item Wire current = $I_0$ :\\
Comparators: $I_0$ and $0.5I_0$.\\
Residue generator: $I_0\cdot V_{dd}$\\
Total power = $2.5I_0\cdot V_{dd}$.
\item Wire current = $0$ :\\
no current flows anywhere and hence there is no static power loss.\\
\end{itemize}
\end{columns}
\vspace{1em}
 Assuming equal likelihood of all states,
the average power consumption is
$2.75 I_0\cdot V_{dd}$.
\end{frame}
\begin{frame}
\frametitle{Comparison of the two receivers}
\begin{itemize}
\item The average power consumption of both circuits is identical,
\item In the worst case, the A to D type receiver consumes more power
than the standard receiver.
\item However,  the A to D type receiver offers advantages in speed
and eliminates the possibility of glitches in the output.
\end{itemize}
\end{frame}
\begin{frame}
\frametitle{Summary of Power Analysis}
\begin{itemize}
\item
The static power in the circuits dominates
over the power dissipation in the wire.
\item The power consumption of the system
is independent of the wire length.
\item This is because the power consumed in the wire
is always supplied by the transmitter - which depends only on Io.
\item Therefore, the power consumed by
the transmitter circuit + wire + left arm of the beta multiplier
is independent of the wire length.
\end{itemize}
\end{frame}
\begin{frame}
\frametitle{Summary of Power Analysis}
The wire length limit of operation of this system
arises from the current drawn by the wire capacitance
and the transmitter-end voltage.
\begin{itemize}
\item
If the wire length is high enough
such that the wire capacitance sinks current more than $0.5I_0$,
then the current reaching the beta-multiplier will reduce
by half the unit current level,
which can lead to (transient) incorrect decoding.
\item
If the wire is so long that the transmitter-end voltage,
$V_{dd} + I_{int}\cdot R_{int}$,
rises sufficiently for the transmitter transistors to go out of saturation,
then the transmitter will be unable to drive the required current into the wire.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Speed Analysis}
Latency:
\begin{itemize}
\item Current switching at transmitter is faster.
\item Wire delay is lower
due to negligible voltage swings on the interconnect.
\item However, the receiver may be slower due to
\begin{itemize}
\item Beta multiplier turning off at zero current.
\item Slow current comparison
\end{itemize}
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Beta-Multiplier with Trickle Current}
\begin{columns}
\column{3cm}
\includegraphics[width=3cm]{./Images/beta-mult.eps}
\column{9cm}
For input current of 0,
the beta multiplier will turn off completely.
For subsequent input transitions,
the beta multiplier needs to be turned on.
\end{columns}
\begin{columns}
\column{3cm}
\includegraphics[width=3cm]{./Images/trickle.eps}
\column{9cm}
Turn on delay can be avoided by adding a trickle current.
The trickle current is added to the interface current. \vspace{1ex}\\
Trickle current of $40\mu A$ to $80\mu A$ has been used in the design. 
\end{columns}
\end{frame}

\begin{frame}
\frametitle{Current Comparators}
\begin{columns}
\column{4cm}
\includegraphics[width=4cm]{./Images/Current-Comparison.eps}
\column{8cm}
Current mode receivers use current comparators to produce
a voltage mode digital output.
\vspace{1ex}\\
The load capacitance is charged by the difference current.
\end{columns}
\begin{itemize}
\item These comparators have a `dead spot'
when the two currents are exactly equal.
\item If the currents are {\em nearly} equal,
the comparators are extremely slow.
\item This has a bearing on deciding the current separation
between differnt levels, as the nominal current difference
between \xx{I}{ref} and \xx{I}{int} is $\frac{\Delta I}{2}$.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Current Comparators}
Current comparators can be speeded up by limiting
the voltage swing required at their output.\\
\centering
\includegraphics[width=3cm]{./Images/cc-src-follow.eps}\\
\begin{itemize}
\item The source follower stage restricts the output
beyond a swing of \xx{V}{Tn} above and \xx{V}{Tp} below
the resting voltage.
\item It does have a dead band near zero difference current.
\item Also, the inverter amplifier consumes static power. 
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Current Comparators}
\begin{columns}
\column{4cm}
\includegraphics[width=4cm]{./Images/cc-fb.eps}
\column{8cm}
The circuit here uses an inverter with resistive feedback
to amplify the small swing at A.
\end{columns}
\begin{itemize}
\item
the Value of Rf is critical for fast operation of the circuit.
\item Large Rf reduces voltage swing at node A
but the reduced output voltage swing
causes static power dissipation in the subsequent inverter. 
\item Rf is implemented using a transmission gate circuit. 
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Speed Analysis: Throughput}
\begin{itemize}
\item Throughput is inversely proportional to variation in delay
\item There is Lower delay variation in current mode.
\item Also, in multi bit current mode systems,
2 bits can be sent per wire $\Rightarrow$ Higher Throughput
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Simulation Results: Current Comparators}
\centering
\begin{tabular}{|c|c|c|c|c|} \hline
$I_{ref}-I_{in}$ & \multicolumn{2}{|c|}{Neg.Feedback Amplifer}&
\multicolumn{2}{|c|}{Low Op. Impedance}\\
\cline{1-5}($\mu A$ )&Rise&Fall&Rise&Fall\\ \hline
40 & 251 &239 &439&387\\
50 & 252 &240 &395&349\\
60 & 255 &243 &364&320\\
80 & 267 &252 &320&284\\
100 & 279 &261 &291&259\\
120 & 288 &268 &270&241\\ \hline
\end{tabular}
\end{frame}

\begin{frame}
\frametitle{Simulation Results: Current Comparators}
\centering
\begin{tabular}{|c|c|c|} \hline
$I_{in}$ &  Neg.Feedback Amplifer($\mu W$) &  Circuit A ($\mu W$) \\ \hline
$0$   & $266.4$ & $312.8$ \\
$I_{0}$   & $339.8$ & $349.74$ \\
$2I_{0}$   & $372.6$ & $395.64$ \\
$3I_{0}$   & $371.9 $ & $458.58$ \\ \hline
\end{tabular}
\begin{itemize}
\item $R_{f} = 35K$ and around $I_{ref}=160\mu A$
 \item Power consumption in circuit A is large.
Hence, we chose current comparators with negative feeck amplifier. 
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Simulation Results: Multi-level Current Mode Signaling}
\begin{itemize}
\item CVCS scheme for two bits per line (N=2)
was designed for $I_{0}=80\mu A$ and $I_{trickle}=60 \mu A$
\item CVCS scheme for N=1
was designed with $I_{0}=40\mu A$ and $I_{trickle}=40 \mu A$
\end{itemize}
\begin{center}
\begin{tabular}{|c|c|c|c|} \hline
{Parameters} & \multicolumn{2}{c|}{CVCS with} & Voltage\\ \cline{2-3}
 & N=1 & N=2 & Mode\\ \hline
Avg Delay (ns)& 0.786 & 0.9  & 0.862\\ \hline
Throughput & 1Gbps & 1Gbps & 1Gbps\\ \hline
Power (mW) & 8.896 &20.704 &118.152\\ \hline
Area ${\mu m}^2$&  870.4   &758.16 &18560\\ \hline
Wires (16bit bus)  &16 &8&16\\ \hline
\end{tabular}
\end{center}
\end{frame}

\begin{frame}
\frametitle{Simulation Results: Multi-level Current Mode Signaling}
\begin{center}
\includegraphics[height=4cm]{./Images/3Energy.eps}
\end{center}
\end{frame}
\end{document}
