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\title[Current Mode Interconnect]
{Current Mode Interconnect}

%\subtitle
%{Include Only If Paper Has a Subtitle}

\author[Marshnil Dave, Supreet Joshi, Dinesh Sharma]
{Marshnil Dave, Supreet Joshi, Dinesh Sharma}
\institute[Department Of Electrical Engineering, IIT Bombay]
{
Department Of Electrical Engineering\\
Indian Institute Of Technology, Bombay
}
\date[\today] % (optional, should be abbreviation of conference name)
{\today}
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\newcommand{\bea}{\begin{eqnarray*}}
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\begin{document}

\begin{frame}
  \titlepage
\end{frame}

\section{Driver Circuits with Inductive Peaking}
\subsection{Inductive peaking: Concept}
\begin{frame}
\frametitle{Inductive Peaking for Bandwith Enhancement}
\begin{center}
\includegraphics[width=8cm]{./Images/line_load_rl.eps}
\end{center}
\begin{itemize} 
\item On-chip interconnects can be modeled as distributed RC
which is essentially a low pass filter 
\item Bandwidth Enhancement techniques
employed in on-chip I/O buffers and RF amplifers
can be employed for bandwidth enhancement of interconnects
\end{itemize} 
\end{frame}

\begin{frame}
\frametitle{Inductive Peaking for Bandwith Enhancement}
\includegraphics[width=5cm]{./Images/line_load_rl.eps}
\includegraphics[width=6cm]{./Images/freqresponse_final.ps}
\begin{itemize} 
\item One way of enhancing bandwidth is through Inductive Peaking.
\item Inductive impedance is used as line termination.
\item Output developed across the inductor has a high pass characteristic,
which counters the low pass character of the wire.
\item Shows enhancement of around 500MHz in 3dB bandwidth.
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Bandwidth Enhancement Vs Load Inductance}
\begin{columns}
\column{4cm}
\includegraphics[width=4cm]{./Images/w3dbvsLDiffRl_last_new1.eps}
\column{8cm}
\begin{itemize}
 \item For a given line length,
the amount of bandwidth enhancement is a function
of inductance and load resistance. 
\item Significant bandwidth enhancement can be achieved
for a wide range of inductance values greater than $L_{peak}$.
 \item Required inductance for significant enhancement in bandwidth
is a few hundreds of nano Henries !!
 \item An active inductor is required
\end{itemize}
\end{columns}
\end{frame}	

\begin{frame}
\frametitle{Beta Multiplier: A Gyrator}
Beta Multiplier Circuits can exhibit inductive input impedance
for some frequency range if designed properly.
\begin{columns}
\column{4cm}
\includegraphics[width=4cm]{./Images/beta-mult.eps}
\column{8cm}
A Beta Multiplier is essentially a gyrator circuit
with two Gm elements connected back to back
and parasitic capacitance of the transistors.
\end{columns}
\end{frame}

\begin{frame}
\frametitle{Beta Multiplier: Input Impedance}
\begin{columns}
\column{5cm}
\includegraphics[width=6cm]{./Images/BmulSmallsigmodel_withro_woeqckt.eps}
\column{7cm}
\begin{eqnarray}	
\nonumber
\mbox{Let } \tau_{1}=\frac{C_{g1}}{g_{mn1}} &
\tau_{2}=\frac{C_{g2}}{g_{mp2}} &
R_{1}=\frac{1}{g_{mn1}}\\ \nonumber
\tau_{3}=C_{g3}r_{op1} &
\tau_{4}=\frac{C_{g3}}{g_{mp1}} &
R_{3}=r_{op1} \\ \nonumber
\gamma=\frac{g_{mp1}/g_{mp2}}{g_{mn1}/g_{mn2}} & &
\frac{R_{1}}{R_{3}}=k\\ \nonumber
\end{eqnarray}
\end{columns}
\vspace{-2em}
\[ Z_{in} = \frac{\lbrace{ (\tau_{1}\tau_{2}+k\tau_{2}\tau_{3})s^{2}
+(\tau_{1}+\tau_{2}+k(\tau_{3}+\tau_{2}))s +1+k-\gamma \rbrace}}
{\lbrace{(g_{mp1}+\frac{1}{R_{3}})\lbrace(1+\tau_{1}s)
(1+\tau_{2}s)(1+\tau_{4}s)\rbrace}\rbrace}\]
\[
R_{in} = \frac{(1-\gamma)+\frac{1}{g_{mn1}r_{op1}}}{g_{mp1}+\frac{1}{r_{op1}}}
\]
\end{frame}

\begin{frame}
\frametitle{Beta Multiplier : Equivalent Circuit}
\[ Z_{in} = \frac{\lbrace{ (\tau_{1}\tau_{2}+k\tau_{2}\tau_{3})s^{2}
+(\tau_{1}+\tau_{2}+k(\tau_{3}+\tau_{2}))s +1+k-\gamma \rbrace}}
{\lbrace{(g_{mp1}+\frac{1}{R_{3}})\lbrace(1+\tau_{1}s)
(1+\tau_{2}s)(1+\tau_{4}s)\rbrace}\rbrace}\]
\begin{itemize}
\item Relative location of poles and zeros
determine nature of impedance (inductive of capacitive)
\item If the first zero occurs a decade prior to the first pole,
input impedance is inductive 
\item $\gamma-\frac{1}{g_{mn1}r_{op1}}> 0.9$
and any two time constants being equal ensures
that a zero occurs a decade prior to the first pole
\end{itemize}
\end{frame}

\begin{frame}
\begin{columns}
\column{3cm}
\vspace{2em}\\
\includegraphics[width=3cm]{./Images/Bmul_eqckt.eps}
\column{9cm}
\[ R_{eff} = \frac{(1-\gamma)+\frac{1}
{g_{mn1}r_{op1}}}{g_{mp1}+\frac{1}{r_{op1}}}\]
\[C_{eff} = KC_{gx}\]
\begin{eqnarray}
L_{eff}& = &\frac{r_{op1}}{g_{mp1}r_{op1}+1}
\left\lbrace \frac{C_{g1}}{g_{mn1}}
+ \frac{C_{g2}}{g_{mp2}} \right . \nonumber \\
\nonumber
& & \left . + \frac{C_{g2}}{g_{mp2}g_{mn1}r_{op1}}
+\frac{C_{g3}}{g_{mn1}g_{mp1}r_{op1}}  \right\rbrace \nonumber \\
\end{eqnarray} 
\end{columns}
\end{frame}

\begin{frame}
\frametitle{Beta Multiplier : Input Impedance Control}
\begin{columns}
\column{5cm}
\includegraphics[width=4cm]{./Images/Zinbmulitrickle1.eps}
\column{7cm}
It is possible to generate effective inductance
of hundreds of nano Henries for a practical range
of input current  and transistor geometries using
beta multipliers.
\end{columns}
\begin{itemize}
\item Their effective resistance can be controlled
by ratios of transconductances
while its effective inductance depends
on the absolute value of transconductance.
\item It is possible to control $R_{in}$ and $L_{eff}$
with very little interaction between the two.
\item Inductance changes from 100nH to 980nH
while the value of effective resistance remains
within 12\% of its nominal value
for $20 \mu A$ change in the current. 
\end{itemize}
\end{frame}
\begin{frame}
\frametitle{Current Mode Receiver Circuit with Beta Multiplier}
\begin{columns}
\column{4cm} 
\includegraphics[width=4cm]{./Images/rx_bmul.eps}
\column{8cm}
\begin{itemize}
\item Effective impedance offered by the receiver
is equal to the parallel combination of
impedance offered by individual beta multipliers. 
\item Voltage at node linerx swings around $V_{ref}$.
A small voltage swing on the line
is sensed and amplified by receiver amplifier. 
\end{itemize}
\end{columns}
\end{frame}

\begin{frame}
\frametitle{Current Mode Receiver Circuit with Beta Multiplier}
\begin{columns}
\column{4cm}
\includegraphics[width=4cm]{./Images/rx_bmul.eps}
\column{8cm}
\begin{itemize}
\item $V_{ref}$ is generated by shorting the input and the output
of an inverter, so that the value of $V_{ref}$
is the same as the switching threshold of the receiver amplifier
across all process corners. 
\item $V_{ref}$ generation circuit consumes static power. 
\end{itemize}
\end{columns}
$r_{out}$ of $V_{ref}$ generation circuit
comes in series with beta multiplier $Z_{in}$
and hence, the beta multiplier has to be sized accordingly. 
\end{frame}

\begin{frame}
\frametitle{Current Mode Receiver Circuit: Dynamic Input Impedance}
\begin{columns}
\column{3cm} 
\includegraphics[width=3cm]{./Images/rx_inductive3.eps}
\column{9cm}
\begin{itemize}
\item We would like the receiver circuit to initially offer high impedance
(while the transmitter is charging the line)
and later (in steady state) to offer a small resistance.
\item It is possible to achieve this by using feedback.
\end{itemize}
\end{columns}
\end{frame}

\begin{frame}
\frametitle{Current Mode Receiver Circuit: Dynamic Input Impedance}
\begin{columns}
\column{3cm} 
\includegraphics[width=3cm]{./Images/rx_inductive3.eps}
\column{9cm}
\begin{itemize}
\item In steady state either of the two switches Sn and Sp, is ON.
The state of these switches is controlled by the receiver amplifier.
The state (ON/OFF) of these two switches flips
as voltage on line flips with input transition. 
\item Because of delay through the receiver amplifier,
the interconnect node is a high impedance node during input transition,
enabling faster charging/discharging of line capacitors.  
\end{itemize}
\end{columns}
\end{frame}

\begin{frame}
\frametitle{A Receiver with Source Follower feedback}
\begin{columns}
\column{4cm}
\includegraphics[width=4cm]{./Images/rx_src_follow.eps}
\column{8cm}
Feedback is enabled when the output of the first inverter
changes by more than \xx{V}{Tp} or \xx{V}{Tn},
turning on either the n or the p source follower.
\end{columns}
\begin{itemize}
\item Feedback prevents any further change in the line voltage.
\item The receiver circuit will cause somewhat higher
voltage swing on line because of non-zero $V_{sb}$ of transistor Mn1.
\item The operating points of source follower
and receiver amplifier may not be same under all process corners. 
\end{itemize}
\end{frame}


\begin{frame}
\frametitle{A Current Mode Receiver with Dynamic Input Impedance}
\begin{columns}
\column{6cm}
\includegraphics[width=6cm]{./Images/rx_katoch.eps}
\column{6cm}
In this receiver proposed by Katoch {\em et al},
either Mp1 or Mn1 is ON in steady state.
\end{columns}
\begin{itemize}
\item The arm with the ON transistor consumes static power.
\item It offers very low input impedance.
\item If higher input impedance is required,
long channel transistors must be used,
which increases the delay of the receiver circuit. 
\end{itemize}
\end{frame}

\section{Driver Circuits with Dynamic Overdriving}
\begin{frame}
 \frametitle{Dynamic Overdriving: Concept}
\begin{columns}
\column{9cm} 
\includegraphics[width=6cm]{./Images/DOD_concept1.eps}
\begin{itemize}
\item Dynamic overdriving means
driving an interconnect by large current during input transition
and by small current for the rest of the period. 
\item In frequency domain, DOD means magnifying
high frequency components of input signal.
\end{itemize}
\column{3cm}		
\includegraphics[width=3cm]{./Images/DOD_wave1.eps}
\end{columns}
\end{frame}

\begin{frame}
\frametitle{Dynamic Overdriving Driver Circuits}
\begin{columns}
\column{6cm} 
\includegraphics[width=6cm]{./Images/DOD_K.eps}
\column{6cm} 
In this driver circuit proposed by Katoch {\em et al},
the full swing driver provides large current during input transition.
\end{columns}
\begin{itemize}
\item The full Swing driver is turned off
as soon as line voltage crosses switching threshold of the inverter I1. 
\item Small swing driver either sources or sinks current from the line
depending on the input bit.
\item Input to the feedback inverter is not full swing.
Hence it consumes static power. 
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Dynamic Overdriving Driver Circuits}

\centering
\includegraphics[scale=0.26,trim=0 0 0 0,clip=]{./Images/DOD_fpw_k_and_fpw_kp.eps}
\begin{itemize}
 		
\item In the driver circuit suggested by Tabrizi et. al.
the full swing driver is turned off after a fixed time period
given by delay element. 
\item The driver circuit of Figure C
eliminated the big NAND and NOR
present in the driver proposed by Tabrizi et. al.
\end{itemize}
\end{frame}

\subsection{Simulations Results}

\begin{frame}
\frametitle{Simulation Setup}	
\begin{itemize}
\item Technology $0.18 \mu m$  UMC, $V_{dd}=1.8$
\item All signaling systems are designed
such that they present equal input capacitance
(1$\times$Minimum sized inverter)
and drive the same load of four min sized inverters(FO4). 
\item Interconnects modeled as a 5section RC:
$R_{0}=178\Omega/mm$, $C_{0}=0.192pF/mm$, $L=0.5 nH/mm$
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Comparison of Receiver Circuits: Speed and Power}
\begin{itemize}
\item Receiver circuits are designed for line voltage swing of $50mV$.
The designed source follower receiver offers $65mV$ of voltage swing. 
\item Driver circuit K'Fixedpw-DOD is designed for overdrive current($I_{peak}$) of $200\mu A$. 
\item Power is measured at 1Gbps and delay measured at 100Mbps
\end{itemize}
\begin{tabular}{|c|c|c|c|} \hline
Driver + Receiver & Power & Delay & Throughput\\
 &($\mu W$)&($ns$)&(Gbps)\\ \hline
K'-Fixedpw-DOD + Diode  & $452$ & $ 1.5 $  & $1.0 $\\ \hline
K'-Fixedpw-DOD + Beta Multiplier  & $450 $ & $0.964$  & $1.25 $\\ \hline
K'-Fixedpw-DOD + Katoch & $445$ & $1.19$  & $1.1$\\ \hline
K'-Fixedpw-DOD + SF & $423$ & $1.29$ & $1.15 $ \\ \hline
\end{tabular}
\end{frame}

\begin{frame}
\frametitle{Comparison of Driver Circuit:Power and Delay}
\begin{itemize}
\item All three driver circuits are designed
for the same overdrive current ($I_{peak}=400\mu A$)
and overdrive duration ($t_{p}=130ps$).
\item The designed drivers Fixedpw-DOD and K'-Fixedpw-DOD
employ the same inverter chain(three minimum sized inverters).
\end{itemize}
\centering
\begin{tabular}{|c|c|c|} \hline
Driver & Power($\mu W$) & Driver Delay ($ps$) \\ \hline
K-DOD   & $464$ & $190 $  \\ \hline
Fixedpw-DOD  & $273$ & $156$ \\ \hline
K'-Fixedpw-DOD& $252$ & $152$ \\ \hline
\end{tabular}
\end{frame}

\begin{frame}
\frametitle{Why Process Variation Tolerant}
\begin{itemize}
\item In modern technologies, $3\sigma$ variation in device parameters
is $40\%$ of their nominal value. 
\item Variation in delay of interconnects with buffer insertion scheme
makes timing verification of modern SOCs an iterative task.
\item In an SOC, driver and receiver circuits
of a repeaterless current mode signaling scheme
are very much likely to be at different parts of the chip.
Transistor parameters of driver and receiver may not be identical.
This can degrade throughput or even correctness of data transmission.
\item Hence, a current mode signaling scheme
which is robust against inter-die and intra-die process variations
is required. 
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Parameters Affecting Performance}
The speed of a current mode signaling scheme with dynamic overdriving driver
is a strong function of the following parameters. 		
\begin{description}
\item[a)] Voltage Swing on line ($\Delta V$)
\item[b)] Duration for which strong driver is ON ($t_{p}$)
\item[c)] Current supplied by the strong driver during input transitions ($I_{peak}$)
\end{description}
Variations in any of these three parameters
cause significant variations in the speed of a CMS with dynamic overdriving
\end{frame}

\begin{frame}
\frametitle{Performance of Current Mode Schemes with Process Variation}
\begin{itemize}
\item CMS scheme proposed by Katoch et. al.
performs well across all process corners
when transistor parameters of transmitter and receiver are identical.
Its performance degrades significantly
in the presence of intra-die process variations.
\item CMS scheme proposed by Tabrizi et. al.
is less sensitive to intra-die process variations
but its throughput degrades significantly
in the worst process corner.
\item  The perfomance of this scheme is worst in the skewed corners
where speed of logic circuit doesn't degrade much.
Hence, with this scheme interconnects can become a bottleneck
in the overall speed of the chip. 
\item We have deleloped a new CMS scheme
that performs well under inter-die and intra-die process variations.  
\end{itemize}
\end{frame}

% 
\begin{frame}
\frametitle{Analysis of Existing Current Mode Signaling Schemes}
\begin{columns}
\column{4cm}
\includegraphics[width=4cm]{./Images/DOD_K.eps}
\column{8cm}
\begin{itemize}
\item \textbf{Proposed by Katoch et. al.}:
The driver circuit employs a feedback inverter
which controls turning off of the strong driver.
Receiver employs an inverter as an amplifier
to amplify small voltage swing on the line.
\item Here, steady state voltage swing at receiver end
should be more than the mismatch
between switching threshold($V_{M}$) of the transmitter
and the receiver inverter for faithful reproduction of the signal.
\end{itemize}
\end{columns}
\end{frame}

\begin{frame}
\begin{itemize}
\item Mismatch in $V_{M}$ leads to a large difference
in rise delay and fall delay of the scheme
which leads to degradation in data rate. 
\item In corner based analysis the entire chip is in the same corner.
For identical inverters at transmitter and receiver,
the scheme is very robust against four corner variations.  
\end{itemize}

\end{frame}
% 
\begin{frame}
\frametitle{Analysis of Existing Current Mode Signaling Schemes}
 	
	
	
 	\begin{columns}
 	\column{4cm}
	\includegraphics[width=4cm]{./Images/DOD_fpw.eps}
	\column{8cm}
	\begin{itemize}
	\item Less sensitive to$ V_{M}$ mismatch between driver and receiver inverters
as ON duration of the strong driver is determined by the delay element.
	\item In SS and FF corners, change in $I_{peak}$ is
somewhat compensated by change in ON duration in the opposite direction.
	\end{itemize}
	\end{columns}
\end{frame}

\begin{frame}
\begin{itemize}	
\item In skewed corners, the $I_{peak}$ changes significantly while delay of delay element remains nearly unchanged. 
\item Leads to difference in rise and fall delays which causes degradation in throughput. 
\item In skewed corners, steady state voltage swing on line is also uneven around switching threshold of receiver amplfier. 
\item Performance of this sginaling scheme degrades significantly in the skewed corners where speed of logic circuit does not degrade much. 
\end{itemize}
\end{frame}

\begin{frame}
 \frametitle{Proposed Current Mode Signaling Scheme: Driver Circuit}
	Why not to employ constant current source at driver ? 
	\begin{columns}
 	\column{1.6in}
	\begin{figure}[h]
 		\centering
 		\includegraphics[scale=0.35,trim=0 0 0 0,clip=]{./Images/DOD_bias.eps}
 		%\caption{Dynamic Overdriving Driver: Current and Voltage Waveform}
% 		%\label{DOD_wave}
 	\end{figure}
	\column{3in}
	\begin{itemize}
	\item Duration for which strong driver is ON is controlled by delay element.
	\item $I_{peak}$ and current supplied by weak driver ($I_{static}$) is  controlled by bias voltages Vbp and Vbn. 
	\item In Vbp generation circuit small PMOS transistor acts as process corner sensor and a long channel NMOS transistor which acts as a resistor.
	
	\end{itemize}
	
	\end{columns}
	
	
	\begin{itemize}
	
	 
	 \item The bias voltages Vbp and Vbn are close to Vdd/2 in typical process corner. These bias voltages,Vbp or Vbn, are lower or higher than Vdd/2 based on process corner. 
	 \item In skewed corners change in bias voltage is suffient to keep $I_{peak}$ nearly same. In SS anf FF coners change in $I_{peak}$ is compensated by change in $t_{p}$.
	\end{itemize}
	
	
	
\end{frame}
% 
% 
\begin{frame}
 \frametitle{Proposed Current Mode Signaling Scheme: Receiver Circuit}
	\begin{columns}
	 \column{1.2in}
	 \begin{figure}[h]
 		\centering
 		\includegraphics[scale=0.5,trim=0 0 0 0,clip=]{./Images/diode_rx.eps}
 		%\caption{Dynamic Overdriving Driver: Current and Voltage Waveform}
% 		%\label{DOD_wave}
 	\end{figure}
	\column{4in}
	\begin{itemize}
	 \item Diode connected inverter followed by inveter amplifier. The amplifier inverter can also be seen as a current comparator that compares current through PMOS and NMOS. 
	\item The diode connected inverter and receiver amplifier (inverter IA) are designed using fingers
	and placed close to each other so that their switching thresholds are nearly same under all process conditions. 
	\end{itemize}

	\end{columns}
	
	\begin{itemize}
	 
	\item With proposed driver and receiver, voltage swing on line $\Delta V$ remains nearly unchanged across process corners.
	\item  $\Delta V$=$I_{static}R_{L}$, Where $R_{L}=\frac{1}{gm_{p}+gm_{n}}$. 
	\item In FNSP and SNFP corners, $R_{L}$ and $I_{static}$ both remain nearly unchanged. 
	\item In SS and FF corners, decrease/increase in $I_{static}$ is somewhat compensated by increase/decrease in $R_{L}$. Hence, line voltage swing remains nearly unchanged in all process corners. 
	\end{itemize}
	
	
\end{frame}

\subsection{Simulations Results}

\begin{frame}
   \frametitle{Simulation Setup}	
   \begin{itemize}
    \item Technology $0.18 \mu m$  UMC, $V_{dd}=1.8$
     \item All signaling systems designed such that they present equal input capacitance (1$\times$Minimum sized inverter) and drive same load of four min sized inverters(FO4). 
     \item All the signaling schemes, current mode and voltage mode, are designed for throughput of 2.5 Gbps in typical process corner. 
     \item All the CMS schemes are designed for a given voltage swing on line based on sensitivity of the circuit to on-chip PVT variations. 
    
   \end{itemize}
 
 \end{frame}

 
 \begin{frame}
     \frametitle{Minimum Voltage Swing on Line}
      \begin{itemize}
      \item \textbf{Vdd Vaiations:} 5\% (of Vdd)  signal related and 5\% signal unrelated variation in both Vdd and Vss. Signal unrelated variations are modeled as triangular wave of 2GHz frequency. Vdd and Vss change in opposite direction reducing magnitude of supply by 10\%.
      \item \textbf{Temperature Variations:} Transmitter and receiver are assumed to be operating at 30$ ^\circ C $  and 130$ ^\circ C $  respectively.
      \item \textbf{On-chip process variations:} 33.33\% of overall process variations given in model file provided by the foundry. The worst case for on-chip process variations is when all transistors of transmitter are in $TT_{SNFP}$ or $TT_{FNSP}$ corner and all the transistors of receiver are in $TT_{FNSP}$ or $TT_{SNFP}$  corner.
     \end{itemize}
  
     \begin{table}[h]
	\centering
	
	\begin{tabular}{|c|c|c|c|} \hline
	CMS system &  \multicolumn{3}{c|}{Line Voltage Swing (mV)} \\
	\cline{1-4}
	 & Process & Voltage  & Temp\\
	\hline
	CMS-Bias&$ 1$ & 10 & $ 1$ \\
	\hline
	CMS-Fpw & 30 &  10 & 10  \\
	\hline
	CMS-Fb  & $1$ & 10 & $1$ \\
	\hline
	\end{tabular}
    \end{table}
	\begin{itemize}	
	 \item CMS schemes proposed by Tabrizi et. al. (CMS-Fpw) and the one proposed here are designed for 30mV of line voltage swing. CMS schemes with the driver proposed by Katoch et. al. are designed for 70mV. 
	\end{itemize}
 \end{frame}

\begin{frame}
\frametitle{Spped-Power-Area Comparison } 
     
\begin{itemize}
%\item Power is measure for 1000 random input bits with activity factor of around 0.5
 \item In the proposed scheme bias generation circuit will be shared by all the wires in a bus. Considering typical bus width of 16, one by sixteenth of power and area of bias generation circuit is added in total power and area of a single wire.
 
  
\end{itemize}

\begin{table}[h]
%\label{tab:1}
\centering
%\caption{Performance Comparison of four signaling schemes (line=6 mm, Power measured at 1Gbps)}
\begin{tabular}{|c|c|c|c|c|} \hline
 
Signaling & Delay & Throughput & Power & Area \\
Scheme & (ps) & (Gbps) & ( $\mu W$) & ($\mu m^2$) \\ 
\hline
Proposed CMS & 490 & 2.63 & 113 & 3.07  \\
 \hline
 CMS-Fb  & 570 &  2.77 & 140 & 2.00   \\
 \hline
% \hline
 CMS-Fpw & 503 & 2.56 & 114 & 2.45 \\
 \hline
 Voltage Mode & 1100 & 2.85 &   655 & 12.53 \\
% \hline:
% Ref. \cite{katoch05} Ref. \cite{katoch05} & 13 & 33 \\
% \hline
% Ref. \cite{mwscas07} Ref. \cite{katoch05} & 10 & 14\\
\hline
\end{tabular}
\end{table}
\begin{itemize}
 \item Proposed CMS scheme shows 14\% and 19\% improvement in delay and power, repectively over the CMS proposed by Katoch et. al. 
 \item Delay and power of the voltage mode signaling scheme is twice and 5.79 times those of the prposed scheme, respectively.
 \item Three signaling schemes, CMS-Bias, CMS-Fb and CMF-Fpw gain 76\%, 84\% and 80\% in area over voltage mode scheme respectively.
 \item By using CMS scheme with DOD, it is possible to achieve throughput as high as that of voltage mode without using repeaters at much lower power and smaller delay.

  
\end{itemize}


\end{frame}

\subsection{Effect of Process Variations}
\begin{frame}
\frametitle{Effect of Inter-die Process Variations } 
     
\begin{itemize}
%\item Power is measure for 1000 random input bits with activity factor of around 0.5
\item Seperate analyses for Inter-die and Intra-die Process Variations
\item Throughput is defined as maximum rate at which data can be transmitted with $V_{OH} > 0.8 Vdd$ and $V_{OL} < 0.2 Vdd$. Throughput of a system is measured by applying 1000 random bits. 
\item The performance of CMS schemes with all six combination of drivers and receivers have been analyzed. 
\end{itemize}

\begin{table}[h]
%\label{tab:1}
\centering
%\caption{Effect of Inter-die Process Variations}
\begin{tabular}{|c|c|c|c|} \hline
 
 \multicolumn{2}{|c|}{CMS system} &  \multicolumn{2}{c|}{Percentage Degradation} \\
\cline{1-4}
Driver&Receiver & Delay & Throughput\\
\hline
DOD-Bias&Rx-D & 22 & \textbf{22.4}  \\
\hline
DOD-Fb&Rx-D & 16 &  15   \\
\hline
DOD-Fpw&Rx-D & 20 & 36 \\
\hline
%\hline
DOD-Bias&Rx-Fb & 17 & 24 \\
\hline
DOD-Fb&Rx-Fb & 4.6 & \textbf{14} \\
\hline
DOD-Fpw&Rx-Fb & 18 & \textbf{34} \\
\hline
\multicolumn{2}{|c|}{Voltage Mode} & 42 & \textbf{30}\\
\hline
\end{tabular}
\end{table}

\begin{itemize}
 \item The degradation in delay in voltage mode buffer insertion scheme is more than that of any other CMS scheme.
\item The effect of receiver circuits in degradation of throughput is not significant. 
 
\end{itemize}
\end{frame}


\begin{frame}
\frametitle{Effect of Inter-die Process Variations } 
     
\begin{itemize}
%\item Power is measure for 1000 random input bits with activity factor of around 0.5

\item A 7-stage ring oscillator with each inverter driving FO4 load is considered as representative of logic core. 
\end{itemize}

\begin{table}[h]
\centering
%\caption{Effect of Four Corner Process Variations on Logic Circuits and Various Interconnects }
\begin{tabular}{|c|c|c|c|c|c|} \hline
\multicolumn{2}{|c|}{Signaling System/} &  \multicolumn{4}{c|}{Percentage Variation} \\
\cline{3-6}
\multicolumn{2}{|c|}{Logic Circuit} & SS & FF & SNFP & FNSP \\
\cline{1-6}
\hline
DOD-Bias & Rx-D & -22.4 & +6 & \textbf{-7} & \textbf{-7}  \\
\hline
DOD-Fb & Rx-D & -14 & < 2 & \textbf{-3} & \textbf{-4} \\
\hline
DOD-Fpw & Rx-D & -22.4 & +10 & \textbf{-34} & \textbf{-33 } \\
\hline
\multicolumn{2}{|c|	}{Voltage Mode} & -27 & +6 & $<$ \textbf{1} & \textbf{-2.8} \\
\hline
\multicolumn{2}{|c|}{Ring Oscillator Freq.} & -23 & +19.0 & \textbf{-2.88} & \textbf{-3}  \\
\hline
\end{tabular}
\end{table}

\begin{itemize}
 \item The degradation in throughput of CMS with the driver DOD-Fpw is large and the worst case corner for throughput is SNFP.
 \item The proposed signaling scheme requires some amount of overdesign so that interconnects do not become bottleneck in overall speed of the chip. 
\end{itemize}
\end{frame}

\begin{frame}
\frametitle{Effect of Intra-die Process Variations } 
     
\begin{itemize}
%\item Power is measure for 1000 random input bits with activity factor of around 0.5

\item The worst case for intra-die process variations is when all the transistors of transmitter are in $TT_{SNFP}/TT_{FNSP}$ while all the transistors of receiver are in $TT_{FNSP}/TT_{SNFP}$ corner. 
\end{itemize}

\begin{table}[h]
%\label{tab:1}
\centering
%\caption{Effect of Intra-die Process Variations}
\begin{tabular}{|c|c|c|c|} \hline
 
\multicolumn{2}{|c|}{CMS system} &  \multicolumn{2}{c}{Percentage Degradation} \\
\cline{1-4}
Driver&Receiver & Delay & Throughput\\
\hline
DOD-Bias & Rx-D &4 & \textbf{9.5}  \\
\hline
DOD-Fb& Rx-D & 16 & 36    \\
\hline
DOD-Fpw& Rx-D & 6 & 16 \\
\hline
DOD-Bias& Rx-Fb & 10 & 12 \\
\hline
DOD-Fb & Rx-Fb& 13 & \textbf{33} \\
\hline
DOD-Fpw  &  Rx-Fb&10 & \textbf{14}\\

\hline
\end{tabular}
\end{table}
\begin{itemize}
 \item In the worst case of on-chip process variations this process conditions logic frequency degrades by less than 1\%.
 \item The degradation in throughput of the CMS scheme with the driver DOD-Fpw is more. This is because
at high frequencies voltage at node linerx is uneven around VM because of feedback from line in weak driver.
 \item The proposed signalign scheme shows least degradation in throughtput in the presence of intra-die process variations.
\end{itemize}
\end{frame}
% 
% \begin{frame}
% \frametitle{Conclusion} 
%      
% \begin{itemize}
% \item 
% \end{itemize}
% \end{frame}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%


% \begin{frame}
%  \frametitle{Effect of Process Variations on Existing Current Mode Signaling}
%  \begin{itemize}
%   \item 
%  \end{itemize}
% 
% \end{frame}

% 
% \section{Simulation Results}
% 
%  \begin{frame}
%    \frametitle{Simulation Setup}	
%    \begin{itemize}
%     \item Technology $0.18 \mu m$  UMC, $V_{dd}=1.8$
%      \item All signaling systems designed such that they present equal input capacitance (1$\times$Minimum sized inverter) and drive same load of four min sized inverters(FO4). 
%     \item Interconnects modeled as 5section RC: $R_{0}=178\Omega/mm$, $C_{0}=0.192pF/mm$, $L=0.5 nH/mm$
%    \end{itemize}
%  
%  \end{frame}
% 
% \subsection{Comparison of Driver Circuits}
% 
% \begin{frame}
% \frametitle{Driver Circuits: Performance Metrics}
% 	\begin{itemize}
% 	\item Power consumption in driver circuit at high data rate 
% 	\item Delay through the driver circuit: The delay of driver circuit is defined as the time difference between input reaches to its $50\%$ value and voltage at the input of full swng driver reaches $50\%$ of its final value.
% 	\item Variation in delay of complete current mode signaling scheme across process corners
% 	\item Throughput of the complete signaling scheme in presence of on-chip process variations 
% 	\end{itemize}
% \end{frame}
% 
% \begin{frame}
% \frametitle{Driver Circuit:Power and Delay}
% 	\begin{itemize}
% 	\item The driver circuits proposed by Katoch et.al., Fixedpw-DOD, K'-Fixedpw-DOD and with Skewed inverters are designed for same overdrive current ($I_{peak}=400\mu A$) and overdrive duration ($t_{p}=130ps$).
% 	\item The designed drivers Fixedpw-DOD and K'-DOD employ same inverter chain(three minimum sized inverters).
% 	\item In skewed inverter driver, difference between switching threshold of skewed inverters is 80mV. 
% 	\item In Bootstrapping driver input capacitors are of $10fF$ gives $I_{peak}$ of $270\mu A$
% 	
% 	\end{itemize}
% 
% 		\begin{table}[h]
% 		%\label{tab:driver}
% 		\centering
% 		% 
% 		\begin{tabular}{|c|c|c|}
% 		\hline
% 		Driver & Power($\mu W$) & Driver Delay ($ps$) \\
% 		\hline
% 		K-DOD   & $464$ & $190 $  \\
% 		\hline
% 		Fixedpw-DOD  & $273$ & $156$  \\
% 		\hline
% 		K'-Fixedpw-DOD& $252$ & $152$  \\
% 		\hline
% 		Skewed Inverters & $260$ & $121$ \\
% 		%\hline
% 		Boot Strapping & $257$ & $160$  \\
% 		%\hline
% 		\hline
% 		\end{tabular}
% 		%\caption{Comparison of Various Driver Circuit: Power and Delay }
% 		\end{table}
% \end{frame}
% \begin{frame}
% \frametitle{Driver Circuit:Variation in Delay with Process Variations}
% 	\begin{itemize}
% 	\item The complete current mode signaling schemes are designed for line voltage swing of $120 mV$ and overdrive current($I_{peak}$) of $400 \mu A$.  
% 	\item Receiver Circuit employed is diode connected inverter as line termination  
% 	\end{itemize}
% 
% 		\begin{table}[h]
% 		%\label{tab:driver_corner}
% 		\centering
% 		% 
% 		\begin{tabular}{|c|c|c|c|c|c|c|}
% 		
% 		\hline
% 		Driver & \multicolumn{5}{c|}{Delay(ps)}&\% Maximum Variation\\
% 		\cline{1-7} Circuit& tt & ss & ff & snfp & fnsp & \\
% 		\hline
% 		K-DOD   & $665$ & $765$ & $600$ & $660$ & $662$&  $24\%$\\
% 		\hline
% 		K'-Fixedpw-DOD& $600$ & $745$&$566$&$650$&$720$ & $30\%$ \\
% 		\hline
% 		\end{tabular}
% 		%\caption{Comparison of Various Driver Circuit: Variation in Delay across process variation}
% 		\end{table}
% 	\begin{itemize}
% 	\item The CMS with K-DOD driver is more robust against four corner process variations because  that the feedback inverter I1 of the driver turns ON the full swing driver after the line voltage crosses switching threshold of inverter I1. 
% 	\item The switching threshold of the feedback inverter and receiver amplifier inverter are same under all process corners. 
% 	\end{itemize}		
% 		
% \end{frame}
% 
% \begin{frame}
% \frametitle{Driver Circuit:Effect of On-chip Process Variations}
% 	\begin{itemize}
% 	\item In the presence of on-chip PVT variation switching threshold of the feedback inverter and receiver inverter are different causing unequal rise and fall delays of the system 
% 	\item On-chip process variations: $1.2\%$ variation in  $t_{ox}$, $5\%$ variation in $V_{t}$ and $5\%$ variation in $L_{eff}$
% 	\item The maximum throughput is defined as datarate at which output $V_{OH}>0.1V_{dd}$ and $V_{OL}<0.1$ for $200$ random input bits 
% 	\item Throughput of the system with K-DOD and K'-Fixedpw-DOD degrades by more than $61\%$ and $8\%$ respectively. 
% 	\end{itemize}
% 		\begin{table}[h]
% 		\label{tab:driver:mismatch1}
% 		\centering
% 		% 
% 		\begin{tabular}{|c|c|c|c|}
% 		\hline
% 		$ V_{MRx}$ & $ V_{MTx}$ & \multicolumn{2}{c|}{Data Rate(Gbps)} \\
% 		\cline{3-4}
% 		(mV) & (mV) & K-DOD  & K'-Fixedpw-DOD\\
% 		\hline 
% 		$900$ & $900$ & $2.85 $ & $2.5$  \\
% 		\hline
% 		$900$ & $935$ & $2.0 $ & $2.5$  \\
% 		\hline
% 		$900$ & $884$ & $2.22 $ & $2.5$  \\
% 		\hline
% 		$935$ & $884$ & $1.1 $ & $2.3$  \\
% 		\hline
% 		\end{tabular}
% 		\caption{Performance of Driver Circuits in Presence of Process Variation}
% 		\end{table}
% 	
% \end{frame}
% \subsection{Comparison of Receiver Circuits}
% \begin{frame}
% \frametitle{Receiver Circuit:Speed and Power}
% 	\begin{itemize}
% 	\item Receiver circuits are designed for line voltage swing of $50mV$ and overdrive current($I_{peak}$) of $200\mu A$. The designed source follower receiver offers $65mV$ of voltage swing. 
% 	\item Power measured at 1Gbps and delay measured at 100Mbps
% 
% 	\end{itemize}
% 		\begin{table}[h]
% 		%\label{tab:receiver}
% 		\centering
% 		% 
% 		\begin{tabular}{|c|c|c|c|}
% 		\hline
% 		Driver + Receiver & Power($\mu W$) & Delay ($ns$) & Throughput(Gbps) \\
% 		\hline
% 		
% 		K'-Fixedpw-DOD + Diode  & $452$ & $ 1.5 $  & $1.0 $\\
% 		\hline
% 		K'-Fixedpw-DOD + Beta Multiplier  & $450 $ & $0.964$  & $1.25 $\\
% 		\hline
% 		K'-Fixedpw-DOD + Katoch & $445$ & $1.19$  & $1.1$\\
% 		\hline
% 		K'-Fixedpw-DOD + SF & $423$ & $1.29$ & $1.15 $ \\
% 		%\hline
% 		\hline
% 		\end{tabular}
% 		%\caption{Comparison of Various Receiver Circuit}
% 		\end{table}
% 	
% \end{frame}
% 
% 
% 
% \subsection{Comparison with Other Current Mode Signaling}
% 
% \begin{frame}
% \frametitle{Comparison with Other Current Mode Signaling}
% \begin{tiny}
% 
% 		\begin{table}[h]
% 		%\label{tab:simr_cms}
% 		\centering
% 		% 
% 		\begin{tabular}{|c|c|c|c|c|c|}
% 		\hline
% 		CMS(Driver+Receiver) &$\Delta V$(mV) & $I_{peak} (\mu A)$& Delay (ns)& Power ($\mu W$) & Throughput(Gbps) \\
% 		
% 		
% 		\hline 
% 		\multirow{2}{*}{K'-Fixedpw-DOD +} & \multirow{2}{*}{$50$} & $ 200 $ & $0.940$ & $450$  &  $1.25$   \\
% 						&			  & $636$  & $0.666$  & $424.8 $ & $2.63$	\\	
% 					
% 		\multirow{2}{*}{Beta Multiplier}   & \multirow{2}{*}{$120$} & $ 350 $ & $1.05$ & $441$  &  $2.38$   \\
% 						&					  & $636$  & $0.762$  & $428.8 $ & $2.63$	\\	
% 		\hline
% 		\multirow{2}{*}{K'-Fixedpw-DOD +} & \multirow{2}{*}{$50$} & $ 200 $ & $1.5$ & $452$  &  $1.0$   \\
% 						&			                 & $636$  & $0.666$  & $424.8 $ & $2.63$	\\	
% 					
% 		\multirow{2}{*}{Diodeconnected}	  & \multirow{2}{*}{$120$} & $ 350 $ & $1.52$ & $502$  &  $2.08$   \\
% 						&			  & $636$  & $0.923$  & $509 $ & $2.5$	\\	
% 		
% 		
% 		\hline
% 		\multirow{4}{*}{K-DOD+ Katoch} 		& \multirow{2}{*}{$50$} & $ 200 $ & $0.884$ & $514$  &  $1.4$   \\
% 								&	                 & $636$  & $0.726$  & $552.6 $ & $2.83$\\
% 					
% 								& \multirow{2}{*}{$120$} & $ 350 $ & $1.1$ & $574$  &  $2.2$   \\
% 								&			  & $636$  & $0.858$  & $540 $ & $2.83$\\
% 		\hline
% 		
% 		\end{tabular}
% 		%\caption{Comparison of Various Current Mode Signaling Scheme }
% 		\end{table}
% 		
% 		\begin{itemize}
% 		\item  25\% to 40\% improvement in throughput for small overdrive current and small voltage swing achieved by CMS with Inductive Input Impedance. 
% 		\item  No improvement in throughput for small overdrive current. 
% 		\item 11\% and 20 \% improvement in delay and power compared to the one proopsed by Katoch et. al., at high overdrive currents achieved by proposed current mode signaling scheme
% 		\end{itemize}
% \end{tiny}
% 
% \end{frame}
% 
% \subsection{Comparison with Voltage Mode Signaling}
%  
% \begin{frame}
% \frametitle{Comparison with Voltage Mode:Delay and Power} 
% 	\begin{columns}
% 	\column{1in} 
% 		\begin{figure}[h]
% 		\centering
% 		\includegraphics[scale=0.2,trim=0 0 0 0,clip=]{./Images/delay_line_act.eps}
% 		%\caption{Comparison of Voltage mode and Proposed signaling scheme : Delay}
% 		%\label{delay_line}
% 		\end{figure}
% 
% 	\column{2.5in}
% 		\begin{figure}[h]
% 		\centering
% 		\includegraphics[scale=0.19,trim=0 0 0 0,clip=]{./Images/eb_ilne1.eps}
% 		%\caption{Comparison of Voltage mode and Proposed signaling scheme :Energy per bit}
% 		%\label{eb_line}
% 		\end{figure}
% 		
% 	\end{columns}
% 		\begin{itemize}
% 		\item  The proposed signaling shows around 40\% improvement in delay at the same time 50\% improvement in power
% 		\item  The proposed current mode signaling scheme consumes around 25 times lower energy for transmission of each bit for 6mm long line measured at 1data rate of 1Gbps. 
% 		\end{itemize}
% 
% \end{frame}
% 
% \begin{frame}
% \frametitle{Comparison with Voltage Mode: Power vs Data Rate} 
% 	\begin{figure}[h]
% 	\centering
% 	\includegraphics[scale=0.3,trim=0 0 0 0,clip=]{./Images/power_datarate.eps}
% 	%\caption{Comparison of Voltage mode and Proposed signaling scheme : Power vs Data rate}
% 	%\label{power_datarate}
% 	\end{figure}
% 		\begin{itemize}
% 		\item The proposed current mode signaling scheme consumes less power than voltage mode for data rates more than 50Mbps. 
% 		\end{itemize}
% \end{frame}
% 
% \section {Delay Model}
% \subsection{Approach}
% \begin{frame}
%  \frametitle{Motivation}
%  Modeling: Analytical expressions for delay of the system as a function of design variables and system parameters. 
%  \begin{itemize}
% %  \item Buffer insertion is one of the most established methods of CMOS integrated circuits: fairly accurate delay models  available and design methodology established. 
% %  \item The first step towards current mode replacing current mode signaling scheme replacing buffer insertion scheme is accurate delay model of current mode signaling scheme.
%  \item Delay of the current mode signaling scheme depends on design of the driver and receiver circuits
%  \item Required to know delay of the scheme under various design parameters, in order to design the system for given delay requirements
%  \item Inefficient to find delay for large number of combinations of design parameters through simulations
%  \item Delay model gives quick estimate of delay of the system for given design variables. 
%  \item Objective : To develop a simple delay model for this current mode signaling scheme which correctly predicts change in delay of the system with change in various design variables.
%  
%  \end{itemize}
% \end{frame}
% 
% \begin{frame}
%  \frametitle{Delay Modeling :Approach}
%  \begin{itemize}
%  \item If we consider transistor geometries as design variables and try to find delay of the system as a function of these transistor geometries, then number of design variables becomes very large and the task becomes very complex. 
%  \item First find simple equivalent circuit of the system which has small number of design variables and develop delay model for these reduced number of design variables.
%  \item Derive these reduced number of design variables from the actual circuits. 
%  \item Then find transistor geometries for given reduced number of design variables
%  \item Dynamic overdriving driver with diode connected inverter as load are 
% \end{itemize}
% \end{frame}
% 
% \begin{frame}
%  \frametitle{Delay Modeling :Current Mode Signaling with Diode Connected Inverter}
%  \begin{figure}
% 	\centering
% 	\includegraphics[scale=0.3,trim=0 0 0 0,clip=]{./Images/cms_diode.eps}
% 	%\caption{Distributed RC model of On-chip Interconnect}
% 	%\label{line_load_l}
% 	\end{figure}	
% \end{frame}
% 
% \begin{frame} 
%  	\frametitle{Delay Modeling: Simplified Circuit }
% 	\begin{figure}
% 	\centering
% 	\includegraphics[scale=0.3,trim=0 0 0 0,clip=]{./Images/DOD_eqckt.eps}
% 	%\caption{Distributed RC model of On-chip Interconnect}
% 	%\label{line_load_l}
% 	\end{figure}	
% 	
% 	\begin{itemize}
%  	\item The driver circuit can be modeled as a current source with DOD current waveshape
%  	\item At receiver end diode connected inverter is modeled as $R_{L}$ and voltage source $V_{dd}/2$. 
%  	\item The receiver amplifier is considered as an inverting amplifier with gain of G and time constant of $\tau $.
%  	\end{itemize}
% 	
%  	% 	
%  \end{frame}
% 
%  
%  
%  \begin{frame} 
%  	\frametitle{Delay Modeling: Simplified Circuit Parameters}
% 	 \begin{itemize}
%  	\item $I_{peak }$: Current through transistor P2-P3/N2-N3 when their input is $V_{ss}/V_{dd}$ and line voltage is $V_{dd}/2$. 
% 	\item tp:  It is 50\% delay of the inverter  chain forming delay element. 
% 	\item $td_{tx}$: It is time difference between input reaches 50\% of its final value and input at the gate of P2/N2 reaches 50\%. 
% 	\item $R_{L}$: Resistance offered by diode connected inverter, given by $1/(g_{mp}+g_{mn})$. Where, $g_{mp}$ and $g_{mn}$ are transconductances of  diode connected transistors. 
% 	\item $G$: Gain of receiver amplifier,  $(g_{mp1}+g_{nm1})(r_{on1}||r_{op1})$. Where, $g_{mp1}$ and $g_{mn1}$ are transconductances of transistors of inverter amplifier.
% 	\item $\tau$: Time constant of the receiver amplifier, $((r_{on1}||r_{op1})C_{La})$. Where, $C_{La}$ is sum of gate capacitance of one minimum size inverter and junction capacitance of the receiver amplifier.
%  	\end{itemize}
% \end{frame}
% 
% \begin{frame} 
%  	\frametitle{Delay Modeling: Approach}
% 	 \begin{itemize}
% 	 \item Split into three parts : Transmitter Delay + Line Delay + Receiver Delay 
% 	\item{\textbf{Transmitter Delay:}} Time in which signal reaches $V_{dd}/2$ at the input of strong driver
% 	\item{\textbf{Line Delay:}} Time difference between input reaches strong driver and voltage at line end (input of amplifier) reaches $ V_{dd}/2$).
% 	\item{\textbf{Receiver Model:}}Delay from input to receiver amplifier crosses $V_{dd}/2$ and output of the inverter reaches $V_{dd}/2$.
%  	\end{itemize}
% \end{frame}
% 
% 
%  
% \begin{frame} 
%  	\frametitle{Modeling : Approach  }
% 	\begin{figure}
% 	\centering
% 	\includegraphics[scale=0.3,trim=0 0 0 0,clip=]{./Images/modeling_block_aps.eps}
% 	%\caption{Distributed RC model of On-chip Interconnect}
% 	%\label{line_load_l}
% 	\end{figure}	
%  	% 	
%  \end{frame}
% 
% \begin{frame}
% \frametitle{Range of Design Variables and System Parameters}
% 	\begin{itemize}
%   	\item $I_{peak}$ : $400\mu A$ to $1200\mu A$
% 	\item $t_{p}$    : $40ps$ to $300ps$
% 	\item $ \Delta V$: $40mV$ to $100mV$
% 	\item $ R_{L}$: $1K$ to $2K$
% 	\item Line Length= $4mm$ to $10mm$
% 	\item G=Gain of a minimum sized inverter
% 	
%   	\end{itemize}
% \end{frame}
% 
% \subsection{Delay Models}
% 
% \begin{frame}
% \frametitle{Transmitter Delay}
% 	\begin{itemize}
%   	\item The optimum design of the system requires three inverters ($I_{1}$, $I_{2}$, $I_{3}$) between the input and full swing driver
% 	\item The sizes of these inverters are fixed. 
% 	\item $Td_{tx}=\tau_{1}+\tau_{2}+\tau_{3}$
% 	\item Where $\tau_{1}$, $\tau_{2}$ and $\tau_{3}$ are delays of inverters $I_{1}$, $I_{2}$ and $I_{3}$
% 	\end{itemize}
% \end{frame}
% 
% 
%  
%  \begin{frame} 
%  	\frametitle{Line Delay Model}	
% 	
%  	\begin{itemize}	
%  	 \item Developed for RC dominated on-chip interconnects and hence line is modeled as five section RC
% 	 \item For simple step response to five section RC line for small voltage swing on line $td=\frac{co*line*\Delta V}{I_{avg}}$
% 	 \item In case of DOD-waveshape input, for small tp delay does not vary linearly with $\Delta V$  
% 	 \item Delay for ipeak=1200u:tp=50p is less than delay for ipeak=600u:tp=100p
% 	 \item Reason: Two mechanisms under which signal propagates: a) parallel charging b) wave pipelining  
% 	 \item Hence, delay is function of amount of overdrive given to line in some t1 time ... Here, experimentally we find t1=tau/50 ..
% 	 
% 	
% 	\end{itemize}
% 
% % 	
%  \end{frame}
%  
%  
%  \begin{frame} 
%  	\frametitle{Line Delay Model}	
%  	\begin{itemize}	
%  	 \item $td=(k_{11}*ov_{1}^{-2}+k_{12}*ov_{1}^{-1}+k_{21}*ov_{2}^{-2}+k_{22}*ov_{2}^{-1}...+k_{52}*ov_{5}^{-1}+k_{0})$
%  	\item $ov_{i}$=Amount of extra charge given in $i*tau/50 secs$ 
% 	\item $ov_{i}$=$(I_{line}*tau/50)/(C_{line} \Delta V)$, $I_{line}=I_{peak}$ for $0<t<tp$, $I_{line}=I_{static}$ for $tp<t<\tau/5$, 
% 	%\item co is capacitance per unit line length 
% 	\item $k_{ij}$ are constants 
% 	 
% 	 \end{itemize}  
%  	
% % 	
%  \end{frame}
%  \begin{frame} 
%  	\frametitle{Delay Model: Accuracy }	
%  	
% % 	\begin{frame} 
%  	\frametitle{Delay Model}
% 	\begin{columns}[t]
% 	 \column{2.5in}
% 	\begin{figure}
% 	\centering
% 	%\includegraphics[scale=0.38,trim=0 0 0 0,clip=]{./Images/delay_line5.eps}
% 	\includegraphics[scale=0.35,trim=0 0 0 0,clip=]{/home/users/marshnil/matlab/inductivepeaking/DesignSpaceAnalysis/linedelay1.eps}
% 	%\caption{Actual Delay and Modeled delay: Delay vs $\Delta V$(line=6mm; different Ipeak and tp)}
% 	%\label{line_load_l}
% 	\end{figure}	
% 	\column{2.5in}
% 	\begin{figure}
% 	\centering
% 	\includegraphics[scale=0.35,trim=0 0 0 0,clip=]{/home/users/marshnil/matlab/inductivepeaking/DesignSpaceAnalysis/error.eps}
% 	%\caption{Percentage Error between two delays}
% 	%\label{line_load_l}
% 	\end{figure}	
% 	\end{columns}
% 
%  \end{frame}
% 
%  \begin{frame} 
%  	\frametitle{Delay Model: Constants }	
%  	
% % 	\begin{frame} 
%  %	\frametitle{Delay Model}
% 	\begin{itemize}
% 	 \item Equations for delay for 5 different Ipeak, 5 different tp, 6 different $\Delta V$ are written for a given line length 
% 	\item Constants are found using Least square method in MATLAB
% 	\end{itemize}
% 	 
% 	\begin{tiny}
% 			%\centering
% 			\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|}
% 			\hline
% 			Line&  $k_{11}$&$ k_{12} $&$k_{21}$&$ k_{22}$&$k_{31}$&$ k_{32}$&$k_{41}$&$k_{42}$&$k_{51}$&$k_{51}$&$k_{0}$\\
% 			\hline
% 			6mm & 0.6186 &   80.247  &   0.1338   &  -12.99   & 0.0422 & -4.02 & 0.0608&-5.96&0.2515&-24.1210&156 \\
% 			\hline
% 			10 &   -5.107  &   114.64   &  -41.0338  & 0.0412 & -1.27 & -0.08&5.7&-0.0032&0.19&0.063&176  \\
% 			\hline
% 			\end{tabular} 
% 	\end{tiny}
% 	
%  \end{frame}
% 
% \section{Summery and Future Work}
% 
% \begin{frame}
% \frametitle{Summery and Conclusions} 
% 		\begin{itemize}
% 		\item The technique of inductive peaking in current mode signaling schemes has been suggested.
% 		\item It was discovered that beta multiplier circuits can exhibit inductive input impedance for practical current levels and transistor geometries.
% 		\item The circuit conditions for which beta multiplier exhibit inductive input impedance has been derived : $\gamma-\frac{1}{g_{mn1}r_{op1}}> 0.9$
% 		\item A current mode receiver with inductive input impedance using beta multiplier has been suggested. 
% 		\item The proposed current mode receiver shows around 25\% improvement in delay and 9\% improvement in data rate at equal power  compared to other current mode receiver circuits. 
% 		
% 		\end{itemize}
% \end{frame}
% 
% \begin{frame}
% \frametitle{Summery and Conclusions} 
% 		\begin{itemize}
% 		\item A low power dynamic over driving driver has been proposed
% 		\item The proposed dynamic overdriving driver consumes 46\% improvement in power compared to the existing DOD driver at slightly less delay.  
% 		\item Although the CMS scheme with existing dynamic overdriving driver, gives 14\% higher throughput compared in typical process conditions, the throughput of CMS with the existing driver degrades by 61\%. Whereas throguhput of CMS system with prposed driver derades by 14\% in the presence of on-chip process variations,
% 		\item The current mode signaling schemes with inductive input impedance shows around 25\% improvement in throughput for small overdrive current and large voltage swing. 
% 		\item The proposed signaling shows around 40\% improvement in delay at the same time 50\% improvement in power(100Mbps) for 6mm long line. 
% 		\item The proposed current mode signaling scheme consumes less power than voltage mode for data rates more than 50Mbps. 
% 		\end{itemize}
% \end{frame}
% \begin{frame}
%  \frametitle{Future Work}
% 	\begin{itemize}
% 	\item Take the design of current mode signaling scheme to fabrication at 180nm. 
% 	\item Migrate the design to lower technology node. 
% 	\item Analyze the performance of the system in the presence of on-chip cross-talk from near by short voltage mode lines. Determine the minimum voltage swing in presence of cross talk    
% 	\end{itemize}
% 	
%  %	\begin{tabular}{cc}
% %  	
% % 	\begin{minipage}{2in}
% 		
% 		
% %	\end{minipage}	
% 	
% %	\begin{minipage}{2in}
% 	
% 		
% \end{frame}
% \begin{frame}
% \frametitle{Future Work} 
% 		\begin{itemize}
% 		\item{Modeling:} Extend this delay model for high frequency. Develop a model for power consumption in the system and prepare design space analysis for the system. Extend the delay model such that it is valid even for scaled down technologies. 
% 		\item{Current Mode Repeater:}Employ the current mode receiver plus driver as a repeater. Use the derived delay model to find delay optimum repeater insertion scheme. Find its application in clock distribution. 
% 		\item Explore current mode singling for Finfets
% 		\item Design a bi-directional current mode signaling scheme
% 		\end{itemize}
% % 		\begin{figure}[h]
% % 		\centering
% % 		\includegraphics[scale=0.2,trim=0 0 0 0,clip=]{./Images/bidir.eps}
% % 		%\caption{Dynamic Overdriving Driver: Current and Voltage Waveform}
% % 		%\label{DOD_wave}
% % 		\end{figure}
% \end{frame}
% \begin{frame}
% \frametitle{List of Publications} 
% [1] M. Dave, M. Shojaei and D. Sharma,''Low power current mode receiver with inductive input impedance'', Proceedings of International Symposium on Low Power Electronics and Design, pp. 225-228, August 2008.
% 		%\begin{tiny}
% % 		\begin{thebibliography}{10}
% % 			\providecommand{\url}[1]{#1}
% % 			\csname url@samestyle\endcsname
% % 			\providecommand{\newblock}{\relax}
% % 			\providecommand{\bibinfo}[2]{#2}
% % 			\providecommand{\BIBentrySTDinterwordspacing}{\spaceskip=0pt\relax}
% % 			\providecommand{\BIBentryALTinterwordstretchfactor}{4}
% % 			\providecommand{\BIBentryALTinterwordspacing}{\spaceskip=\fontdimen2\font plus
% % 			\BIBentryALTinterwordstretchfactor\fontdimen3\font minus
% % 			\fontdimen4\font\relax}
% % 			\providecommand{\BIBforeignlanguage}[2]{{%
% % 			\expandafter\ifx\csname l@#1\endcsname\relax
% % 			\typeout{** WARNING: IEEEtranS.bst: No hyphenation pattern has been}%
% % 			\typeout{** loaded for the language `#1'. Using the pattern for}%
% % 			\typeout{** the default language instead.}%
% % 			\else
% % 			\language=\csname l@#1\endcsname
% % 			\fi
% % 			#2}}
% % 			\providecommand{\BIBdecl}{\relax}
% % 			\BIBdecl
% % 			\bibitem{meislped}
% % 		M. Dave, M. Shojaei and D. Sharma,``Low power current mode receiver with inductive input impedance``\emph{Proceedings of  International Symposium on Low Power Electronics and Design}, August 2008.
% % \end{thebibliography}
% 
% 		%\end{tiny}
% 		
% \end{frame}
% \frametitle{References} 
% 
% \begin{frame}
% %\frametitle{References} 
% \begin{center}
% Thank You 
% \end{center}
% 
% \end{frame}
% 
% 
% \begin{frame}
%  \frametitle{Dynamic Overdriving Driver Circuits: Boot Strapping}
% 	
% 		\begin{figure}[h]
% 		\centering
% 		\includegraphics[scale=0.3,trim=0 0 0 0,clip=]{./Images/DOD-boot.eps}
% 		%\caption{Dynamic Overdriving Driver: Current and Voltage Waveform}
% 		%\label{DOD_wave}
% 		\end{figure}
% \end{frame}
% 
% %\subsection{Analysis of Proposed Current Mode Signlaing Scheme}
% 
% 
% \begin{frame}
% \frametitle{Effect of $\Delta V$}
% 	\begin{itemize}
% 	\item Supply Noise : Signal correlated noise (5\% of Vdd and 5\% of Gnd) and Signal un-correlated noise of 2Hz (5\% of Vdd and 5\% of Gnd) requires voltage swing of $\Delta V=30mV$   
% 	\item $I_{peak}=636 \mu A$ and $t_{p}=130ns$  
% 	\item With increase in $\Delta V=30mV$, average voltage swing on line over one period of input, increases and hence static power consumption in receiver circuit decreases
% 	\item $\Delta V$ is varied by redesigning beta multiplier and hence by changing $R_{L}$.
% 	\end{itemize}
% 		\begin{table}[h]
% 		%\label{tab:simr_delv}
% 		\centering
% 		% 
% 		\begin{tabular}{|c|c|c|c|c|}
% 		\hline
% 		$\Delta V$ & Delay & \multicolumn{3}{c|}{Power $\mu W$} \\
% 		\cline{1-5}
% 		(mV) & (ps) &200Mbps & at 1Gbps  & at 2Gbps\\
% 		\hline 
% 		$30$& $595$ & $325.8$ & $440 $ & $586$  \\
% 		\hline
% 		$50$  & $650$& $322.2$ & $424.8 $ & $590.4$  \\
% 		\hline
% 		$120$ & $762$ & $297$ & $428.4 $ & $594$  \\
% 		\hline
% 		\end{tabular}
% 		%\caption{Effect of $\Delta V$ on performance of the system}
% 		\end{table}
% 	
% \end{frame}
% 
% \begin{frame}
% \frametitle{Effect of $I_{peak}$}
% 	\begin{itemize}
% 	\item $\Delta V=50mV$ and $t_{p}=130ns$  
% 	\item With increase in $I_{peak}$, average voltage swing on line over one period of input, increases and hence static power consumption in receiver circuit decreases
% 	\end{itemize}
% 		\begin{table}[h]
% 	%	\label{tab:simr_ipeak}
% 		\centering
% 		% 
% 		\begin{tabular}{|c|c|c|c|}
% 		\hline
% 		$I_{peak}$ & Delay & \multicolumn{2}{c|}{Power $\mu W$} \\
% 		\cline{3-4}
% 		($\mu A$) & (ps) & at 1Gbps  & at 1.25Gbps\\
% 		\hline 
% 		$200$ & $940$ & $450 $ & $491$  \\
% 		\hline
% 		$362$ & $735$ & $435 $ & $453$  \\
% 		\hline
% 		$525$ & $666$ & $426 $ & $462$  \\
% 		\hline
% 		$636$ & $650$ & $424 $ & $473$  \\
% 		\hline
% 		$746$ & $615$ & $426 $ & $495$  \\
% 		\hline
% 		$837$ & $600$ & $453 $ & $502$  \\
% 		\hline
% 		\end{tabular}
% 	%	\caption{Effect of $I_{peak}$ on performance of the system}
% 		\end{table}
% 	
% \end{frame}
% 
% 
% % \begin{frame}
% % 	\frametitle{Dynamic Overdriving Driver}
% % 	\begin{itemize}
% % 	 \item Strong driving current is given to the line during transition and small static current is given during the rest of the time
% % 	\end{itemize}
% % 	\begin{columns}
% %   	\column{3.5in}
% % 	
% % 	\begin{figure}
% % 	\centering
% % 	\includegraphics[scale=0.31,trim=0 0 0 0,clip=]{/home/users/marshnil/Doc/Dynamicoverdriving.eps} 
% % 	%\caption{}
% % 	\label{fig:driver}
% % 	\end{figure}
% % 	\column{1.5in}
% % 	\begin{figure}
% % 	\centering
% % 	\includegraphics[scale=0.2,trim=0 0 0 0,clip=]{/home/users/marshnil/ISLPED/paper_pdf/DODillu1.eps} 
% % 	%\caption{}
% % 	\label{fig:driver}
% % 	\end{figure}
% % 	\end{columns}
% % % 	\begin{figure}
% % 	%\centering
% % 	%\includegraphics[scale=0.44,trim=0 0 0 0,clip=]{/home/users/marshnil/ISLPED/final_paper_pdf/results/katochdriverandcompletescheme_sir.eps} 
% % 	%\caption{Complete Current Mode System}
% % 	%\label{fig:driver}
% % 	%\end{figure}
% % % 
% %  \end{frame} 
% %  \section{Complete Current Mode Signaling System}
% %  \begin{frame}
% % 	\frametitle{Complete Signaling Scheme}
% % 	\begin{figure}
% % 	\centering
% % 	\includegraphics[scale=0.5,trim=0 0 0 0,clip=]{/home/users/marshnil/ISLPED/final_paper_pdf/results/katochdriverandcompletescheme_sir.eps} 
% % 	\caption{Complete Current Mode System}
% % 	\label{fig:driver}
% % 	\end{figure}
% % 	\end{frame} 
% % \section{Simulation Reults}
% % 
% % % 





\end{document}

\begin{frame}
\frametitle{Effect of Inductance}
Since currents are used to signal information across the wire,
the effect of wire inductance on system performance needs to be considered.\\

 Wire inductance changes the characteristic impedance of the wire,
and hence the wire needs to be terminated into the characteristic impedance $Z_0$
rather than $0$.\\

 The beta-multiplier circuit used for termination however,
is capable of matching any impedance
because its input impedance can be controlled by sizing.
\end{frame}
\begin{frame}
\frametitle{Effect of Inductance}
 Inductance will increase the latency due to $L\cdot dI/dt$ factor
affecting the current transition times.\\

 However, at 0.18$\mu$m technology node,
the wire inductance is very small,
and the change in latency is expected to be small.\\

 Simulation results confirm that the increase in latency
due to increased inductance is negligible.
\end{frame}
