Memory Sub-system Design for Optimal Performance in Systems-on-Chip

In modern VLSI systems-on-chip, the memory subsystem is an important component which occupies a significant fraction of the area, consumes a significant fraction of the energy, and most importantly, defines the performance characteristics of the SoC. To date, there has not been a systematic study of the architecture of the memory sub-system on an SoC starting from a requirements level analysis and proceeding to an architecture definition and optimization flow. In our research we aim to lay the foundations of such an approach. To this end, we have proposed:

• a model for viewing the SOC as an interaction between users and memory spaces
• a formulation of the memory subsystem design problem in terms of user behaviour
• a template for a general memory architecture
• algorithms for data distribution and memory selection.

This work envisages the establishment of an SOC design flow that treats the memory subsystem in a formal manner, so that high quality architectures for the memory subsystem may be derived in a natural manner.

We have already identified an assignment quality metric which is highly correlated with memory performance over large regions of the design space. Currently we are looking at identifying a second metric in order to completely characterize memory subsystem performance for a given address trace. In order to give our research an empirical justification, we have developed a memory simulator for systems-on-chip (this simulator uses the Augmint framework from UIUC).