Release Notes for MPASM™ Assembler v5.10
26 January 2007
Table of Contents

1. Important MPLINK and MPLAB IDE Compatibility Note
2. Command Line Device Options Supported
3. Operating System Support List
4. Repairs and Enhancements Made Since v5.00
5. Known Problems
6. Using MPASM Assembler
7. Customer Support

1. # Important MPLINK and MPLAB IDE Compatibility Note

Due to a change in COFF file format, MPASM v5.00 and later will not be compatible with versions of MPLINK prior to v4.00 or versions of the MPLAB IDE prior to v7.21.

MPASM v5.00 and later will have backward compatibility to earlier versions at the source level only. Any existing object files or libraries compiled with earlier versions of the tools will not link using new versions of the tools. They will need to be recompiled from source.

If the user attempts to use this release with object files or libraries compiled with earlier versions of MPLAB C18, MPLINK, and MPASM, the error message that will be received will be similar to:

    Error - Coff file format for 'C:\mcc18\lib/c018i.o' is out of date.

If the user attempts to use an old version of MPLINK to link object files or libraries compiled with this release, the error message that will be received will be similar to:
`
Error - Coff file format for 'C:\mcc18\lib/c018i.o' does not appear to be a valid COFF file.
`

2. # Command Line Device Options Supported

    10F200       10F202       10F204       10F206
    10F220       10F222

    12C508       12C508A      12C509       12C509A
    12C671       12C672
    12CE518      12CE519      12CE673      12CE674
    12CR509A
    12F508       12F509       12F510       12F609
    12F615       12F629       12F635       12F675
    12F683
    12HV609*     12HV615*

    14000

    16C432       16C433       16C505       16C52
    16C54        16C54A       16C54B       16C54C
    16C55        16C554       16C557       16C558
    16C55A       16C56        16C56A       16C57
    16C57C       16C58A       16C58B
    16C5X
    16C61        16C62        16C620       16C620A
    16C621       16C621A      16C622       16C622A
    16C62A       16C62B       16C63        16C63A
    16C64        16C642       16C64A       16C65
    16C65A       16C65B       16C66        16C662
    16C67        16C71        16C710       16C711
    16C712       16C715       16C716       16C717
    16C72        16C72A       16C73        16C73A
    16C73B       16C74        16C745       16C747
    16C74A       16C74B       16C76        16C765
    16C77        16C770       16C771       16C773
    16C774       16C781       16C782       16C84
    16C923       16C924       16C925       16C926
    16CE623      16CE624      16CE625
    16CR54       16CR54A      16CR54B      16CR54C
    16CR56A      16CR57A      16CR57B      16CR57C
    16CR58A      16CR58B      16CR62       16CR620A
    16CR63       16CR64       16CR65       16CR72
    16CR83       16CR84
    16CXX
    16F505       16F506       16F54        16F57
    16F59        16F610       16F616       16F627
    16F627A      16F628       16F628A      16F630
    16F631       16F636       16F639       16F648A
    16F676       16F677       16F684       16F685
    16F687       16F688       16F689       16F690
    16F716       16F72        16F722*      16F723*
    16F724*      16F726*      16F727*      16F73
    16F737       16F74        16F76        16F767
    16F77        16F777       16F785       16F818
    16F819       16F83        16F84        16F84A
    16F87        16F870       16F871       16F872
    16F873       16F873A      16F874       16F874A
    16F876       16F876A      16F877       16F877A
    16F88        16F882*      16F883       16F884
    16F886       16F887       16F913       16F914
    16F916       16F917       16F946

    16HV540      16HV610*      16HV616      16HV785

    17C42        17C42A       17C43        17C44
    17C752       17C756       17C756A      17C762
    17C766
    17CR42       17CR43
    17CXX

    18C242+      18C252+      18C442+      18C452+
    18C601+      18C658+      18C801+      18C858+

    18F1220+     18F1230      18F1231      18F1320+
    18F1330      18F1331      18F2220+     18F2221
    18F2320+     18F2321      18F2331+     18F2410+
    18F242+      18F2420+     18F2423      18F2431+
    18F2439+     18F2450      18F2455+     18F2458*
    18F248+      18F2480+     18F24J10+    18F24K20
    18F2510+     18F2515+     18F252+      18F2520+
    18F2523      18F2525+     18F2539+     18F2550+
    18F2553*     18F258+      18F2580+     18F2585+
    18F25J10+    18F25K20     18F2610+     18F2620+
    18F2680+     18F2682      18F2685      18F4220+
    18F4221      18F4320+     18F4321      18F4331+
    18F4410+     18F442+      18F4420+     18F4423
    18F4431+     18F4439+     18F4450      18F4455+
    18F4458*     18F448+      18F4480+     18F44J10+
    18F44K20     18F4510+     18F4515+     18F452+
    18F4520+     18F4523      18F4525+     18F4539+
    18F4550+     18F4553*     18F458+      18F4580+
    18F4585+     18F45J10+    18F45K20     18F4610+
    18F4620+     18F4680+     18F4682      18F4685
    18F6310+     18F6390+     18F63J11     18F63J90
    18F6410+     18F6490+     18F64J11     18F64J15
    18F64J90     18F6520+     18F6525+     18F6527+
    18F6585+     18F65J10+    18F65J11     18F65J15+
    18F65J50     18F65J90     18F6620+     18F6621+
    18F6622+     18F6627+     18F6680+     18F66J10+
    18F66J11     18F66J15+    18F66J16     18F66J50
    18F66J55     18F66J60     18F66J65     18F6720+
    18F6722+     18F67J10+    18F67J11     18F67J50
    18F67J60     18F8310+     18F8390+     18F83J11
    18F83J90     18F8410+     18F8490+     18F84J11
    18F84J15     18F84J90     18F8520+     18F8525+
    18F8527+     18F8585+     18F85J10+    18F85J11
    18F85J15+    18F85J50     18F85J90     18F8620+
    18F8621+     18F8622+     18F8627+     18F8680+
    18F86J10+    18F86J11     18F86J15+    18F86J16
    18F86J50     18F86J55     18F86J60     18F86J65
    18F8720+     18F8722+     18F87J10+    18F87J11
    18F87J50     18F87J60     18F96J60     18F96J65
    18F97J60

    EEPROM16     EEPROM8

    RF509AF      RF509AG      RF675F       RF675H
    RF675K

*Note: Early adopter support has been added for these devices since last release

+Note: These are the only PIC18 devices with peripheral library support.

THE PARTS CORRESPONDING TO THESE OPTIONS MAY NOT ALL BE COMMERCIALLY AVAILABLE.

These can be chosen through the introductory screen, on the command line, or in source file.

NOTES:

- The selections 16C5X, 16CXX, 17CXX, and 18CXX are supported as generic family indicators.
- The selections EEPROM8 and EEPROM16 are provided for generic memory product support. Read below for a description of how to use MPASM Assembler to generate files for programming Microchip Serial EEPROM devices.
- Use files 'MCP250XX.INC' and 'MCP250XX.ASM' as references for programming I/O expander (MCP250XX) devices. The file 'MCP250XX.ASM' is in the 'TEMPLATE\CODE' directory under 'MPLAB'.
  The standard header files have been updated to reflect these devices. One header file, MEMORY.INC, is provided for generic memory product support. Another header file, MCP250XX.INC, is provided for generic MCP250XX device support.
- The devices 18F2423, 18F2523, 18F4423, and 18F4523 were formerly known as 18LF2423, 18LF2523, 18LF4423, 18LF4523.
- Use the P12C509A.INC header file for the PIC12CR509A; Use the P16C620A.INC header file for the PIC16CR620A.
- Use the P16C74.INC header file for the PIC16CR74; Use the P16C77.INC header file for the PIC16CR77.
- Use the 16C5X.INC header file for the following device command line options:

                      16C52
                      16C54
                      16CR54
                      16C54A
                      16CR54A
                      16C54B
                      16CR54B
                      16C54C
                      16CR54C
                      16C55
                      16C55A
                      16C56
                      16C56A
                      16CR56A
                      16C57
                      16CR57A
                      16CR57B
                      16C57C
                      16CR57C
                      16C58A
                      16CR58A
                      16C58B
                      16CR58B

- Use the P16F5X.INC header file for the following device command line options:

                      16F54
                      16F57
                      16F59

3. # Operating System Support List

MPASMWIN.EXE is the 32-bit Windows version of MPASM Assembler which is distributed with MPLAB IDE and MPLAB C18. It is supported by the following platforms:

Windows 2000 and Windows XP

MPASM.EXE is the command-line version of MPASM Assembler which is distributed with MPLAB C18 only. It is supported by the following platforms:

Windows 2000 and Windows XP

NOTE: MPASM.EXE does not support device file names greater than an 8.3 format (e.g. p18f87J15.INC). Use MPASMWIN.EXE instead.

4. # Repairs and Enhancements Made Since v5.00

- ## Problems resolved between v5.06.04 and v5.10:

  (25130)
    An incorrect error message, referring to an odd number of bytes instead of an odd address, could be given when using an RES directive.
  (25131)
    In some cases assembly code written to reserve memory can reserve no memory and produce no raw data in the COFF file. In earlier versions, no warning was given when that would happen. Now the assembler will give a warning when such code reserves no memory.
  (MPASM-114)
    In support files for 16F883 and 16F884, __BADRAM was defined incorrectly.
  (MPASM-115)
    Support files for 12F615 were corrected to match the datasheet. Bits PORTA, TRISA and GPIO were added also.
  (MPASM-116)
    In support files for 16F616 and 16HV616, FVREN now refers to bit 4 of VRCON, conforming to the current naming convention.
  (MPASM-117)
    In support files for 16F913, 16F914, 16F916, and 16F917, GO now refers to bit 1 of ACDON0. This was required to use some assembler examples with these devices.
  (MPASM-118)
    Support files for 16F610 were corrected to match the datasheet.
  (MPASM-119)
    Support files for 16F616 and 16HV616 were corrected to match the datasheet.
    SRCON0 bit 4 renamed C2REN instead of C2SEN.
    SRCON1 bit 6 renamed SRCS0 instead of SRCS2.
  (MPASM-120)
    Support files for 12F609 and 12HV609 were corrected to match the datasheet. Some aliases were also added for compatibility with other devices.

- ## Enhancements between v5.06.04 and v5.10:

  Support for MPLAB REAL ICE Instrumented Trace is provided.

- ## Enhancements between v5.06 and v5.06.04:

  This revision of MPASM Assembler includes slight modifications to provide beta support for Instrumented Trace using MPLAB IDE and MPLAB REAL ICE In-Circuit Emulator System.
  These changes do not affect users not using MPLAB REAL ICE.

- ## Problems resolved between v5.05 and v5.06:

  (22612)
    Combining a typedef name with a 'rom' type qualifier in a declaration would assign the incorrect type if 'rom' followed the typedef name.
  (28973)
    Modifications were required in the support files for the 18F87J50 and 18F87J11 families.
    The following modifications were made to bit names in these support files:
    PMDATA1L renamed PMDIN1L
    PMDATA1H renamed PMDIN1H
    PMDATA2L renamed PMDIN2L
    PMDATA2H renamed PMDIN2H
    ADCON1 renamed ADCON0
    ADCON2 renamed ADCON1
    PADCFGH renamed ANCON0
    PADCFGL renamed ANCONH
    VREGSLP renamed REGSLP (in WDTCON register)
  (28979)
    Setting for 2.0V BOR is removed from support files for 18F1320.
  (29218)
    The descriptions of WRTB and WRTC configuration bits in support files for 18F2455 and 18F4455 were swapped, but have been corrected. The WRTB affects the write protection of the boot block, and the WRTC affects the configuration registers.
  (29219)
    The descriptions of WRTB and WRTC configuration bits in 18F2455 and 18F4455 were swapped in the MPLAB C18 Config Settings Addendum (DS51537 revision E). This document is now obsolete, and has been replaced with the help file, hlpPIC18ConfigSet.chm. The descriptions of these configuration bits in the help file in this release have been corrected.
  (29261)
    Support files for the 18F45K20 family of devices were changed to match the datasheet.
    The following changes were made:
    Register PSTCON renamed PSTRCON
    Added CKTXP (bit 4) and DTRXP (bit 5) to BAUDCTL
    Changed IPR2 (bit 5) from CM2IP to C2IP
    Changed IPR2 (bit 6) from CM1IP to C1IP
    Changed PIR2 (bit 5) from CM2IF to C2IF
    Changed PIR2 (bit 6) from CM1IF to C1IF
    Changed PIE2 (bit 5) from CM2IE to C2IE
    Changed PIE2 (bit 6) from CM1IE to C1IE
    Added TUN5 (bit 5) to OSCTUNE
    Added MSK0-MSK7 bits to SSPMSK register
    Updated configuration setting descriptions to match datasheet
  (29287)
    In support files for 18F4550, 18F4455, 18F2550, 18F2455, 18F4450, and 18F2450, bit name FCMEM in CONFIG1H was changed to FCMEN to match the datasheet, DS39632C.

- ## Problems resolved between v5.04 and v5.05:

  (28976)
    EEDAT was added as a register name, synonymous with EEDATA, in device support files for the 16F887 family of devices to match data sheet DS41291B.
  (28977)
    UFRMH bits 0-2 (FRM8 - FRM10) and UFRML bits 0-8 (FRM0 - FRM7) were added to device support files for the 18F4450 family of devices to match data sheet DS39760A.
  (28978)
    Device support files for the 18F85J90 family were modified to match data sheet DS39770A. The following changes were made:
    MEMCON register has been removed.
    DISCARD bit in ADCON0 has been removed.
    PSPIP bit in IPR1 register has been removed.
    LATE bit in LATE register has been removed.
    PSPIE bit in PIE1 register has been removed.
    PSPIF bit in PIR1 register has been removed.
    TRISE2 bit in TRISE register has been removed.
  (28489)
    RE3 (PORTE) is not available as input on devices 18F2331/2431, so it has been removed from .INC files.
  (28592)
    The .INC files for the 16F887 family of devices were missing the SSPMSK register and the SENDB bit in the TXSTA register.
  (28600)
    GPR locations from 0XE86-0XE89, 0XED6-0XED7 are unimplemented for the 18F97J60 family of devices and have been removed from the INC files.
  (28696)
    For 18F85J11, 18F84J11 and 18F83J11, the config directive for the External Memory Bus Configuration bits (MODE =) defined the bits in reverse order.
    Note: The workaround recommended in the Read Me file for MPASM v5.04 is no longer correct. Instead simply use the config directive as described in the Config Settings Help file.
  (28789)
    The RE3 bit of PORTE was missing from include files for the 18F2221 and 18F2321 devices.

- ## Problems resolved between v5.03 and v5.04:

  (28292)
    INTEDG2 bit of INTCON2<4>, was missing from INC files of 18F458 family devices.

- ## Problems resolved between v5.02 and v5.03:

  (27893)
    Bits were missing in the INC file for devices 18F1330 and 18F1230 according to data sheet DS39758A.
    SEVTEN (ADCON0<7>) and INTSRC (OSCTUNE<7>) have been added to the INC file.
    CVROE (CVRCON<6>) and FLTCON (FLTCONFIG) are unimplemented and were removed from the INC file.
    Correct bit names for DTCON have been added in the INC file.
  (24712)
    GPIO SFR bits GP3, GP2, GP1, and GP0 were not defined in the .INC files for the PIC10F20X devices. GPIO bit names have been added to 10F200/202/204/206/220/222.
  (27953)
    For 18F87J10, the config directive for the External Memory Bus Configuration bits (MODE =) defined the bits in reverse order.
    NOTE: The workaround recommended for this issue in a previous release, v5.02, is no longer valid.
    When using the config directive, please follow the instructions in the PIC18 Config Settings Help file:

    MM | instead of XM20 | for MCU mode - External bus disabled
    XM12 | instead of XM16 | for Extended MCU mode, 12-bit Address mode
    XM16 | instead of XM12 | for Extended MCU mode, 16-bit Address mode
    XM20 | instead of MM | for Extended MCU mode, 20-bit Address mode

    The MPLAB IDE settings were always correct. Only the config directive settings were incorrect.
  (27948)
    In the MPLAB IDE, macro expansion was incorrect in the Disassembly Listing display when the macro was defined in an include file.
  (17233)
    Errors in macros in an include file could be reported in an asm file that included it. If a macro was defined in an include file and called in an asm file, MPASM reported errors, warnings, and messages in the macro definition as errors, warnings, and messages in the asm file, but using line numbers from the include file.
  (28136)
    Configuration word changes for 18F2585/2680/4584/4680 devices:
    OSC setting - ERC value has been removed. Use RC
    OSC setting - ERC1 value has been removed. Use RC
    FCMENB setting has been changed to FCMEN
    IESOB setting has been changed to IESO
    BOR setting has been changed to BOREN
    BORV setting value 20 has been changed to 3
    BORV setting value 27 has been changed to 2
    BORV setting value 42 has been changed to 1
    BORV setting value 45 has been changed to 0
    Additional Configuration word changes for 18F2585/4585:
    CP3 setting has been removed
    WRT3 setting has been removed
    EBTR3 setting has been removed
    SFR changes for 18F2585/2680/4585/4680 .INC files:
    RB0 is bit 0 in PORTB and bit 4 in other SFRs so use "RB0_SFRname" where SFRname is the name of the SFR
    RB1 is bit 1 in PORTB and bit 5 in other SFRs so use "RB1_SFRname" where SFRname is the name of the SFR
    CANSTAT bit 1 has been renamed from ICODE0 to ICODE1
    CANSTAT bit 2 has been renamed from ICODE1 to ICODE2
    CANSTAT bit 3 has been renamed from ICODE2 to ICODE3
    ICODE0_CANSTAT_R0x where x is 0-9 is now ICODE0
    ICODE1_CANSTAT_R0x where x is 0-9 is now ICODE1
    ICODE2_CANSTAT_R0x where x is 0-9 is now ICODE2
    RXRTRRO is bit 3 in RXB1CON and RXB0CON but bit 5 in BxCON where x is 0-5 so use "RXRTRRO_SFRname" where SFRname is the name of the SFR.
    T3ECCP1 (on T3CON) was incorrectly defined as bit 5 but has been corrected to bit 6.
  (26624)
    In 18F8680.h the FIFOWMIF bit was missing from PIR3.
  (27988)
    Added PORTE bit RE3 to 18F2431 and 18F2331 device header files and INC files.
  (27620)
    Support files for the 18F4580 family (18F4580/2580/2480) were corrected to match the data sheet DS39637A.
    Configuration word changes for 18F2480/2580/4480/4580:
    OSC setting - ERC value has been removed use RC
    OSC setting - ERC1 value has been removed use RC
    FCMENB setting has been changed to FCMEN
    IESOB setting has been changed to IESO
    BOR setting has been changed to BOREN
    BORV setting value 20 has been changed to 3
    BORV setting value 27 has been changed to 2
    BORV setting value 42 has been changed to 1
    BORV setting value 45 has been changed to 0
    Additional Configuration Word changes for 18F4480:
    CP2 and CP3 settings have been removed
    WRT2 and WRT3 settings have been removed
    EBTR2 and EBTR3 settings have been removed
    SFR changes for 18F2480/2580/4480/4580 .INC files:
    RB0 is bit 0 in PORTB and bit 4 in other SFRs so use "RB0_SFRname" where SFRname is the name of the SFR.
    RB1 is bit 1 in PORTB and bit 5 in other SFRs so use "RB1_SFRname" where SFRname is the name of the SFR.
    CANSTAT bit 1 has been renamed from ICODE0 to ICODE1
    CANSTAT bit 2 has been renamed from ICODE1 to ICODE2
    CANSTAT bit 3 has been renamed from ICODE2 to ICODE3
    ICODE0_CANSTAT_R0x where x is 0-9 is now ICODE0
    ICODE1_CANSTAT_R0x where x is 0-9 is now ICODE1
    ICODE2_CANSTAT_R0x where x is 0-9 is now ICODE2
    RXRTRRO is bit 3 in RXB1CON and RXB0CON but bit 5 in BxCON where x is 0-5 so use "RXRTRRO_SFRname" where SFRname is the name of the SFR.
    T3ECCP1 (on T3CON) was incorrectly defined as bit 5 but has been corrected to bit 6.
    EXIDEN (on RXF1SIDL) was incorrectly defined as bit 1 but has been corrected to bit 3.
    EXIDE (on B1SIDL) was incorrectly defined as bit 1 but has been corrected to bit 3.
    Additional SFR changes for 18F4480 .INC files:
    RXFxSIDL where x is 0-5, bit EXIDEN was changed from bit 1 to bit 3 to correctly match the data sheet. Use EXIDEN instead of "EXIDEN_SFRname".
    RXMxSIDL where x is 0-1, bit 3 is now EXIDEN instead of "EXIDEN_SFRname".
    Additional SFR changes for 18F4580 .INC files:
    RXFxSIDL where x is 6-15, bit 3 is now EXIDE instead of "EXIDE_SFRname".
    BxSIDL where x is 0-4, bit 3 is now EXIDE instead of "EXIDE_SFRname".
    RXFxSIDL where x is 0-5, bit 3 is now EXIDE or EXIDEN instead of "EXIDE_SFRname" or "EXIDEN_SFRname".
    RXMxSIDL where x is 0-1, bit 3 is now EXIDEN instead of "EXIDEN_SFRname".
    TXBxSIDL where x is 0-2, bit 3 is now EXIDE instead of "EXIDE_SFRname".

- ## Problems resolved between v5.01 and v5.02:

  (27432)
    The 18F87J10 family (18F65J10/65J15/66J10/66J15/67J10/67J15, 18F85J10/85J15/86J10/86J15/87J10) include files had _config information, but MPASM does not support the _config directive for them.
  (27700)
    In the include files for 16F873A, 16F874A, and 16F876A, the INTCON bits TMR0IE and TMR0IF, and the ADCON1 bit ADCS2 have been added. For 16F877A, the ADCON1 bit ADCS2 has been added. The include files now match the information in DS39582B.
  (27689)
    In the include file for 16F872, INTCON bits TMR0IE and TMR0IF have been added.
  (27949)
    For 18F87J10, 18F86J10, or 18F97J60, attempting to access external memory gave an error that the argument was out of range.

- ## Problems resolved between v5.00 and v5.01:

  (27358 / 27515)
    The new config directive causes unimplemented bits to become 0, but should be left a '1'.
    Unimplemented/reserve bits are now included in the mask and default settings when the bit must be maintained set.
    Following are the devices and configuration words that were corrected:

            18C442  CONFIG1H, CONFIG4L
            18C452  CONFIG1H, CONFIG4L
            18C658  CONFIG1H, CONFIG4L
            18C858  CONFIG1H, CONFIG4L
            18F242  CONFIG5L, CONFIG6L, CONFIG7L
            18F442  CONFIG5L, CONFIG6L, CONFIG7L
            18F6525 CONFIG3L, CONFIG5L, CONFIG6L, CONFIG7L
            18F6621 CONFIG3L
            18F8525 CONFIG5L, CONFIG6L, CONFIG7L
            18F2220 CONFIG5L, CONFIG6L, CONFIG7L
            18F4220 CONFIG5L, CONFIG6L, CONFIG7L
            18F2439 CONFIG5L, CONFIG6L, CONFIG7L
            18F4439 CONFIG5L, CONFIG6L, CONFIG7L
            18F2525 CONFIG5L, CONFIG6L, CONFIG7L
            18F4525 CONFIG5L, CONFIG6L, CONFIG7L
            18F6520 CONFIG2L, CONFIG2H, CONFIG3L, CONFIG3H, CONFIG5L,
                    CONFIG6L, CONFIG7L
            18F6620 CONFIG3L, CONFIG5L, CONFIG6L, CONFIG7L
            18F6720 CONFIG3L
            18F8520 CONFIG2L, CONFIG2H, CONFIG3H, CONFIG5L, CONFIG6L,
                    CONFIG7L
            18F8620 CONFIG5L, CONFIG6L, CONFIG7L

    18F2331 and 18F2431 had extra settings removed that are unimplemented on these devices as follows:
    CONFIG5L - Removed settings for CP2 and CP3.
    CONFIG6L - Removed settings for WRT2 and WRT3.
    CONFIG7L - Removed settings for EBTR2 and EBTR3.
    In addition, 18F2525, 18F2620, 18F4525 and 18F4620 had their value names modified in CONFIG2L for the BORV setting to be 3 (for Minimum setting), 2, 1, and 0 (for Maximum setting).
  (27518)
    SWDTEN bit should be 0th bit, but the bit location was 7 on 18F4321 family devices. For all devices, changed SWDTEN on SFR WDTCON from bit 7 to bit 0.
  (27519)
    18F4321 family device support changes needed to match the data sheet DS39689A.
    All devices
    -----------
    Added SFR ECCP1DEL
    Added SFR HLVDCON
    Added missing bits 4 and 5 (TXCKP and RXDTP) to BAUDCON
    Added missing bits 6 and 7 (P1M0 and P1M1) to CCP1CON
    Added missing bit 2 (HLVDIP) to IPR2
    Added missing bit 2 (HLVDIE) to PIE2
    Added missing bit 2 (HLVDIF) to PIR2
    Added missing bits 0-4 (SP0, SP1, SP2, SP3, SP4) to STKPTR
    Added missing bits 1-5 (ADMSK1, ADMSK2, ADMSK3, ADMSK4, ADMSK5) in SSPCON2
    Changed CONFIG1H FSCM to FCMEN
    Changed CONFIG2L BORV settings to 3 (Minimum setting), 2, 1, and 0 (Maximum setting)
    Corrected CONFIG3H default settings
    Changed CONFIG3H LPT1OSC setting names from LOW and HIGH to ON and OFF to be consistent with other devices
    Changed CONFIG3H PBAD to PBADEN
    Corrected CONFIG4L default settings
    Updated Configuration descriptions to match data sheet
    18F2221/18F2321
    ---------------
    Removed ICPORT from CONFIG4L - unimplemented on these devices.
  (27612)
    18F4520 family device support changes needed to match the data sheet DS39631A.
    All devices
    -----------
    Updated Configuration descriptions to match data sheet
    Change CONFIG2L BORV settings to 3 (Minimum setting), 2, 1, and 0 (Maximum setting)
    18F4520
    -------
    Removed SFR EEADRH - unimplemented on this device
    18F4420
    -------
    Removed SFR DEBUG - unimplemented on this device
    Removed - SFR TRISE bits TRISE7, TRISE6, TRISE5, TRISE4 - not in data sheet
    Removed - SFR PORTB bits DAD5, DAD6, DAD7 - not in data sheet
    CONFIG3H - added missing setting for LPT1OSC
    CONFIG4L - changed setting name ENHCPU to XINST
    CONFIG5L, CONFIG6L, CONFIG7L - corrected default settings for unimplemented but maintained set bits
    18F2520
    -------
    Added missing SFRs PWM1CON and ECCP1AS
    Removed SFR EEADRH
    CONFIG3H - added missing setting for LPT1OSC
    CONFIG4L - changed setting name ENHCPU to XINST
    18F2420
    -------
    Removed SFR DEBUG - unimplemented on this device
    Added missing SFRs PWM1CON and ECCP1AS
    Removed - SFR PORTB bits DAD5, DAD6, DAD7 - not in data sheet
    CONFIG3H - added missing setting for LPT1OSC
    CONFIG4L - changed setting name ENHCPU to XINST
    CONFIG5L, CONFIG6L, CONFIG7L - corrected default settings for
    unimplemented but maintained set bits
  (27614)
    18F4550 family device support changes needed to match the data sheet DS39632B.
    All devices
    -----------
    Corrected bit positions of TUN3 and TUN4 in OSCTUNE
    UFRMH and UFRML - Add bit names to these register
    Updated Configuration descriptions to match the data sheet
    In CONFIG2L, changed BORV settings to 3 (Minimum setting), 2, 1, and 0 (Maximum setting)
    18F4550
    -------
    Added bits to CCP1DEL and CCP1AS
    Corrected default values in CONFIG1L, CONFIG2L and CONFIG3H
    18F4455
    -------
    Added bits to CCP1DEL and CCP1AS
    Corrected default values in CONFIG1L, CONFIG2L and CONFIG3H
    Removed CP3 from CONFIG5L, WRT3 from CONFIG6L and EBTR3 from CONFIG7L - they are not available in this device
    18F2550
    -------
    Added ECCP1AS and ECCP1DEL and their bits
    Corrected default values in CONFIG1L, CONFIG2L and CONFIG3H
    Removed ICPRT from CONFIG4L - it is not available in this device
    18F2455
    -------
    Added ECCP1AS and ECCP1DEL and their bits
    Corrected default values in CONFIG1L, CONFIG2L and CONFIG3H
    Removed ICPRT from CONFIG4L, CP3 from CONFIG5L, WRT3 from CONFIG6L and EBTR3 from CONFIG7L - they are not available in this device
  (27615)
    18F8410 family device support changes needed to match the data sheet DS39635A.
    18F6310, 18F6410, 18F8310 and 18F8410
    -------------------------------------
    Removed EEIP from SFR IPR2 - unimplemented in data sheet
    Removed EEIE from SFR PIE2 - unimplemented in data sheet
    Removed EEIF from SFR PIR2 - unimplemented in data sheet
    Removed TUN5 from SFR OSCTUNE - unimplemented in data sheet
    Updated Configuration descriptions to match data sheet
    Changed CONFIG2L BORV settings to 3 (Minimum setting), 2, 1, and 0 (Maximum setting)
    CONFIG3H - corrected default settings for unimplemented but maintain set bits
    18F6310 and 18F6410
    -------------------
    CONFIG3L is unimplemented but to keep the default values set it has been added. No settings are available so it can not be changed
    Changed CONFIG3H PORTTBE setting to PORTE
    CONFIG7L is unimplemented for these devices but to keep the default values set it will remain but the EBTR setting is removed
  (27618)
    18F87J10 family device support changes needed to match the data sheet DS39663A.
    All devices
    -----------
    STKPTR - added bits SP4, SP3, SP2, SP1, SP0
    INTCON2 - added bit INT3IP
    ADCON0 - added bit ADCAL
    CCP1CON - added bits P1M1, P1M0
    CCP2CON - added bits P2M1, P2M0
    CCP3CON - added bits P3M1, P3M0
    ECCP1AS - added bits PSS1AC0, PSS1AC1, ECCP1AS0, ECCP1AS1, ECCP1AS2, ECCP1ASE
    EECON2 - added SFR
    EECON1 - added SFR and bits FREE, WRERR, WREN, WR
    OSCTUNE - corrected size of PLLEN
    BAUDCON1 - added bit RCIDL
    BAUDCON2 - added bit RCIDL
    ECCP1DEL - added bits P1DC0, P1DC1, P1DC2, P1DC3, P1DC4, P1DC5, P1DC6, P1RSEN
    ECCP3AS - added bits PSS3AC0, PSS3AC1, ECCP3AS0, ECCP3AS1, ECCP3AS2, ECCP3ASE
    ECCP3DEL - added bits P3DC0, P3DC1, P3DC2, P3DC3, P3DC4, P3DC5, P3DC6, P3RSEN
    ECCP2AS - added bits PSS2AC0, PSS2AC1, ECCP2AS0, ECCP2AS1, ECCP2AS2, ECCP2ASE
    ECCP3DEL - added bits P2DC0, P2DC1, P2DC2, P2DC3, P2DC4, P2DC5, P2DC6, P2RSEN
    CONFIG1H - correct default settings
    Updated configuration descriptions to match data sheet
    18F87J10/86J15/86J10/85J15/85J10
    --------------------------------
    ECCP1AS - added bits PSS1BD0, PSS1BD1
    PORTG - added bits RDPU, REPU, RJPU
    18F67J10/66J15/66J10/65J15/65J10
    --------------------------------
    Removed MEMCON - unimplemented on these devices
    PORTG - added bits RDPU, REPU
    Added CONFIG3L with no settings to maintain default values
    CONFIG3H - correct default settings
  (27621)
    18F4610 family device support changes needed to match the data sheet DS39636A.
    All devices
    -----------
    Updated Configuration descriptions to match data sheet
    Change CONFIG2L BORV settings to 3 (Minimum setting), 2, 1, and 0 (Maximum setting)
    18F4610
    -------
    CONFIG3H - added missing setting for LPT1OSC
    CONFIG4L - changed setting name ENHCPU to XINST
    18F4515
    -------
    CONFIG3H - added missing setting for LPT1OSC
    CONFIG4L - changed setting name ENHCPU to XINST
    CONFIG5L, CONFIG6L, CONFIG7L - corrected default settings
    18F4510
    -------
    CONFIG5H, CONFIG6H - corrected default settings
    18F4410
    -------
    CONFIG3H - added missing setting for LPT1OSC
    CONFIG4L - changed setting name ENHCPU to XINST
    CONFIG5L, CONFIG5H, CONFIG6L, CONFIG6H, CONFIG7L - corrected default settings
    18F2610
    -------
    CONFIG3H - added missing setting for LPT1OSC
    CONFIG4L - changed setting name ENHCPU to XINST
    18F2515
    -------
    CONFIG3H - added missing setting for LPT1OSC
    CONFIG4L - changed setting name ENHCPU to XINST
    CONFIG5L, CONFIG6L, CONFIG7L - corrected default settings
    18F2510
    -------
    CONFIG5H, CONFIG6H - corrected default settings
    18F2410
    -------
    CONFIG3H - added missing setting for LPT1OSC
    CONFIG4L - changed setting name ENHCPU to XINST
    CONFIG5L, CONFIG5H, CONFIG6L, CONFIG6H, CONFIG7L - corrected default settings
  (27622)
    18F44J10 family device support changes needed to match the data sheet DS39682A.
    All devices
    -----------
    Updated configuration descriptions
    18F45J10/18F44J10
    -----------------
    Added bit 7 - P1M1 and bit 6 - P1M0 to CCP1CON
  (27623)
    18F8722 family device support changes needed to match the data sheet DS39646B.
    All devices
    -----------
    Updated Configuration descriptions to match data sheet
    Change CONFIG2L BORV settings to 3 (Minimum setting), 2, 1, and 0 (Maximum setting)
    18F6527
    -------
    CONFIG3H - changed setting name PORTB to PORTE
    CONFIG5L, CONFIG6L, CONFIG7L - corrected default settings
    18F6622
    -------
    CONFIG3H - changed setting name PORTB to PORTE
    CONFIG5L, CONFIG6L, CONFIG7L - corrected default settings
    18F6627
    -------
    CONFIG3H - changed setting name PORTBE to PORTE
    CONFIG5L, CONFIG6L, CONFIG7L - corrected default settings
    18F6722
    -------
    CONFIG3H - changed setting name PORTBE to PORTE
    18F8527
    -------
    CONFIG3H - changed setting name PORTB to PORTBE
    CONFIG5L, CONFIG6L, CONFIG7L - corrected default settings
    18F8622
    -------
    CONFIG3H - changed setting name PORTB to PORTBE
    CONFIG5L, CONFIG6L, CONFIG7L - corrected default settings
    18F8627
    -------
    CONFIG5L, CONFIG6L, CONFIG7L - corrected default settings
  (27639)
    18F8490 family device support changes needed to match the data sheet DS39629B.
    18F6390, 18F6490, 18F8390 and 18F8490
    -------------------------------------
    Removed EEIP from SFR IPR2 - unimplemented in data sheet
    Removed EEIE from SFR PIE2 - unimplemented in data sheet
    Removed EEIF from SFR PIR2 - unimplemented in data sheet
    Removed TUN5 from SFR OSCTUNE - unimplemented in data sheet
    Updated Configuration descriptions to match data sheet
    Changed CONFIG2L BORV settings to 3 (Minimum setting), 2, 1, and 0 (Maximum setting)
    CONFIG3H - corrected default settings
    Removed CONFIG7L it is not implemented in these devices
  (27611)
    16F946 device support changes needed to match the data sheet DS41265A.
    Added ANSEL bits ANS0-ANS7
    Added SFRs EEADRH and EEADRL
  (27627)
    16F59 device support change needed to match the data sheet DS41213A.
    Corrected MAXRAM to H'0FF'
  (27628)
    16F685 device support change needed to match the data sheet DS41262A.
    Added PCON bit NOT_BOR
  (27629)
    16F917 family device support changes needed to match the data sheet DS41250D.
    Added ANSEL bits ANS0-ANS7
    Added SFR EEADRH and EEADRL
  (27645)
    10F206 family device support changes needed to match the data sheet DS41239B.
    Added comment to the configuration word setting _IntRC_OSC that it is for backward compatibility only.
  (27665)
    MPASM appeared to assemble code past the end of memory for 10F222. Corrected the memory size of 10F222 from 0x3FF to 0x1FF and memory size of 10F220 from 0x1FF to 0xFF.
  (23454)
    In MPLAB IDE, the disassembly window now shows macro definitions along with code.
  (27721)
    The EECON2 register was shown to be included in the bad ram location in the include file for 16F946.

5. # Known Problems

The following is a list of known problems. For a list of limitations, please see MPASM Assembler Help, Troubleshooting, Assembler Limitations.

(1008)
  There are no warnings when overflow or underflow occurs during expression evaluation.
(16921 / 23355)
  MPASM Assembler generates a COD file which cannot handle line number information for program memory addresses greater than 64K. This adversely affects debugging.
  The workaround is to generate a .O file, link with MPLINK Linker, and debug in MPLAB IDE v6.0 or greater.
  Here is an example of what might happen. Suppose the source is

              ORG 0xF00000
              DB 0xAB ; eedata
              ORG 0x0
              MOVLW 3
              MOVLW 4

  The disassembly window in MPLAB IDE may appear this way:

              Disassembly               Source
                                        ORG 0xF00000
              000000 0E03 MOVLW 3       DB 0xAB
                                        ORG 0x0
                                        MOVLW 3
              000000 0E04 MOVLW 4       MOVLW 4

  The source line for address 0xF00000 has been associated with the code at address 0x0.
(17236)
  Using a symbol other than one introduced by the DEFINE directive as the operand of an IFDEF or IFNDEF directive causes the IFDEF/IFNDEF to possibly be evaluated incorrectly.
(18510)
  A file register operand which is greater than the absolute max ram address does not generate a message of any kind.
  For example,

              LIST P=18F452
              MOVWF 0x1000
              END

  will assemble without warning.
(18811)
  MPASMWIN generates incorrect code for 'goto' targeting a local label.
  A 'goto' targeting a local label is generating an instruction where the file register field is set to 0 instead of the local label's value.
  The workaround is to use the "$ + n" expression as the target of the 'goto'.
(19703)
  The Japanese directory delimiter character on Windows XP-J and Windows ME-J is not accepted by MPASM.
  The workaround is to invoke MPASM on the command line with a source file path which does not contain any directory delimiters.
(19788)
  MPASM.EXE has problems accepting a file name which contains a space just before the '.' character of the extension. For example,

              MPASM.EXE /Q "TEST .ASM"

  will cause a 'file not found' error, but for MPASMWIN.EXE, this is acceptable.
(20776)
  The return value of the MPASMWIN.EXE process (returned by 'spawnvp') does not get stored in the DOS environment variable ERRORLEVEL.
(20986)
  When assembling with the '/o' option, a duplicate address label declaration causes no error, warning, or message. For example, the program fragment

              U1 IDATA
              X  DB 1
              U2 IDATA
              X  DB 2
                  CODE
                 MOVWF X

  assembles quietly, but the definition of X which is used in the MOVWF instruction is not well defined.
(21677)
  When using MPASM.EXE without the '/q' option, and an output file is specified to be in a nonexistent directory, then the output file is not generated, but no error message is emitted.
  When the '/q' option is used, the message "Couldn't open file..." is emitted. This can be confusing.
(21798)
  The length of the command line argument string to mpasm.exe is limited to about 120 characters. Anything beyond that is truncated.
(21988)
  MPASM cannot handle a source file with UNIX-style line endings. Please convert line endings to the DOS (CR/LF) format.
(22227)
  Error messages are not emitted to standard out.
(22387)
  MPASM cannot assemble files in Unicode format.
(22541)
  A warning is not emitted if the operand for the PUSHL instruction is less than -128, only if it is less than -255. A warning should be emitted if the operand is less than -128, since the operand is 8 bits wide.
(22660)
  When assembling with '/o' and the operand of a DT directive is relocatable but more than 8 bits wide, the linker will fill both bytes of the directive with 16 bits of the operand (instead of truncating the operand to 8 bits for a RETLW instruction):

              UDATA 0x124
              X RES 1
              CODE 0x100
              DT X

  will generate 0x0124 at address 0x100 instead of 0x3424 (RETLW 0x24).
(23071)
  The LIST n=nnn directive does not properly format the listing file.
(23490)
  As MPASM rescans macro expressions, it searches the substituted arguments for parameters. E.g.,

              #define F(X,Y) X + Y
              Y EQU 2
              movlw F(Y,1)

  will yield movlw 2 instead of movlw 3. After Y is substituted in place of X, it is replaced itself by the second argument upon rescanning.
(23747)
  MAXROM is defined incorrectly for 17C43.
  The following source code:

              LIST p=17c43
              ORG 0xFFE
              NOP
              ....
              ORG 0xFFFE
              NOP
              ....
              END

  Should cause the assembler to emit warning[220] when the code crosses 0x1000. Instead the assembler emits a warning when the code crosses 0x10000.
  Also note that "__maxrom 0xFFF" causes the assembler to emit the following error:
  `
  Error[126] MAXROM.ASM 3 : Argument out of range (must be greater than or equal to 65535)
  `
  As a workaround:

              LIST p=17c43
              __maxrom 0xFFFF
              __badrom 0x1000 - 0xFFFF
              ORG 0xFFE
              NOP
              ....
              END

  Causes the assembler to emit "Invalid ROM location," warning[228], when the code crosses 0x1000.
(24275)
  After a file is compiled, the debug information does not seem to be loaded.
(24560)
  No error or warning is produced for the following code:

              bsf   ,1
              END

  This assembles as if "bsf 0,1" was given.
(24794)
  MPASM generates invalid PIC18 relocation for $+<odd offset>. The following code, containing an invalid goto destination address, assembles without error when generating an object file (18f452):

                            code 0
                            bra start

              startscn      code 0x100
              start         nop
                            goto $-1
                            bra $

                            end

  causing a link-time error:
  `
  Error - file 'C:\test\mpasm\gotoneg1.o', section 'startscn', Symbol '_startscn_0102' is not word-aligned.
  It can not be used as the target of a call or goto instruction.
  `
  However, the assembler generates a warning when assembling equivalent code in absolute mode:

                            org 0
                            bra start

                            org 0x100
              start         nop
                            goto $-1
                            bra $

                            end

  `Warning[226] C:\TEST\MPASM\GOTONEG1.ASM 8 : Destination address must be word aligned
  `
(26223)
  MPASM does not correctly handle Windows CLI and DOS command line string limitations and error diagnostics can be ambiguous or absent.
(26588)
  The Processor Type list in the MPASM.EXE GUI (DOS executable) doesn't display all of the processors. Many 16xxx and all 18xxx processors are not shown.
  The workaround is to use the MPASMWIN.EXE GUI.
(27088)
  MPASM may generate an invalid COFF file when passing an undefined constant as a macro parameter.
  For example:

              RM          MACRO Name,Size
                          LOCAL i    =0
              Name        RES   0
                          GLOBAL Name
                          WHILE i <Size
              Name#v(i)     RES 1
                            i +=1
                          ENDW
                          ENDM
              myuscn      UDATA
                          RM hello,myconstsz ; Should cause an assembly error
              myconstsz  equ  2
                          CODE
                          lfsr  0,hello0
                          END

  Assembly of this code causes only a warning, but MPLINK gives an error message "reloc[0] has an invalid r_symndx." while trying to link the COFF file.
  MPASM should give an error.
  To avoid this problem, the code should define 'myconstsz' before calling the macro, as shown:

              myconstsz  equ 2
              RM hello, myconstsz

(27165)
  MPASM does not give an error when ENDIF is missing; it gives only a warning.
  With a macro like:

              IF (CONST)
              ; no ENDIF

  MPASM assembles it and gives no error, only a warning.
(27914)
  The assembler gives an error when the FILL macro is used with Address - $. For example, the following code:

              #include <p16f877a.inc>

              cfill code 0x7f
              fill (clrf PCLATH), H'4FF'-$
              end

  causes the assembler to give this error:

              Operand contains unresolvable labels or is too complex

(28228)
  Running the assembler on a file with a '.' in the name, other than the '.' separating the file extension from the base name, for example foo.bar.asm, results in a DOS error:

              File not found.

  Any resulting intermediate or output files will not include the portion of the file name after the first '.' For example, the file name above may cause files named foo.ERR, foo.COD, or foo.LST to be created.

6. # Using MPASM Assembler

Create your source code with any text editor. The file should contain ASCII text only. Assemble your code with the command line:

            mpasm <file>[.asm]

A version of MPASM Assembler is also available for Windows. To invoke this assembler, execute:

            mpasmwin

from within Windows. You will then be given a Windows interface window. Help on using the interface is provided on-line. MPASMWIN.EXE can also be invoked with parameters or through drag-and-drop. In these cases, the interface screen is not displayed and assembly begins immediately.

Correct any syntax problems, referring to the MPASM Assembler, MPLINK Object Linker, MPLIB Object Librarian User's Guide(DS33014) for syntax help. MPASM assembles with INHX32 as the default hex output, and generates a listing file, error file, and .COD file.

Serial EEPROM Support:

Two "processor" selections are provided to generate byte data - EEPROM8 and EEPROM16. Both generate data in terms of bytes, but EEPROM8 considers a "word" to be 8 bits wide, while EEPROM16 considers a "word" to be 16 bits wide. The "program counter" is always incremented in terms of bytes.

The default size for memory products is 128 bytes. This can be overridden by using the LIST M=<max address> directive. Note that <max address> is always evaluated as a decimal number. The header file MEMORY.INC is provided to define the maximum address for available memory devices. The format of the defined symbols is _<device>; for example, to set the maximum memory size for a 24LCS21, use the directive LIST M=_24LCS21.

The following data generation directives are supported for memory products:

            DW           FILL        ORG

The behavior of other data generation directives is not guaranteed. All other directives are unchanged.

An example of generating a file for programming a memory device is as follows:

    ;*************************************************
    ; Generate data for a 8-bit wide memory device.

            LIST    P=EEPROM8, R=DECIMAL
            INCLUDE "MEMORY.INC"
            LIST    M=_24LCS21

    #DEFINE MAX_VALUE       255

            ORG     0

    ;-------------------------------------------------
    ; Create a packed-byte, null terminated string.

            DW      "Hello World", 0

    ;-------------------------------------------------
    ; Create data representing a line.  The X position
    ; is implied from the position of the data in the
    ; device.  The Y values are stored in the device.

    ; First, define an equation for the line.

    #DEFINE Line( X )       Slope * X + Y_Intercept

    ; Now define the values needed for the equation.

    Slope                   EQU     10
    Y_Intercept             EQU     5

    ; Declare and initialize the X and Y values.

            VARIABLE        X = 0, Y = Line( X )

    ; Generate values until the maximum Y value is
    ; reached or the device is filled up.

            WHILE (Y <= MAX_VALUE) && ($ <= _24LCS21)
               DW   Y
    X = X + 1
    Y = Line( X )
            ENDW

    ;-------------------------------------------------
    ; Perform some checking based on the line data
    ; generated above.

    ; If the device filled up before the end of the
    ; line was reached, generate an error. Otherwise,
    ; if the device is almost out of room, generate a
    ; message.

            IF (Y < MAX_VALUE)
               ERROR        "Device is full."
            ELSE
               IF (($+10) > _24LCS21)
                  MESSG     "Device is nearly full."
               ENDIF
            ENDIF

    ;-------------------------------------------------
    ; Fill the rest of the device with zeroes.

            FILL    0, _24LCS21 - $ + 1

            END

CLRW COMMAND:

The CLRW encoding was changed on all 14-bit core devices from 0x0100 to 0x0103 (v1.40 and later). This will not affect the expected operation of the instruction, but it will change the value for the instruction in the hex file and therefore the checksum.

WARNING MESSAGE:

The text for Message #302 was modified to explain more clearly that bank indication bits are stripped when assembling instructions that access file registers. The appropriate bank must be selected by the appropriate bank selection bits. For example, 14-bit core devices contain the lower seven bits of the file register address in the opcode, with two bank selection bits in the STATUS register. The message was changed from:

            Argument out of range. Least significant bits used.

to:

            Register in operand not in bank 0. Ensure that bank bits are correct.

END DIRECTIVE:

Take care to not use the END directive in a macro. If the END directive is encountered in a macro, it can cause the assembler to loop indefinitely. Macros should be terminated with the ENDM directive.

7. # Customer Support

Microchip provides online support via our home page at:
http://www.microchip.com
Technical support is available through the web site at:
http://support.microchip.com
A forum for discussion of Microchip products and tools is available at:
http://forum.microchip.com