Academic Experience:

• Ph.D., Integrated Circuits and Systems, Electrical Engineering, IIT Bombay (2021-present)
• B.Tech. + M.Tech. Dual Degree, Electrical Engineering (Microelectronics), IIT Bombay (2014-2019)

Area of Interest:

• Radio frequency IC design, Analog and Mixed-Signal IC design

M.Tech. Thesis: 

• A Tri-Band Fractional-N Phase-Locked Loop for NavIC Receiver

Designed a compact, low phase noise Fractional-N PLL for Indian Regional Navigation Satellite System (IRNSS) receiver. It generates LO frequency for navigation frequency bands L1/L2/L5/S with 1.1-2.5 GHz frequency range. This PLL is integrated with IRNSS receiver front end ‘DHRUVA’ and is fabricated in UMC 65 nm CMOS technology.

Work experience:

• Scientist / Engineer ‘SC’, ISRO Inertial Systems Unit, Indian Space research Organisation (2019-2020)
• Served as an ASIC design engineer and contributed to the design and verification of ICs for launch vehicle and space-craft electronics of ISRO. 

Email: 

• ajinkyakharalkar[AT]gmail.com
• ajinkyak[AT]iitb.ac.in