D. Mukhopadhyay, P. K. Basu, V.Ramgopal Rao,"Physics and Technology:Towards Low-Power DSM Design", Tutorial to be conducted at the 18 th International Conference on VLSI Design, Jan 3-7, 2005, Calcutta,India

Neeraj K. Jha, P. Sahajananda Reddy and V.Ramgopal Rao, "A New Drain Voltage Enhanced NBTI Degradation Mechanism", Accepted for oral presentation, International Reliability Physics Symposium (IRPS),April 17 ~V 21, 2005, San Jose, California, USA

V.Ramgopal Rao, "CMOS Device Design for Mixed Signal Applications"Short course to be conducted at the 16th Asia Pacific Microwave Conference (APMC-04), Dec 15-18, 2004 New Delhi (Invited)

D. R. Nair, N. R. Mohapatra, S. Mahapatra, S. Shukuri and J. Bude,"Effect of P/E cycling on drain disturb in Flash EEPROMs under CHEand CHISEL operation", IEEE Trans. Device and Materials Reliability,v.4, p.32, 2004.

D. R. Nair, S. Mahapatra, S. Shukuri and J. Bude, "Drain disturb
during CHISEL programming of NOR Flash EEPROMs ~V Physical mechanisms and impact of technological parameters", IEEE Trans. Electron Devices, v.51, p.701, 2004.
 

S. Mahapatra, M. A. Alam, P. Bharath Kumar, T. R. Dalei and D. Saha,"Mechanism of Negative Bias Temperature Instability in CMOS Devices:Degradation, Recovery and Impact of Nitrogen", Invited paper,International Electron Devices Meeting (IEDM), San Francisco, CA,USA, 2004.

V.Ramgopal Rao, "Current Trends in Hybrid Micro-Nano-Molecular
Electronics", International Microelectronics and Packaging Society
(IMAPS) INDIA National Conference (IINC)", Bangalore November 27-28,2004 (Invited)

K. Narasimhulu, Siva G.Narendra, and V. Ramgopal Rao, ~SEffect of Process Variations on Device and Circuit Parameters with LAC/DH MOSFETs~T, proceedings of the 17 th IEEE International Conference on VLSI Design, January 7-9, 2004, Mumbai, India

Bhawna Tomar, V. Ramgopal Rao, "Sub-threshold Swing  Degradation due to Localized Charge Storage in SONOS Memories",Proceedings of 11 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, July 5-8, 2004

Hinshcu, Taiwan Neeraj Jha, V.Ramgopal Rao, "Understanding the NBTI Degradation in Halo- Doped Channel p-MOSFETs" Proceedings of the 11th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, July 5-8, 2004 Hinshcu, Taiwan

 V.Ramgopal Rao, "System on Chip using CMOS", Workshop on Nanotechnology, VNIT, Nagpur, Sponsored by the IEEE Bombay Section,July 15-16, 2004 (Invited)

K. Narasimhulu, V. Ramgopal Rao, "Understanding the Impact of Process Variations on Analog Circuit Performance with HaloChannel Doped Deep Sub-Micron CMOS Technologies", Proceedings of the 35th International Conference on Solid State Devices and Materials (SSDM 2004), Tokyo,Japan, September 15-17, 2004

Pradeep Kumar Chawda, B. Anand, and V.Ramgopal Rao, "Effectiveness of Optimum Body Bias for Leakage Reduction in High K CMOS Circuits",Proceedings of the 35 th International Conference on Solid State Devices and Materials (SSDM 2004), Tokyo, Japan, September 15-17,2004

V.Ramgopal Rao, "Nanotechnology-A revolution in progress",
'Electrical & Electronics' magazine, June, 2004 (Invited)

D. R. Nair, S. Mahapatra, S. Shukuri and J. Bude, "Multi-Level
Programming of NOR Flash EEPROMs by CHISEL Mechanism", Proceedings,Int. Reliability Phys. Symp (IRPS), Phoenix, USA, p.635, 2004.

P. R. Nair, P. Bharath Kumar, R. Sharma, S. Kamohara and S.
Mahapatra, "A Comprehensive Trapped Charge Profiling Technique for SONOS Flash EEPROMs", accepted, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2004
 

S. Mahapatra, P. Bharath Kumar and M. A. Alam, "Investigation and Modeling of Interface and Bulk Trap Generation During Negative Bias Temperature Instability of p-MOSFETs", IEEE Trans. Electron Devices,v.51, p.1371, 2004.

D. R. Nair, S. Mahapatra and S. Shukuri, "Cycling endurance of NOR Flash EEPROM cells under CHISEL programming operation - Impact of technological parameters and scaling", accepted, to appear in IEEE Trans. Electron Devices, v.51, p.1672, 2004.
 

M. A. Alam and S. Mahapatra, "A Comprehensive Model of PMOS NBTI Degradation", accepted, to appear in Microelectronics Reliability,special issue on NBTI, 2004 (Invited paper)

S. Mahapatra, S. Shukuri and J. Bude, "Substrate bias effect on
cycling induced performance degradation of scaled flash EEPROMs",Proceedings, 16th IEEE VLSI Design Conference, New Delhi, India,p.223, 2003.

N. R. Mohapatra, S. Mahapatra, V. R. Rao, S. Shukuri and J. Bude,"Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs", Proceedings, Int. Reliability Phys. Symp (IRPS),Dallas, USA, p.518, 2003.
 

D. R. Nair, N. R. Mohapatra, S. Mahapatra, S. Shukuri and J. Bude,"The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMs", Proceedings, 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore,p.164, 2003.

N. R. Mohapatra, D. R. Nair, S. Mahapatra, V. R. Rao and S. Shukuri,"The Impact of Channel Engineering on the Performance Reliability and Scaling of CHISEL NOR Flash EEPROMs", Proceedings, 33rd European Solid State Device Research Conference (ESSDERC), Lisbon, Portugal,p.541, 2003.

D. R. Nair, N. R. Mohapatra, S. Mahapatra and S. Shukuri, "The Impact of Technology Parameters and Scaling on the Programming Performance and Drain Disturb in CHISEL Flash EEPROMs", Proceedings,International Conference on Solid State Devices and Materials (SSDM),Tokyo, Japan, p.644, 2003.

K. G. Anil, S. Mahapatra and I. Eisele, "A detailed experimental
investigation of impact ionization in n-channel metal-oxide-semiconductor field-effect-transistors at very low drain voltages", Solid State Electron, v.47, p.995, 2003.

S. Mahapatra, P. Bharath Kumar and M. A. Alam, "A new observation of enhanced bias temperature instability in thin gate oxide p-MOSFET",Tech. Digest, International Electron Devices Meeting (IEDM),Washington, DC, USA, p.337, 2003.

A.Dixit, and V. Ramgopal Rao, ~SA Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep sub-micrometer CMOS Regime~T, Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003, New Delhi, India

N.R Mohapatra, M.P.Desai, and V. Ramgopal Rao ~SDetailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics~T, Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003, New Delhi, India

D. Vinay Kumar, N. R.Mohapatra, V. Ramgopal Rao, and M. B. Patil,"Application of the look-up table approach to high-K dielectric MOS transistor circuits," Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003, New Delhi, India

Najeeb-ud-Din, V.Ramgopal Rao, and J.Vasi, ~SSmall Signal Characteristics of Thin Film Single Halo SOI MOSFETs for Mixed Mode Applications~T, Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003, New Delhi, India

 Nihar. R. Mohapatra, S. Mahapatra, V. Ramgopal Rao, S. Shukuri and J.Bude, ~SEffect of Programming Biases on the Reliability of CHE and CHISEL Flash EEPROMs~T, Proceedings of the International Reliability Physics Symposium (IRPS) 2003, March 30 - April 3, 2003, Dallas,Texas, USA

A. Prasad, V. Agarwal, R. O. Dusane, and V. Ramgopal Rao, ~SStudy of Plasma Immersion Ion Implantation Induced Damage on Ultra-thin Gate Dielectrics~T, Accepted, 203rd Meeting of The Electrochemical Society, Paris, France, April 27-May 2, 2003 (Symposium on "Thin Film Materials, Processes, and Reliability: Plasma\\Processing for the 100 nm Node and Copper Interconnects\\ with Low-k Inter Level Dielectric Films)

Nihar Mohapatra, Deleep Nair, Souvik Mahapatra, V. Ramgopal Rao,Shoji Shukuri, "The Impact of Channel Engineering on the Performance Reliability and Scaling of CHISEL NOR Flash EEPROMs", 33rd European Solid-State Device Research Conference (ESSDERC) 2003: 16 - 18 September 2003, pp. 541-544, Lisbon, Portugal

K.N.Manjularani, V.Ramgopal Rao, J.Vasi, "Relaibility of Ultrathin JVD Silicon Nitride MNSFETs under High Field Stressing"Proceedings of the 10 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 7-11 July 2003, Singapore

V.Ramgopal Rao, K.Narasimhulu,"Novel Device Architectures and Processes for the 65 nm CMOS Technology Node and Beyond", Indian National Academy of Engineering (INAE) Conference on Nanotechnology(ICON-2003), Dec. 22-23, 2003, Chandigarh, India (Invited)

Najeeb-ud-Din, V. Ramgopal Rao, and J. Vasi, "Thin Film Single Halo (SH) SOI nMOSFETs - Hot Carrier Reliability for Mixed Mode
Applications" IEEE TENCON 2003, Convergent Technologies for the
Asia-Pacific, OCTOBER 14-17, 2003,BANGALORE, INDIA

 K.N.Manjularani, V.Ramgopal Rao,J.Vasi, "Characterization of
High-Field Stress-Induced Border Traps in JVD Si3N4 Transistors by Drain urrent Transient and 1/f Methods" 34th IEEE Semiconductor Interface Specialists Conference (SISC), December 4-6, 2003,Washington, D.C., USA

N.R Mohapatra, S. Mahapatra and V. Ramgopal Rao, ~SBias and Time Dependene of Damage Generation in n-Channel MOS Transistors Operating Pulsed AC Stress Degradation in Thin Gate Oxide MOSFETs~T Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore

Neeraj .K. Jha, M. Shojaei, V.Ramgopal Rao, ~SPerformance and
Reliability of Single Pocket Deep Submicron MOSFETs for Analog
Applications~T, Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore

Neeraj K. Jha, V. Ramgopal Rao, and J.C.S.Woo, "Optimization of
Single Halo p-MOSFET Implant Parameters for Improved Analog
in the Substrate Enhanced Gate Current Regime~T Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore

Neeraj K. Jha, V. Ramgopal Rao, and J.C.S.Woo, "Optimization of
Single Halo p-MOSFET Implant Parameters for Improved Analog
Performance and Reliability", Proceedings of the 32 nd European
Solid-State Device Research Conference (ESSDERC), 24 - 26 September 2002, Florence, Italy

Parag C. Waghmare, Samadhan B. Patil, Alka A. Kumbhar, Laxmi Sahoo,V. Ramgopal Rao, and R.O. Dusane, ~SNitrogen dilution effects on structural and electrical properties of hot wire deposited a-SiN:H films for Deep Sub-micron CMOS Technologies~T, Proceedings of the International Conference on Cat-CVD (Hot-Wire CVD) Process, Denver, CO, USA, September 10-13, 2002

Samadhan B. Patil, Anand V. Vairagar, Alka A. Kumbhar, Laxmi K. Sahu,V. Ramgopal Rao, N. Venkatramani, R. O. Dusane and B. Schroeder,~SHighly Conducting P+- PolySi Deposited by HWCVD and its Applicability As Gate Material for CMOS Devices~T Proceedings of the International Conference on Cat-CVD (Hot-Wire CVD) Process, Denver,CO, USA, September 10-13, 2002

A.V. Vairagar, S.B. Patil, D.J. Pete, R.O. Dusane,, N. Venkatramani and V.Ramgopal Rao, "Suppression of Boron Penetration by Hot Wire CVD Polysilicon" Accepted, 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore

N.R Mohapatra, S. Mahapatra and V. Ramgopal Rao, "Bias and Time Dependene of Damage Generation in n-Channel MOS Transistors Operating in the Substrate Enhanced Gate Current Regime" Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore

Yatin M. Mutha, R. Lal and V.Ramgopal Rao, "Physical Mechanisms for Pulsed AC Stress Degradation in Thin Gate Oxide MOSFETs" Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore

Neeraj .K. Jha, M. Shojaei, V.Ramgopal Rao, "Performance and Reliability of Single Pocket Deep Submicron MOSFETs for Analog Applications", Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore

Nihar R. Mohapatra, Madhav P. Desai, Siva G. Narendra, V. Ramgopal Rao, "The Effect of High-K Gate Dielectrics on Deep Sub-micrometer CMOS Device and Circuit Performance" IEEE Transactions on Electron Devices, vol.49, (no.5), May 2002, p.826-831

Najeeb-ud-Din, Aatish Kumar, Mohan V.Dunga, V.Ramgopal Rao, J.Vasi, "Suppression of Parasitic BJT Action in Single Pocket Thin Film Deep Sub-micron SOI MOSFETs", Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

Nihar. R. Mohapatra, M. P. Desai, V. Ramgopal Rao, "Effect of Technology Scaling on MOS Transistors with High-K Gate Dielectrics", Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

Krishna K. Bhuwalka, Nihar. R. Mohapatra, Siva G.Narendra, V. Ramgopal Rao, "Effective dielectric thickness Scaling for High-K Gate Dielectric MOSFETs", Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

P.C.Waghmare, S.B.Patil, A.Kumbhar, R.O.Dusane, and V.Ramgopal Rao, "Improvement of Gate Dielectric Quality of MNS Capacitors by Hydrogen Etching for Ultra Thin Gate Dielectrics", Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi, "Degradation Study of Ultra-Thin JVD Silicon Nitride MNSFET", Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

Nihar. R. Mohapatra, Souvik Mahapatra and V. Ramgopal Rao, "Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors", Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

A.Dixit, R.O.Dusane, and V.Ramgopal Rao, "Electrically Induced Junction MOSFET for High Performance Sub 50 nm CMOS Technology", Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

Yatin Mutha, K.N.ManjulaRani, R.Lal and V.Ramgopal Rao, "Polarity Dependence of Degradation in Ultra Thin Oxide and JVD Nitride Gate Dielectrics", Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

D.G.Borse, Manjula Rani K.N., Neeraj K. Jha, A.N. Chandorkar, J.Vasi, V. Ramgopal Rao, B.Cheng, J.C.S. Woo, "Optimization and Realization of Sub 100nm Channel Length Single Halo p-MOSFETs" IEEE Transactions on Electron Devices, vol.49, (no.6), June 2002.

K. G. Anil, S. Mahapatra and I. Eisele, "Electron-electron interaction signature peak in the substrate current vs gate voltage characteristics of n-channel silicon MOSFETs", IEEE Trans. Electron Devices (submitted)

K. G. Anil, S. Mahapatra and I. Eisele, "A detailed experimental investigation of impact ionization in n-channel MOSFETs at very low drain voltages", Solid State Electron (submitted)

S. Mahapatra, S. Shukuri and J. Bude, "CHISEL flash EEPROM part-I: performance and scaling", IEEE Trans. Electron Devices (submitted)

S. Mahapatra, S. Shukuri and J. Bude, "CHISEL flash EEPROM part-II: reliability", IEEE Trans. Electron Devices (submitted)

S. Mahapatra and M. A. Alam, "Hole energy dependent anomalous, yet universal interface degradation in p-MOSFETs", IEEE Electron Devices Lett. (submitted)

P.C.Waghmare, S.B.Patil, A.Kumbhar, R.O.Dusane, and V.Ramgopal Rao, "Reliability Issues of Ultra Thin Silicon Nitride by Hot-Wire CVD for Deep Sub-Micron CMOS Technologies", Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India

Mayank Gupta, V.Vidya, V.Ramgopal Rao, Kun H. To, Jason C.S. Woo, "Optimization of Sub 100 nm Gamma-Gate Si-MOSFETs for RF Applications" Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India

Nihar. R. Mohapatra, Souvik Mahapatra and V. Ramgopal Rao, "A Comparative Study of Degradation for NMOSFET's in CHE and CHISEL Injection Regime", Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India

K.N. Manjularani, V.Ramgopal Rao, J.Vasi, "Border Trap Generation in JVD Nitride Capacitors Under High Field Stressing", 31 st IEEE Semiconductor Interface Specialists Conference, November 28 - December 1, 2001, Washington D.C, USA

P.Poornima, S.K.Tripathy, V.Ramgopal Rao, and D.K.Sharma, "Resolution Enhancement Techniques for Optical Lithography", Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India (Invited)

Najeeb-ud-Din, V.Ramgopal Rao, and J.Vasi, "Characterization and simulation of Lateral Asymmetric Channel Silicon-on-Insulator MOSFETs", Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India

K.N.ManjulaRani, V.Ramgopal Rao, and J.Vasi, "High Field Stressing Effects in JVD Nitride Capacitors", Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India

K. G. Anil, S. Mahapatra and I. Eisele, "Experimental verification of the nature of the high energy tail in the electron energy distribution in n-channel MOSFETs", IEEE Electron Devices Lett., v.22, p.478, Oct. 2001.

Najeebuddin, Aatish Kumar, Mohan V.Dunga, V.Ramgopal Rao, J.Vasi, "Characterization of Lateral Asymmetric Channel (LAC) Thin Film SOI MOSFETs", 6 th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Shanghai, China, 22-25 th October, 2001 (Invited)

Nihar. R. Mohapatra, M. P. Desai, Narendra Siva, V. Ramgopal Rao, "The Impact of High-K Gate Dielectrics on Sub 100nm CMOS Circuit Performance", Proceedings of the 31 st European Solid-State Device Research Conference (ESSDERC), 11 - 13 September 2001, Nuremberg, Germany, September, 2001.

Nihar Mohapatra, Souvik Mahapatra, V.Ramgopal Rao, ""Study of Degradation in Channel Initiated Secondary Electron Injection Regime", Proceedings of the 31 st European Solid-State Device Research Conference (ESSDERC), 11 - 13 September 2001, Nuremberg, Germany, September, 2001.

Parag C.W, Samadhan Patil, Alka Kumbhar, R.O.Dusane, V.Ramgopal Rao, "Ultra thin Silicon Nitride by Hot Wire CVD for Deep Sub-Micron CMOS Technologies", Proceedings of the Micro and Nanoengineering (MNE'01) Conference, September16-19, 2001,France

Mohan V. Dunga, Aatish Kumar, and V. Ramgopal Rao, "Analysis of Floating Body Effects in Thin Film SOI MOSFETs using the GIDL Current Technique", Proceedings of 8 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 9-13 July 2001, Singapore

Aatish Kumar, Rakesh Lal, and V. Ramgopal Rao, "A Simple and Direct Technique for Interface Characterization of SOI MOSFETs and its Application in Hot Carrier Degradation Studies in Sub 100 nm JVD MNSFETs", Microelectronic Engineering, Vol. 59, p. 429-433, 2001

K. G. Anil, I. Eisele and S. Mahapatra, "Observation of double peak in the substrate current versus gate voltage characteristics in n-channel MOSFETs", Appl. Phys. Lett., v.78, no.15, p.2238, April 2001.

S. Mahapatra, V. Ramgopal Rao, B. Cheng, M. Khare, C. D. Parikh, J. C. S. Woo and J. Vasi, "Performance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor Deposited Si3N4 MNSFETs", IEEE Transactions on Electron Devices, vol.48, (no.4), April 2001. p.679-84

S. Mahapatra, V.Ramgopal Rao, B.Cheng, J.Vasi and J.C.S.Woo "A Study of Hot-Carrier Induced Interface-Trap Profiles in Lateral Asymmetric Channel MOSFETs Using a Novel Charge Pumping Technique", Solid State Electronics, Vol. 45, p.1717-1723, 2001

Nihar.R.Mohapatra, A.Dutta, G.Sridhar, M.P.Desai and V.Ramgopal Rao "Sub 100 nm CMOS Circuit Performance with High-K Gate Dielectrics" Microelectronics Reliability, Vol. 41, p.1045-1048, 2001

Aatish Kumar, Souvik Mahapatra, Rakesh Lal, and V. Ramgopal Rao, "Multi-Frequency Transconductance Technique for Interface Characterization of Deep Sub-Micron SOI-MOSFETs", Microelectronics Reliability, Vol. 41, p. 1049-1051, 2001

Samadhan B.Patil, A.Kumbhar, P.Waghmare, V.Ramgopal Rao, and R.O.Dusane, "Low Temperatue Silicon Nitride deposited by Hot-Wire CVD for Deep Sub-micron CMOS Devices", Thin Solid Films, Vol. 395, p 270-274, 2001

Aatish Kumar, Rakesh Lal, and V. Ramgopal Rao, "A Simple and Direct Technique for Interface Characterization of SOI MOSFETs and its Application in Hot Carrier Degradation Studies in Sub 100 nm JVD MNSFETs", Microelectronic Engineering, Vol. 59, p. 429-433, 2001

Kottantharayil Anil, Souvik Mahapatra, V.Ramgopal Rao and I. Eisele, "Comparison of Sub-Bandgap Impact Ionization in Sub-100 nm Conventional and Lateral Asymmetrical Channel nMOSFETs", Japanese Journal of Applied Physics, Vol. 40 (2001) 2621-2626, Part 1, No. 4B, 30 April 2001

G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele "Performance Optimization of 60 nm Channel Length Vertical MOSFETs Using Channel Engineering", Proceedings of the 14th International Conference on VLSI Design, January 2001, Bangalore, INDIA

Nihar.R.Mohapatra, A.Dutta, M.P.Desai and V. Ramgopal Rao, "Effect of Fringing Capacitances in Sub 100 nm MOSFET's with High-K Gate Dielectrics" Proceedings of the 14th International Conference on VLSI Design, January 2001, Bangalore, INDIA

D.Vinay Kumar, Nihar R. Mahapatra, V. Ramgopal Rao, and Mahesh B. Patil, "Look-up Table Simulator for Circuit Simulation", To be published.

Anil K. G., S. Mahapatra and I. Eisele, "Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel

Parag C.W, Samadhan Patil, Alka Kumbhar, R.O.Dusane, V.Ramgopal Rao, "Ultra thin Silicon Nitride by Hot Wire CVD for Deep Sub-Micron CMOS Technologies", To appear in Microelectronics Reliability

N.Mahapatra, M.P.Desai, and V.Ramgopal Rao, "Device and Circuit Performance Issues with High-K Gate Dielectrics", Proceedings of the National seminar on VLSI: Systems, Design and Technology, IIT Bombay, Dec 2000

Nihar.R.Mohapatra, A.Dutta, G.Sridhar, M.P.Desai and V.Ramgopal Rao "Sub 100 nm CMOS Circuit Performance with High-K Gate Dielectrics" Proceedings of the 11th Workshop on Dielectrics in Microelectronics (WoDiM), November 13-15, 2000, Munich, Germany

Aatish Kumar, Souvik Mahapatra, Rakesh Lal, and V. Ramgopal Rao, "Multi-Frequency Transconductance Technique for Interface Characterization of Deep Sub-Micron SOI-MOSFETs", Proceedings of the 11th Workshop on Dielectrics in Microelectronics (WoDiM), November 2000, Munich, Germany

Samadhan B.Patil, A.Kumbhar, P.Waghmare, V.Ramgopal Rao, and R.O.Dusane, "Low Temperatue Silicon Nitride deposited by Cat CVD for Deep Sub-micron CMOS Devices", Proceedings of the International Conference on Cat-CVD (Hot-Wire CVD) Process, Kanazawa, Japan, November 2000

S.Mahapatra, V.Ramgopal Rao, J.Vasi, B.Cheng, and J.C.S. Woo, "Reliability Studies on Sub 100 nm SOI-MNSFETs", Proceedings of the International Integrated Reliability Workshop, October 23-26, 2000, California, USA.

K.G. Anil, S. Mahapatra, I. Eisele, V.Ramgopal Rao, and J. Vasi "Drain Bias Dependence of Gate Oxide Reliability in Conventional and Asymmetrical Channel MOSFETs in the Low Voltage Regime", Proceedings of the 30 th European Solid-State Device Research Conference (ESSDERC), Ireland, September, 2000

K.G. Anil, S. Mahapatra, V. Ramgopal Rao and I. Eisele, "Comparison of Sub-Bandgap Impact Ionization in Deep-Sub-Micron Conventional and Lateral Asymmetrical Channel nMOSFETs", Proceedings of the International Conference on Solid state Devices and Materials (SSDM) Sendai, Japan, August 28-31, 2000

V. Ramgopal Rao, S. Mahapatra, J.Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele, "Hot-Carrier Performance of 60 nm Channel Length Delta-Doped Vertical MOSFETs with High-pressure Grown Oxide as a Gate Dielectric", Proceedings of the 30th IEEE Semiconductor Interface Specialists Conference, San Diego, California, USA

V. Ramgopal Rao, Rahul Sachdev, and C. R. Viswanathan, "Oxide Thickness and Supply Voltage Scaling for Optimum Gate Delay in sub 100 nm CMOS Technologies" To be published

V. Vidya, V. Ramgopal Rao, and J. Vasi, Kun H. To and J.C.S. Woo, "Electrical Characterization of 60 nm Channel Length Gamma-gate n-MOSFETs", To be published

R.Wagh, M.Sudhakar, and V.Ramgopal Rao, "A Novel Charge Pumping Technique for Plasma Process Induced Interface Damage Profiling in Sub-Micron MOSFETs" To be published

S.Mahapatra, C.D.Parikh, V.Ramgopal Rao, C.R.Viswanathan, and J.Vasi, "A Comprehensive tudy of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique", IEEE Transactions on Electron Devices, vol. 47, p. 171-178, January, 2000

S.Mahapatra, C.D.Parikh, V.Ramgopal Rao, C.R.Viswanathan, and J.Vasi, "Device Scaling Effects on Hot-Carrier Induced Interface and Oxide Trap Distributions in MOSFETs", IEEE Transactions on Electron Devices, vol. 47, p. 789-796, April 2000

M. Hemkar, J.Vasi, V. Ramgopal Rao, B. Cheng, J.C.S. Woo, "Optimization and realization of sub 100 nm channel length lateral asymmetric channel p-MOSFETS" Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec. 1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.584-7.

Sharad Sharma, and V. Ramgopal Rao, "Performance Trade-offs by the Use of High-K Gate Dielectrics in Sub 100 nm CMOS Technologies", Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec. 1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.896-9

Sushant S. Suryagandh, and V. Ramgopal Rao, "Dynamic Threshold Voltage MOSFETs for Future Low Power Sub 1V CMOS Applications", Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec. 1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.655-8

Samadhan B. Patil , Sangeeta Vaidya, Alka Kumbhar, R. O. Dusane, A. N. Chandorkar and V. Ramgopal Rao, "Low Temperature Hot-Wire CVD Nitrides for Deep Sub-Micron CMOS Technologies" Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec.1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.879-82

S. Mahapatra, K. N. Manjularani, V. Ramgopal Rao, J. Vasi, " ULSI MOS Transistors with Jet Vapour Deposited (JVD) Silicon Nitride for the Gate Insulator", Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec. 1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.803-10

B.Cheng, V.Ramgopal Rao and J.C.S.Woo, "Exploration of Velocity Overshoot in a High-Performance Deep sub 100 nm SOI MOSFET with Asymmetric Channel Profile" IEEE Electron Device Letters, vol. 20, p. 538-540, October 1999

G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, C. D. Parikh and J. Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele " Performance Optimization of 60 nm Channel Length Vertical MOSFETs Using Channel Engineering" Submitted to 29 th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium 13 - 15 September 1999

S. Mahapatra, V. Ramgopal Rao, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo , "Hot-Carrier Induced Interface Degradation in Jet Vapor Deposited SiN MNSFETs as Studied by a Novel Charge Pumping Technique" p. 592-595, 29 th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium 13 - 15 September 1999

A. Inani, V. Ramgopal Rao, B. Cheng, P. Zeitzoff, and J. C. S. Woo, "Capacitance Degradation due to Fringing Fields in Deep Sub-Micron MOSFETs with High-K Gate Dielectrics" p.160-163, 29 th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium 13 - 15 September, 1999

B.Cheng, M.Cao, V.Ramgopal Rao, A.Inani, P.V.Voorde, W.Greene, Z.Yu, H.Stork, and J.C.S.Woo, "The impact of high-k gate dielectrics and metal gate electrode on sub 100 nm MOSFETs", IEEE Transactions on Electron Devices, vol. 46, p. 1537, 1999

A.Inani, V.Ramgopal Rao, B.Cheng, and J.C.S. Woo, "Gate Stack Architecture Analysis and Channel Engineering in Deep Sub-Micron MOSFETs", Japanese Journal of Applied Physics, Part 1, April 1999, vol.38, (no.4B): p. 2266-71

S.Mahapatra, C.D.Parikh, J.Vasi, V.Ramgopal Rao, and C.R.Viswanathan, "A Direct Charge Pumping Technique for Spatial Profiling of Hot-Carrier Induced Interface and Oxide Traps in MOSFETs", Solid State Electronics, p. 915, vol. 43, 1999

V. Ramgopal Rao, W.Hansch, S. Mahaptra, D.K. Sharma, J.Vasi, T.Grabolla, and I.Eisele, "Low Temperature-High Pressure Grown Thin Gate Dielectrics for MOS Applications" Microelectronic Engineering, vol. 48, p.223-226, 1999

S. Mahapatra, V. Ramgopal .Rao, C.D.Parikh, J.Vasi, B.Cheng, and J.C.S.Woo, "A Study of 100 nm Channel Length Asymmetric MOSFETs by Using Charge Pumping", Microelectronics Engineering, vol. 48, p. 193-196, 1999

S. Mahapatra, V. Ramgopal .Rao, C.D.Parikh, J.Vasi, B.Cheng, and J.C.S.Woo, "A Study of 100 nm Channel Length Asymmetric MOSFETs by Using Charge Pumping", Proceedings of the Insulating Films on Semiconductors (INFOS), June 1999, Kloster Banz, Germany

S.Mahapatra, V.Ramgopal Rao, K.N. Manjularani, C.D. Parikh, J. Vasi, B. Cheng, M. Khare, and J.C.S. Woo, "100 nm Channel Length MNSFETs using a Jet Vapor Deposited Ultra-thin Silicon Nitride Gate Dielectric", Technical Digest, 1999 Symposium on VLSI Technology, June 14-19, Kyoto, Japan

B.Cheng, A.Inani, V.Ramgopal Rao, and J.C.S.Woo, "Channel Engineering for High Speed Sub-1.0 V Power Supply Deep Sub-Micron CMOS" Technical Digest, 1999 Symposium on VLSI Technology, June 14-19, Kyoto, Japan

S. Mahapatra, V. Ramgopal Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S.Woo, "Hot-Carrier Induced interface Trap Distributions in Conventional and Asymmetric Channel MOSFETs as Determined by a novel Charge Pumping Technique" Presented at the 30 th Semiconductor Interface Specialists Conference (SISC), South Carolina, USA, December 1999

V. Ramgopal Rao, W.Hansch, S.Mahaptra, D.K.Sharma, J.Vasi, T.Grabolla, and I.Eisele, "Low Temperature-High Pressure Grown Thin Gate Dielectrics for MOS Applications", Proceedings of the Insulating Films on Semiconductors (INFOS), June 1999, Kloster Banz, Germany

V. Ramgopal Rao, G. Wijeratne, D. Chu, T. Brozek, and C.R. Viswanathan, "Plasma Process Induced Abnormal 1/f Noise Behavior in Deep Sub-Micron MOSFETs", 3 rd International Symposium on Plasma Process-Induced Damage (P2ID), Hawaii, USA, June, 1998

W.Hansch, A.Nakajima, K.Shibahara, V. Ramgopal Rao and I.Eisele, "Observation of Periodic Current Oscillations in Vertical sub-100nm MOS-PDBFETs with Wide Channels", 1998 IEEE Silicon Nanoelectronics workshop, (Satellite Workshop, VLSI T.echnology Symposium) Honolulu, Hawaii, USA, June, 1998

C.R. Viswanathan and V. Ramgopal Rao, "Application of charge pumping technique for sub-micron MOSFET characterization" Presented at the Electrical and Physical Characterization of Materials and Devices for Silicon Microelectronics. MIGAS, Autrans, France, 29 June -5 July 1998

A.Inani, B.Cheng, V. Ramgopal Rao, and J.C.S.Woo, "Gate Stack Architecture Analysis in sub 100 nm Channel Length MOSFETs" , 5 th National SRC Conference TECHCON, 1998, Las Vegas, USA

B.Cheng, V. Ramgopal Rao, B.Ikegami, and J.C.S.Woo, "Realization of sub 100 nm asymmetric Channel MOSFETs with Excellent Short-Channel Performance and Reliability" Technical Digest, 28 th European Solid-State Device Research Conference (ESSDERC), Bordeaux, France, 1998

R.Sachdev, G.Wijeratne, V. Ramgopal Rao, and C.R.Viswanathan, "A study of the effect of Plasma Damage on Sub-micron MOSFET's Flicker Noise Properties", Technical Digest, 28th European Solid-State Device Research Conference (ESSDERC), Bordeaux, France, 1998

A.Inani, V.Ramgopal Rao, B.Cheng, M.Cao, P.V.Voorde, W.Greene, and J.C.S. Woo, "Performance Considerations in Using High-k Dielectrics for Deep Sub-Micron MOSFETs", Proceedings of the Solid state Devices and Materials (SSDM) Research Conference, Hiroshima, Japan, 7-10 Sept., 1998

B. Cheng, V. Ramgopal Rao, and J. C. S. Woo, "Sub 0.18 um SOI MOSFETs Using Lateral Asymmetric Channel Profile and Ge Pre-amorphization Salicide Technology", Proceedings of the IEEE SOI Conference, October 5-8, Stuart, Florida, USA, 1998

W.Hansch, V.Ramgopal Rao, C.Fink, F.Kaesen, and I.Eisele, "Electric Field Tailoring in MBE Grown Vertical Sub-100 nm MOSFETs", Thin Solid Films, vol..321, p. 206-214, 1998

T.Brozek, V. Ramgopal Rao, A.Sridharan, J. Werking, D.Chan, and C.R.Viswanathan, "Charge Injection using Gate-Induced-Drain-Leakage Current for Characterization of Plasma Edge Damage in CMOS Devices" IEEE Transactions on Semiconductor Manufacturing, vol. 11 (2), May 1998

C.R. Viswanathan, and V. Ramgopal Rao "Application of charge pumping technique for sub-micron MOSFET characterization" Microelectronic Engineering, vol.40, (no.3-4):p. 131-46, Nov. 1998

A.Balandin, S.Cai, R.Li, K.L.Wang, V.Ramgopal Rao, and C.R.Viswanathan, "Flicker Noise in GaN/Al0.15Ga0.85N Doped Channel Heterostructure Field Effect Transistors", IEEE Electron Device Letters, p. 475, Vol. 19, 1998

The Microelectronics Group, "Radiation effects in silicon devices," Int. Conf. on Computers and Devices for Communication, Calcutta (1998).

S. Mahapatra, C. D. Parikh and J. Vasi, "A reliable approach to determine hot-carrier induced interface state distribution in nMOSFETs using charge pumping," Int. Conf. on Computers and Devices for Communication (CODEC), p. 373, Calcutta (1998).

C.R.Viswanathan and V. Ramgopal Rao, "Plasma Damage Studies Using SPIDER Structures", Microelectronic Innovation and Computer Research Opportunities (MICRO), University of California, 1998

W. Hansch, V.Ramgopal Rao, and I.Eisele, "The Planar-Doped-Barrier FET:MOSFET Overcomes Conventional Limitations", Technical Digest, p. 624, 27 th European Solid-State Device Research Conference (ESSDERC), Stuttgart, Germany, September, 1997

W. Hansch, F. Kaesen, V.Ramgopal Rao, and I. Eisele, "Electric field-tailoring in MBE-grown MOSFETs", Technical Digest, p. 117, 7th International Symposium on Silicon Molecular Beam Epitaxy, Banff, Canada, July 1997

V. Ramgopal Rao, W. Hansch, and I. Eisele, "Simulation, Fabrication and Characterization of High Performance Planar-Doped-Barrier Sub 100 nm Channel MOSFETs" Technical Digest, IEEE International Electron Devices Meeting (IEDM), p. 811, Washington DC, USA, December, 1997

Anand Sridharan, V.Ramgopal Rao, Tomasz Brozek, J. Werking, and C.R.Viswanathan, "Charge Injection using Gate-Induced-Drain-Leakage Current for Characterization of Plasma Edge Damage in CMOS Devices", Technical Digest, p. 560, 27 th European Solid-State Device Research Conference (ESSDERC), Stuttgart, Germany, September, 1997

C.R.Viswanathan, V.Ramgopal Rao and T.Brozek, "Localized Charge Injection-A Tool to Investigate Plasma Damage in CMOS Devices" (invited) Proceedings of the 9 th International Conference on Physics of Semiconductor Devices, December, 1997, New Delhi, India

V. Ramgopal Rao, W. Hansch, H. Baumgartner, I. Eisele, D. K. Sharma and J. Vasi "Charge Trapping Behavior in Deposited and Grown Oxides", Thin Solid Films, vol. 296, p. 37, 1997

V. Ramgopal Rao, I. Eisele, R. M. Patrikar, D. K. Sharma, J. Vasi, and T. Grabolla "High-Field Stressing of LPCVD Gate Oxides", IEEE Electron Device Letters, vol.18, p.84, 1997

P. V. S. Subrahmanyam, A. Prabhakar and J. Vasi, "High-field stressing effects on the split N2O grown thin gate dielectrics by rapid thermal processing," IEEE Trans. Electron Devices 44, 505 (1997).

A. Topkar, T. Mathew, R. Lal, J. Vasi and L. Nanver, "Radiation induced degradation of bipolar transistors," Proc. of the 9th International Workshop on the Physics of Semiconductor Devices, New Delhi (1997).

S. Mahapatra, C. D. Parikh and J. Vasi, "A new technique to profile hot-carrier induced interface state generation in nMOSFETs using charge pumping," Proc. of the 9th International Workshop on the Physics of Semiconductor Devices, p. 1030, New Delhi (1997).

V.Ramgopal Rao, W.Hansch, H.Baumgartner, I.Eisele, D.K.Sharma, J.Vasi, and T.Grabolla, "Charge Trapping Behavior in Deposited and Grown Thin MOS Gate Dielectrics", Proceedings of the European Materials Research Society (EMRS) Symposium, 1996 Spring Meeting, Strasbourg, France

V. Ramgopal Rao, F. Wittmann, H. Gossner, and I. Eisele, " Hysteresis Behaviour in 85 nm Channel Length Vertical MOSFETs Grown by MBE", IEEE Trans. on Electron Devices, vol. 43(6), p. 973, 1996

V. Ramgopal Rao, D. K. Sharma, and J. Vasi, "Neutral Electron Trap Generation under Irradiation in Reoxidised Nitrided oxide Gate Dielectrics", IEEE Trans. on Electron Devices, vol. 43, p. 1467, 1996

V. Ramgopal Rao, I. Eisele, and T. Grabolla, "Alternative Gate Insulators for Future Deep Submicron Channel Length MOSFETs", Proc. of VIII International Conference on Physics of Semiconductor Devices, December, 1995, New Delhi, India

N. Arthi, C.Kaivalya, and V.Ramgopal Rao, "Computers in Medicine" CSI Communications, vol. 17, p.5, 1993 R. M. Patrikar, R. Lal and J. Vasi, "Interface-state generation due to high-field stressing in MOS oxides," Solid State Electronics. 38, 477 (1995).

S. S. Moharir, J. Vasi and A.N. Chandorkar, "Data and Modelling of HCl Oxidation of Silicon," Journal of the Institution of Engineering (India) 76, 2 (1995).

A.Mallik, A.N.Chandorkar and J. Vasi, "Capture cross-section of hole traps in reoxidized nitrided oxide measured by irradiation," Solid-State Electronics 38, 1851 (1995).

A. Mallik, V. Ramgopal Rao, A.N. Chandorkar, and J. Vasi, "Trap generation upon irradiation in reoxidised nitrided oxide gate dielectrics", Proc. of VII International conference on Physics of Semiconductor Devices, December, 1993 New Delhi, India

Mallik, A.N. Chandorkar and J. Vasi, "Electron trapping during irradiation in RNO," 30th IEEE Nuclear and Space Radiation Effects Conference, Snowbird, USA (1993).

R. M. Patrikar, R. Lal and J. Vasi, "Power Law Model for Positive Charge Buildup in Silicon Dioxide due to High Field Stressing," Solid State Electronics, 36, 723 (1993).

R. M. Patrikar, R. Lal and J. Vasi, "Degradation of Oxides in MOS Capacitors Under High Field Stress," J. Appl. Phys. 74, 4598 (1993).

R. M. Patrikar, R. Lal and J. Vasi, "Net Positive Charge Buildup in Various MOS Insulators Due to High-Field Stressing" IEEE Electron Device Lett. 14, 530 (1993).

R. M. Patrikar, R. Lal, J. Vasi, "High Field Stressing characteristics for the case of silicon in Inversion," J.Appl.Phys., 73, 3857 (1993).

A. Mallik, J. Vasi and A. N. Chandorkar, "A Study of Radiation Effects on Reoxidized Nitrided Oxide MOSFETs, Including Effects on Mobility," Solid-State Electron. 36, 1359 (1993).

A. Mallik, J. Vasi and A. N. Chandorkar, "Electron Trapping During Irradiation in Reoxidized Nitided Oxide," IEEE Trans. Nucl. Sci. NS-40, 1380 (1993).

A.Mallik, J.Vasi and A.N.Chandorkar, "The nature of the hole traps in reoxidized nitrided oxide gate dielectrics," J.Appl.Phys. 74, 2665 (1993).

M.H.M. Reddy and D.K. Sharma, "Optimization of growth conditions of dry thermal oxides for radiation hard applications," Proc. of the Seventh International Workshop on the Physics of Semiconductor Devices, New Delhi, India, NewDelhi(1993).

S. S. Moharir and R. Lal, "Radiation performance of reoxidized nitrided pyrogenic oxide as a field dielectric," Proc. of the Seventh International Workshop on the Physics of Semiconductor Devices, New Delhi, India, New Delhi (1993).

A.Mallik, J. Vasi and A.N. Chandorkar, "Hole traps in RNO gate dielectrics," Proc. of the Seventh International Workshop on the Physics of Semiconductor Devices, New Delhi (1993).