EE-739: Processor Design
Semester: Jan - Apr 2013
Instructor: Virendra
Singh
Class Timings (Tentative): SLOT1 [8:35
am - 9:30 am (Monday), 9:30 am - 10:30 am (Tuesday), 10:30 am - 11:30 am
(Thursday) ]
Office Hours: To be decided
Moodle
(Course material access)
Syllabus:
CISC Processor Design: Defining microprocessor,
hardware flowchart, implementing from flowchart, exception, control store,
microcode design.
RISC Processor Design: Building datapath and controller, single cycle implementation, multi
cycle implementation, pipelined implementation, exception and hazards handling.
(Example: DLX Processor)
Superscalar Processors Design: Superscalar
organization, superscalar pipeline overview, VLSI implementation of dynamic
pipelines, register renaming, reservation station, re-ordering buffers, branch
predictor, and dynamic instruction scheduler etc.;
simultaneous multi-threading (SMT) design. (Example: Open SPARC T1)
Memory System Design. Application specific
instruction set processor (ASIP) design. Dynamic
reconfigurable processors (DRP).
Impact of physical
technology, trends in power consumption, low power techniques, low voltage
techniques, clock distribution. Verification and test challenges.
References:
Prerequisite: Knowledge of
Digital System Design
Evaluation: Mid term (15%), Final Exam (30%), Course
Projects (20%), Assignments (15%), and Continuous Assessment (20%)
Exam Schedule:
Test1:
Test2:
Test3:
Test4:
Mid Term Exam:
Final Exam:
Assignment 1:
Assignment 2:
Assignment 3:
Assignment 4:
Class Schedule: (For
course material access)
Jan 7 |
Course Introduction |
Introduction to computer systems
design and processor architecture/micro-architecture |
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