Virendra Singh, Ph.D(NAIST,
Japan)
Associate Professor
Department of Electrical Engineering
Indian Institute of Technology Bombay
Powai,
Mumbai 400076 India
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E-mail : |
viren@ee.iitb.ac.in,
virendra@computer.org singhv@iitb.ac.in |
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Tel : |
+91-22-2576-9432
(O) +91-887918-2501
(M) |
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Fax : |
+91-22-2572-3707 |
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Office : |
122
D, EE Building |
New:
Requirement:
Post Doctoral Fellows/ Research Associates
Funding: DST-JST funding,
DST-RFBR
Papers: VTS 2012
paper, ISCAS 2012 paper, IOLTS 2012 paper, VDAT 2012 papers
Conferences: RASDAT`12 IWPVTD`12
Courses: Advanced Computing for
Electrical Engineers, Processor Design, and Advanced Topics in Computer
Architecture
Publications Teaching Funding Professional
Activities Students
Visitors RASDAT IWPVTD WHF
Research
Lab.: Computer Architecture and
Dependable Systems Lab.
Research Interest:
- Computer Architecture
- Processor architecture &
micro-architecture
- Reconfigurable computing
- VLSI Testing
- Fault-tolerant computing
- Robust design and architectures
- Self-healing system design
- SoC/NoC design and test
- Post Silicon Debug
- High level synthesis
- Formal verification
- Trusted computing
- FPGA based acceleration
- Trusted hardware design
Education:
- Ph.D (Computer Science) -
(2002-2005)
Nara Institute of Science and Technology
(NAIST)
Kansai
Science City, Nara, Japan
Advisor: Prof. Hideo Fujiwara
Co-Advisors: Prof. Kewal K.
Saluja (Univ. of Wisconsin-Madison, USA)
and Prof.
Michiko Inoue (NAIST)
Thesis: Instruction-Based
Self-Testing of Performance Oriented Faults in Modern Processors
- M.E (Electronics &
Communication) - (1994-1996)
Malaviya National Institute of Technology
(MNIT)
Jaipur
(Rajasthan) India
Advisor: Prof. MS Gaur
- B.E (Hons) in Electronics &
Communication - (1990-1994)
Malaviya National Institute of Technology
(MNIT)
Jaipur
(Rajasthan)
Professional Experience:
- Faculty member, Indian Institute of Technology Bombay
(Since Dec 2011)
- Faculty member, SERC, Indian Institute of
Science (IISc), Bangalore (May 2007 - Dec 2011)
- Scientist, Central Electronics Engg. Research
Institute (CEERI), Pilani (Mar 1997 - May 2007)
- Faculty member, Banasthali
University (Jun 1996 - Mar 1997)
Publications: List of my
publications
Recent
Publications:
In 2012
- Mohammed
Shayan, Virendra Singh, Adit Singh, and Masahiro Fujita, `SEU tolerant
robust memory cell design`, 18th IEEE International On-Line
Testing Symposium (IOLTS)
2012`, Sitges, Spain, June 2012
- Jaynarayan Tudu,
Deepak Malani, and Virendra Singh, `ILP based approach for input vector
controlled toggle maximization in combinational circuits`, 16th
International Symposium on VLSI Design and Test (VDAT) 2012, Kolkata, India, July 2012
- Mohammad
Shayan, Virendra Singh, Adit Singh, and Masahiro Fujita, `SEU tolerant
robust latch design`, 16th International Symposium on VLSI
Design and Test (VDAT) 2012,
Kolkata, India, July 2012
- Suraj Sindia,
Vishwani D. Agrawal, and Virendra Singh, `Impact of process variation on
computers used for image processing`, IEEE International Symposium on
Circuits and Systems (ISCAS)
2012, Seoul, Korea, May 2012
- Prasanth V., Rubin Parekhji, and Virendra Singh, `Derating based
hardware optimizations in soft error tolerant designs`, 30th
IEEE VLSI Test Symposium (VTS)
2012, Hawai, USA, April 2012.
- Vijay Sheshadri, Prasanth V., Rubin Parekhji, Vishwani D. Agrawal, and
Virendra Singh, `Evaluating impact of soft errors in embedded system`,
IEEE International Workshop on Reliability Aware System Design and Test
(RASDAT) 2012, Hyderabad, India, Jan 2012.
- Satdev
Ahlawat, Virendra Singh, Shashidhar Bapat, and Karthik Madhugiri, `Low
power scan flip-flop design to eliminate output gating overhead for
critical paths`, IEEE International
Workshop on Reliability Aware System Design and Test (RASDAT) 2012,
Hyderabad, India, Jan 2012.
- Mohammed Shayan, Virendra Singh, Adit Singh, and Masahiro Fujita, `A
highly robust and cost effective SEU tolerant memory cell`, IEEE
International Workshop on Reliability Aware System Design and Test
(RASDAT) 2012, Hyderabad, India, Jan 2012.
Selected
Publications (Before 2012):
- Pramod
Subramanyan, Virendra Singh, Kewal Saluja, and Erik Larsson, `Adaptive
execution assistance for multiplexed fault-tolerant chip multiprocessors`,
29th IEEE International Conference on Computer Design (ICCD) 2011, Amherst, MA, USA,
October 2011
- Mohammed Abdul
Razzaq, Virendra Singh, and Adit Singh, `SSTKR: Secure and testable scan
design through test key randomization`, 20th IEEE Asian Test
Symposium (ATS) 2011, New
Delhi, India, Nov. 2011
- Suraj Sindia,
Vishwani Agrawal, and Virendra Singh, `Test and diagnosis of analog
circuits using moment generating functions`, 20th IEEE Asian
Test Symposium (ATS) 2011, New
Delhi, India, Nov. 2011
- Manas Puthal,
Virendra Singh, MS Gaur and Vijay Laxmi, `C-Routing: An adaptive
hierarchical NoC routing methodology`, 19th IFIP/IEEE
International Conference on Very Large Scale Integration (VLSI-SoC) 2011, Hongkong, China,
October 2011
- Pawan Kumar
and Virendra Singh, Efficient regular expression pattern matching using
cascaded automata architecture for network intrusion detection system`, 9th
IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, September 2011.
- V. Prasanth,
Virendra Singh, and Rubin Parekhji, `Reduced overhead soft error
mitigation methodology using error control coding technique`, 17th
IEEE International On-Line Test Symposium (IOLTS) 2011, Athens, Greece, July 2011.
- Suraj Sindia,
Vishwani Agrawal, and Virendra Singh, `Nonlinear analog circuit test and
diagnosis under process variation using V-transform coefficients`, 29th
IEEE VLSI Test Symposium (VTS),
2011, California, USA, May 2011
- Naveen
Choudhary, M.S. Gaur, Vijay Laxmi, and Virendra Singh, `Traffic aware
topology generation methodology for application specific NoC`, IEEE
International Symposium on Electronic Design, Test and Application (DELTA) 2011, Queens Town, New
Zealand, Jan 2011
- [Book Chapter] Dimitar Nikolov,
Mikael Vayrynen, Urban Ingelson, Virendra Singh, and Erik Larsson,
`Optimizing Fault Tolerance for Multi-Processor System-on-Chip`, Design and Test Technology for
Dependable Systems-on-Chip, Editors: Raimund Ubar, Jaan Raik, Heinrich
Theodor Vierhaus, 2010, Hardcover, ISBN:978-1-6096-0212-3.
- Pramod
Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `Energy
efficient fault tolerance in chip multiprocessors using critical value
forwarding`, 40th IEEE International Conference on Dependable
Systems and Networks (DSN),
Chicago, IL, USA, June 2010.
- Jaynarayan
Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `Scan cell
reordering to minimize peak power during test cycle: A graph theoretic
approach`, 15th IEEE European Test Symposium (ETS) 2010, Prague, Czech Rep., May
2010.
- Pramod
Subramanyam, Virendra Singh, Kewal Saluja, and Erik Larsson, `A low cost
redundant execution architectures for Chip multiprocessors`, Design
Automation and Test in Europe (DATE)
2010, Dresden, Germany, March 2010.
- Dimitar
Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Estimating
error probability and its application for optimizing roll-back recovery
with checkpointing`, IEEE Symposium on Electronic Design, Test &
Applications (DELTA) 2010, Ho
Chi Minh , Vietnam, Jan 2010
- Suraj Sindia,
Virendra Singh, and Vishwani Agrawal, `Multi-tone Testing of Linear and
Nonlinear Analog Circuits using Polynomial Coefficients`, IEEE Asian Test
Symposium (ATS) 2009, Taichung,
Taiwan, Nov 2009.
- Deepak K.G., Robinson
Reyna, Virendra Singh, and Adit Singh, `Leveraging Partial Enhanced Scan
for Improved Observabilty in Delay Fault Testing`, IEEE Asian Test
Symposium (ATS) 2009, Taichung,
Taiwan, Nov 2009.
- Jaynarayan
Tudu, Erik Larsson, Virendra Singh, and Vishwani D. Agrawal, `On Minimization of Peak Power during
SoC Test`, IEEE European Test Symposium (ETS) 2009, Seville, Spain, May 2009.
- Reshma Jumani,
Niraj Jain, Virendra Singh, and Kewal K. Saluja, `DX-Compactor: Distributed X-Compaction for SoC Test`, ACM Annual
Great Lake Symposium on VLSI (GLSVLSI)
2009, Boston, USA, May 2009.
- Mikael
Vayrynen, Virendra Singh, and Erik Larsson, `Fault-Tolerant Average Execution Time Optimization for General
Purpose Multi-Processor System-on-Chips`, Intl. Conference on Design
Automation and Test in Europe (DATE)
2009, Nice, France, Apr 2009.
- Virendra
Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara,
`Instruction-Based Self-Testing of Delay Faults in Pipelined Processors`, IEEE
Trans. on VLSI Systems, Vol. 14, No. 11, Nov. 2006, pp. 1203-1215.
- Virendra
Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Program-Based
Testing of Superscalar Microprocessor`, Proceedings of the IEEE 14th
North Atlantic Test Workshop, May 2005, pp. 79-86, Berlington, VT,
USA, May 2005.
- Virendra
Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Delay Fault
Testing of Processor Cores in Functional Mode`, IEICE Trans. on
Information & Systems, Vol. E-88D, No. 3, March 2005, pp. 610-618.
Funding:
- Institutional Grant for
Younger Researchers by Swedish Foundation of International Cooperation
in Research and Higher Education, with Prof. Erik Larsson, Linkoping
University, Sweden - (2008 to 2011)
Project: Design of Self-healing System Chips
Funding: INR 72 Lakhs
- UK India
Education and Research Initiative (UKIERI)
grant, with Prof. MS Gaur, MNIT, Jaipur and Prof. Mark Zwolinski,
Southampton University, UK - (2009 to 2011)
Project:
Multi-Processor Electronic Design Automation
Funding:
INR 22 Lakhs
- LSI Technology Research Grant
(2009 to 2013)
Project: Techniques
to Speedup Loading of Scan Pattern
Funding: INR 40 Lakhs (INR 10 Lakhs
per year)
·
Research
grant under strategic Japanese-Indian
cooperative program (DST-JST) with Prof. Masahiro Fujita,
Tokyo University, Tokyo, Japan (2010 - 2013)
Project: Computer
aided design of hardware accelerated Tsunami prediction system
Funding: INR 1.6 Crores
- Indo Russian
(DST-RFBR) joint research grant with Prof. Anzhela Matrosova, Tomsk State
University (2011 - 2013)
Project:
Synthesis of high quality testable circuits and diagnosis of performance
oriented faults
Funding:
INR 20 Lakhs
- Indo Russian
(DST-RFBR)) joint research grant with Lyudmila Babenko, Taganrog Institute
of Rechnology, and Prof. M.S. Gaur, MNIT, Jaipur (2011 - 2013)
Project:
Development of techniques for metamorphic malware detection and analysis
Teaching:
Current
Semester (July-Nov 2012)
- EE-453/EE-717:
Advanced Computing for Electrical Engineers
- EE-XXX
: Processor Design
- CS-XXX
: Advanced Topics in Computer Architecture
Recent Past
(at IIT-B)
Recent Past
(at IISc)
- E0-285: Computer
Aided Design of VLSI Systems (Aug -
Dec 2008, Aug -
Dec 2009, Aug-Dec
2010, Aug-Dec
2011)
- E0-286: Testing and
Verification of SoC Design (Jan - Apr 2008, Jan -
Apr 2009, Jan -
Apr 2010, Jan -
Apr 2011)
- SE-286: Data Structures and
Programming (Aug - Dec 2007, Aug - Dec 2008, Aug -
Dec 2009, Aug-Dec
2010, Aug-Dec
2011)
- MEL-G626: VLSI Testing and Testability
(at BITS, Pilani, Aug-Dec
2006)
(VLSI
Testing and Formal Verification)
Other Activities/ Courses:
- IEP on Digital
System Synthesis at IIT Kanpur
(Dec 10-21, 2007)
- Co-coordinator, IEP on VLSI Testing & Verification at
IISc. (Mar 10-19, 2008)
Professional Activities
Convener,
Computer Design and Test Lab., SERC, IISc (2007-2011)
Member, Departmental
Curriculum Committee (DCC), SERC, IISc (2007-2011)
Steering
Committee member
- IEEE Intl. Workshop on
Reliability Aware System Design and Test (RASDAT)
- IEEE Asian Test Symposium (ATS)
- IEEE Workshop on RTL and High
Level Testing (WRTLT)
General
Co-Chair - RASDAT
(2010, 2011, 2012)
Program
Co-Chair - WRTLT 2011
Finance
Chair - ATS 2011
Program
Co-Chair - DRV 2011
General
Co-Chair - IWPVTD 2011,
IWPVTD 2012
Technical
Program Committee Member
- IEEE International Conference
on Computer Design (ICCD) - 2011, 2012 (Processor architecture track)
- IEEE Asia Pacific Design Automation
Conference (ASPDAC) - 2011
- IEEE International Symposium on
VLSI (ISVLSI) - 2011
(Chennai)
- IEEE/IFIP International
Symposium on Very Large Scale Integration (VLSI-SoC) - 2011 (Hong Kong)
- Design Automation and Test in
Europe (DATE) - 2009 (Nice), 2010 (Dresden)
- Intl. Conference on VLSI Design
- 2010 (Student
track chair), 2011 (Test Track Chair), 2012 (TV track chair)
- VLSI
Design and Test Symposium (VDAT) - 2009
(Bangalore), 2010 (Chandigarh)
- IEEE Workshop on RTL and High
Level Testing (WRTLT) - 2009 (Hong Kong),
2010 (Shanghai)
- Intl. Conference on Risk and
Security of Internet and Systems (CRiSIS) - 2009 (Toulouse)
- Intl. Conf. on Advanced
Computing and Communication (ADCOM) - 2009
(track chair)
- Intl. Workshop on Network on
Chip Architectures (NoCArc) - 2009 (New York)
- Intl. Conf. on Emerging Trends
in Engineering and Technology (ICETET) - 2009
- IEEE Workshop on Design Reliability
and Variability (DRV) - 2009 (Austin, USA)
- IEEE North Atlantic Test
Workshop (NATW) - 2010 (New York)
Current Students (at IISc):
- Jaynarayan
Tudu (with Prof.
Matthew Jacob)
- Pawan Kumar
(with Prof. N.
Balakrishnan)
- V.
Prasanth (with Dr. Rubin Parekhji, TI)
- Arjun
Chiluka
- S.
Sreekar
- Md.
Shayan
- Vichatra
Pandit
- Roopa
Ram Choudhary