EE-739: Processor Design
Semester: Jan - Apr 2015
Instructor: Virendra
Singh
Class Timings: Slot 4 [11:30 am (Mon),
8:30 am (Tue), and 9:30 am (Thu)]
Office Hours:
Moodle,
Video
(Previous year`s course material access)
Syllabus:
CISC Processor Design: Defining microprocessor,
hardware flowchart, implementing from flowchart, exception, control store,
microcode design.
RISC Processor Design: Building datapath and controller, single cycle implementation, multi
cycle implementation, pipelined implementation, exception and hazards handling.
(Example: DLX Processor)
Superscalar Processors Design: Superscalar
organization, superscalar pipeline overview, VLSI implementation of dynamic
pipelines, register renaming, reservation station, re-ordering buffers, branch
predictor, and dynamic instruction scheduler etc.;
simultaneous multi-threading (SMT) design. (Example: Open SPARC T1)
Memory System Design. Application specific
instruction set processor (ASIP) design. Dynamic
reconfigurable processors (DRP).
Impact of physical
technology, trends in power consumption, low power techniques, low voltage
techniques, clock distribution. Verification and test challenges.
References:
Prerequisite: Knowledge of
Digital System Design
Resources: Moodle, Video
Lectures
Important Note: It
is MANDATORY to watch video
lectures before coming to every class. You are expected to ACTIVELY
participate in the class discussion.
Evaluation: Mid term (10%), Final Exam (20%), Course
Projects (15%), Assignments (25%), and Continuous Assessment (25%),
Presentation/Viva (5%)
Project1: Design of 2-wide fetch superscalar version
of ARMv7 ISA equivalent processor and demonstration on FPGA.