Research Interests
High Performance Computer Architecture
Energy Efficient Micro-architectures
Efficient Memory Subsytem Design
Multi-kernel GPGPU Architecture Design
Efficient Cache Hierarchy Design for High Throughput Systems
Publications
Varun Venkitaraman, Ashok Sathyan, Shrihari P. Deshmukh and Virendra Singh, "Novel Efficient Synonym Handling Mechanism for Virtual-real Cache Hierarchy",Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023.
Shubham Singhania, Neelam Sharma, Varun Venkitaraman, and Chandan Kumar Jha, "CAR: Community Aware Graph Reordering for Efficient Cache Utilization in Graph Analytics",VLSI Design and Test (VDAT) 2022, Communications in Computer and Information Science, vol 1687. Springer, Cham.
Neelam Sharma, Varun Venkitaraman, Newton, Vikash Kumar, Shubham Singhania and Chandan Kumar Jha, "Data-Aware Cache Management for Graph Analytics",Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2022.
Arindam Sarkar, Newton Singh, Varun Venkitaraman and Virendra Singh, "DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches" in IEEE Computer Architecture Letters, vol. 20, no. 1, pp. 62-4, 1 Jan.-June 2021.
Varun Venkitaraman, Ashok Sathyan and Virendra Singh, "CBIT - A Synonym Handler for Low-latency and Energy-efficient Cache Hierarchy", in 2019 IEEE 37th International Conference on Computer Design (ICCD). (Poster)
Educational Background
Teaching Assitantships
EE-739: Processor Design
CS-683: Advanced Computer Architecture
EE-748: Advanced Topics in Computer Architecture
EE-309: Microprocessors
EE-224: Digital Systems
CS-226: Digital Logic Design
CS-254: Digital Logic Design Lab
EE-709: Testing and Verification of VLSI Circuits
EE-677: Foundations of VLSI CAD
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