Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: virenVirendra Singh, Ph.D(NAIST, Japan)


Associate Professor


Department of Electrical Engineering

Indian Institute of Technology Bombay

Powai, Mumbai 400076 India


E-mail :,

Tel :

+91-22-2576-9432 (O)

+91-22-2576-8432 (R)

Fax :


Office :

122 D, EE Building


My Calendar




Publications . Teaching . Funding . Professional Activities . Students . Visitors . RASDAT . IWPVTD . WHF




Research Lab.: Computer Architecture and Dependable Systems Lab. (CADSL)



Coordinator: Indo-Japanese Joint Laboratory for Intelligent Dependable Cyber Physical Systems (IDCPS)


Associated Lab: Gigabit Networking Lab. (GNL), CSE



Requirements: PDFs, Ph.D Aspirants, Project Assistants, VHDL Coder




Funding: DST-JST funding, DRDO funding


Papers: DATE`18 paper, ISCAS`18 papers, GLSVLSI`18 paper


Conferences: VDAT`18, ITC-India`18, RASDAT`19, VLSID`19, ICISS-18


Courses: [Current Semester- Autumn 2018]: EE-748: Advanced Topics in Computer Architecture, CS-683: Advanced Computer Architecture, EE-309: Microprocessors


[Last Semester- Spring 2018]: CS-654: Current Topics in VLSI & System Design, EE-739: Processor Design (Basic & Advanced), EE-709 : Testing and Verification of VLSI Circuits


Serving as Program chair of 22nd Symposium on VLSI Design and Test (VDAT 2018), Program chair of 31st VLSI Design Conference (VLSID-18) & Program chair of 17th Embedded Systems Conference (ES-18), Program chair of 13th International Conference on Information Systems Security (ICISS-2017), Program Co-chair of SIN 2017


Debates at CS-654: End to VN Architecture, Is Microarchitecture dead ?


A note for students



Research Interest:






Nara Institute of Science and Technology (NAIST)

Kansai Science City, Nara, Japan

Advisor: Prof. Hideo Fujiwara

Co-Advisors: Prof. Kewal K. Saluja (Univ. of Wisconsin-Madison, USA)

and Prof. Michiko Inoue (NAIST)

Thesis: Instruction-Based Self-Testing of Performance Oriented Faults in Modern Processors

Malaviya National Institute of Technology (MNIT)

Jaipur (Rajasthan) India

Advisor: Prof. MS Gaur

Thesis: Simulation of ATM Networks with Heavy Tail Traffic Distribution

Malaviya National Institute of Technology (MNIT)

Jaipur (Rajasthan)



Professional Experience:




Publications: List of my publications


Recent Publications:


Selected papers in 2018



Selected Publications (Before 2018):


















Project: Architecting Intelligent Dependable Cyber Physical System Targeting IoTs and Mobile Big Data Analysis

PI: Virendra Singh, IITB and Prof. Masahiro Fujita, The University of Tokyo

Funding: INR 12.5 Crores (IITB: INR 5.1 Crores, and TU: Yen 14.8 Crores)


            Indo Russian (DST-RMES) Joint Project (2017 to 2020)

Project: Technologies and Toolset for Reliable Control of Production Areas of Internet of Things

PI: Prof. RK Shyamasundar, Co-PI: Virendra Singh, IITB, and Prof. Vsevolod Kotlyarov, SPBSTU, Russia

Funding: INR 60 Lakhs (IITB)


Agency: DRDO, Funding: INR 11.4 Crores

PI: Prof. Ashwin Gumaste, Co-PI: Virendra Singh


Agency: MCIT, Govt. of India, Funding: INR 7.2 Crores

PI: Prof. Shalabh Gupta, Co-PI: Virendra Singh


Agency: MCIT, Govt. of India

PI: Prof. R.K. Shyamasundar, Investigator: Virendra Singh


Project: Reflection Aware ICC Analysis Framework for Android Apps

PI: Prof. M.S. Gaur, Co-PI: Virendra Singh


Project: Design of Self-healing System Chips

Funding: INR 72 Lakhs


Project: Multi-Processor Electronic Design Automation

Funding: INR 22 Lakhs


Project: Techniques to Speedup Loading of Scan Pattern

Funding: INR 40 Lakhs (INR 10 Lakhs per year)


            Research grant under strategic Japanese-Indian cooperative program (DST-JST) with Prof. Masahiro Fujita, Tokyo University, Tokyo, Japan (2010 - 2013)

Project: Computer aided design of hardware accelerated Tsunami prediction system

Funding: INR 1.6 Crores

Project: Synthesis of high quality testable circuits and diagnosis of performance oriented faults

Funding: INR 20 Lakhs


Project: Development of techniques for metamorphic malware detection and analysis




Last Semester (Jan-Apr 2018)



Current Semester (July-Nov 2017)



Recent Past (at IIT-B)





Past (at IISc)






(VLSI Testing and Formal Verification)



Other Activities/ Courses:




Professional Activities


Convener, Computer Architecture & Dependable Systems Lab., IITB (2011 - till date)

Convener, Computer Design and Test Lab., SERC, IISc (2007-2011)

Member, Departmental Curriculum Committee (DCC), SERC, IISc (2007-2011)


Steering Committee member


General Co-Chair - RASDAT (2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018)

Vice General Chair: VLSI Design Conference 2014, Embedded Systems Conference 2014

Program Co-Chair: VLSI Design Conference 2014, Embedded Systems Conference 2014

Program Co-Chair - WRTLT 2011, VDAT 2013, VDAT 2016, VDAT 2017

Finance Chair - ATS 2011

Program Co-Chair - DRV 2011

General Co-Chair - IWPVTD 2011, IWPVTD 2012

General Co-Chair – ATS 2015


Technical Program Committee Member



Current Students (at IITB)


Deepak Malani (Ph.D)

Jaidev Shenoy (Ph.D)

Ankush Srivastava (Ph.D)

Suryakant Toraskar (Ph.D)

Toral Shah (Ph.D)

Shoba Gopalkrishnan (Ph.D)

Rohini Gulve (Ph.D)

Nihar Hage (Ph.D)

Rajkumar Chaudhary (Ph.D)

Satyadev Ahlawat (Ph.D)

Newton (Ph.D)

Vineesh V.S (Ph.D)

Nirmal Boran (Ph.D)

Binod Kumar (Ph.D)

Rahul Kumar (Ph.D)

Antara Ganguly (Ph.D)


Current Students (at IISc):



Full list of current and former students