Department of Electrical Engineering
IIT Bombay

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V. Ramgopal Rao

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RESEARCH INTERESTS

  • Nanoelectronics
  • Technology Aware Design Challenges with Emerging Technologies (Multigate MOSFETs, Polymer Transistors, Molecular Electronics etc.)
  • CMOS Reliability
  • Bio-MEMS

BRIEF PROFILE

COURSES OFFERED

ACADEMIC BACKGROUND

  • M.Tech, IIT Bombay, 1991
  • Dr.Ingenieur (magna-cum-laude), Faculty of Electrical Engineering, Universitaet der Bundeswehr Munich, Germany, 1997. (Doctoral thesis:Planar-Doped-Barrier Sub 100 nm Channel Length MOSFETs)
  • EE Department, University of California, Los Angeles: 1997-1998 (Post-doctoral fellow)

WORK EXPERIENCE

  • Professor, EE Department, IIT Bombay, Powai, Mumbai (current)
  • Visiting Professor, Nanyang Technological University, Singapore (since 2005)
  • Head, ("Centre for Research in Nanotechnology & Science"), IIT Bombay (Jan 2006-Jan 2007)
  • EE Department, University of California, Los Angeles: 1997-1998 (Post-doctoral fellow)
  • Prof. Rao has held short term visiting positions (May-July) at the University of California,Los Angeles (2001), Universitaet der Bundeswehr, Munich (2003), Tokyo Institute of Technology, Tokyo (2005), & Monash University, Melbourne (2007).

AWARDS & HONOURS

  • 2005 “Dr. Shanti Swarup Bhatnagar Prize in Engineering Sciences” presented by the Hon'ble Prime Minister, Govt.of India(S.S.Bhatnagar Prize) (the highest scientific award for researchers in India)
  • 2008 'The Materials Research Society of India (MRSI)-ICSC Superconductivity & Materials Science Prize' (presented at the 19th Annual General body meeting of the MRSI by Dr. R.A.Mashelkar, President, MRSI)
  • 'Swarnajayanti Fellowship' Award (2003-04), Department of Science and Technology, Govt. of India (Swarnajayanti Fellowship) (this prestigious fellowship is instituted by Govt. of India in 1997 to mark 50 years of India's independance)
  • Editor, IEEE Transactions on Electron Devices (since 2004)

(IEEE T-ED Editorial Board)

  • IETE M.N.Saha Memorial Award for the best application oriented paper in 2004 in a IETE journal & the Best paper award, 2005 IMAPS India National conference
  • Over 200 Research Publications in refereed International Journals and Conference Proceedings and two patents (US patent No. 6,067247 on SRAM Cell) & Over 100 keynote & invited talks at various international conferences, workshops, academic institutions and industries all over the world in the area of Nanoelectronics
  • Prof. Rao interacts closely with semiconductor industries such as Intel, IBM, Infineon, International Rectifier Corporation,IMEC etc., and has many ongoing industry sponsored projects in the area of Silicon CMOS devices. Prof. Rao’s work on fringing field effects in high-k gate dielctric MOSFETS & circuits is widely cited by the industry, while his work on Lateral Asymmetric Channel (LAC) devices has been successfully applied in reducing the sub-threshold leakage in mobile devices by the semiconductor industries. For an industrial applicaton of his work, please click (here).

NATIONAL LEVEL ADVISORY COMMITTEES

  • Member, Nano Applications and Technology Advisory Group (NATAG),NANO MISSION, Department of Science & Technology (DST),Govt. of India
  • Member, “Working Group on Nanotechnology”, Department of Information Technology (DIT), Ministry of Communication & Information Technology, Government of India
  • Member, Programme Advisory Committee (PAC), Electrical, Electronics & Computer Engineering, Department of Science & Technology (DST), Govt. of India (since 2007)
  • Member, Programme Advisory & Review Committee (PARC-4), National Programme on Micro and Smart Systems (NPMASS), Govt. of India
  • Member, Academic and R&D Initiatives in the area of Info-Nano-Biotechnology for the 11 th Five Year plan, Govt of India
  • Member of Academic Planning, Advisory & Evaluation Boards of various Universities and Educational Institutions in India
  • Member/Chairman of various research project monitoring committees including the (i) Electronic Design Centre project, SAMEER, Chennai (ii) Nano-Metrology facility at the National Physical Laboratories, Delhi (iii) Nano-device Characterization project at VNIT, Nagpur (iv)Nano-scale MOSFET project at Punjab University etc.

PROFESSIONAL SOCIETY ACTIVITIES/EDITORIAL BOARD MEMBER

  • Editor, IEEE Transactions on Electron Devices (since 2004)

(IEEE T-ED Editorial Board)

  • Member of the technical subcommittee “Characterization, Reliability, and Yield”, (2008 IEEE International Electron Devices Meeting (IEDM)), San Francisco, USA, December 2008.
  • Honorary Editor, IETE Journal of Research in the area of “Electronics Devices & Components (since March 2007)
  • Member, Editorial Board, The Open Applied Physics Journal (OAP) (a peer reviewed international Open Access journal) & “Recent Patents in Electrical Engineering”, (Bentham Science Publishers)
  • Vice-Chair, IEEE Asia-Pacific Regions/Chapters Subcommittee (w.e.f.Jan 2007)
  • Editor, VSI Vision, VLSI Society of India (2005-2006)
  • Distinguished Lecturer (DL), IEEE Electron Devices Society (EDS) (IEEE-EDS Distinguished Lecturer Program)
  • Panel member, IEEE Electron Devices Society (EDS) Industry Short Course program (IEEE-EDS Industry Short Course Program)
  • Chairman, IEEE AP/ED Bombay Chapter (2003-2004)
  • Member, Executive Committee, IEEE Bombay Section (2005-2006)
  • Member, Executive Committee, IETE Bombay Section (2002-2003)
  • Member, IEEE Electron Device Society (EDS) Membership Committee (2006-2007)
  • Chairman, Organizing Committee, 17 th International Conference on VLSI Design, Mumbai, 2004
  • Chairman, Organizing Committee, 2005 IMAPS India National Conference on “Microelectronics & VLSI”
  • Chairman, Organizing Committee, 14 th International Workshop on Physics of Semiconductor Devices (IWPSD), Dec 16-20, 2007, Mumbai (IWPSD 2007)
  • Co-chair, Organizing Committee, International Conference on Nanotechnology & Health Care Applications (NateHCA - 07), Oct 11-13, 2007, Mumbai
  • Member, Emerging Applications and Technologies (EA&T) sub-committee, Asian Solid-State Circuits Conference (Asian Solid-State Circuits Conference)
  • Publicity Co-chair, Nano-Net 2006: International Conference on Nano-Networks, Lausanne, Switzerland, September 14-16, 2006
  • Member, Technical Program Committee, (Chairman, Technology Sub-committee), 20 th International Conference on VLSI Design, January 6 – 10, 2007, Bangalore
  • Member, Technical Program Committee, 2007 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'06), Portland, USA, August 27-29, 2007
  • Member, Technical Program Committee, IEEE VLSI Design & Test Symposium (VDAT) (2007- )
  • Organizing/Advisory committee member for various national/international conferences/workshops held in India
  • Reviewer for various International Journals/IEEE Transactions & Conferences.

SPONSORED/CONSULTANCY PROJECTS

Principal Investigator/Co-Investigator for the following funded sponsored / consultancy projects:
  • (Nanoelectronics Centre project) (Ministry of Communications and Information Technology, Govt. of India (ongoing) (2006-2010) - As part of this US $ 25 Million project between IIT Bombay & IISc Bangalore, supported by MCIT, two Centres of Excellence in Nanoelectronics are being established at these two institutions. These centres will have state-of-the art facilities for nano-fabrication. A close industry interaction is also envisaged as part of these centre activites involving substantial funding from leading semiconductor industries. For example, at IIT Bombay, Applied Materials has created a “Nano-manufacturing laboratory” with state of the art equipment for CMOS fabricaton. The equipment involves cluster tools for high-k, PVD & etching (for 8-inch diameter wafers) with the total cost of donation amounting to US $ 7.5 Milion. IIT Bombay has also generously funded this project as part of its internal thrust area activities. Overall, at IIT Bombay, a 100 crore facility with active involvement of Government, industry & IIT is coming up. Many of the facilities are either commissioned already or going to be comissioned in the first quarter of 2008.
  • Technology aware Design Challenges in Nano-scale CMOS Technologies (IBM Corporation) (ongoing) (2007-2008) - As part of this effort (sponsored as a IBM Faculty Award ), technology aware design challenges specific to the Finfets are currently being investigated.
  • MEMS Switches for Power Electronics Applications (Larsen & Toubro (L&T) Limited) (ongoing) (2008-2009) - As part of this project various MEMS switches are being developed for power electronics applications
  • Multigate MOSFETs (IMEC, Belgium) (2005-2007) - As part of this interaction with IMEC Belgium, Multi-gate MOSFETs are being optimized from both the device and circuit performance point of view. Novel characterization techniques are also being developed for interface characterization in MuGFETs. The Taurus TCAD tools are optimized for the IMEC process flow based on the extensive device characterization data. These optimized TCAD tools are being used for understanding the device-circuit level interactions using look-up-table based ciruit simulation approaches. A comprehensive MuGFET device-circuit simulation framework has been developed as part of this activity.
  • Novel Circuit Design Approaches with Multi-gate MOSFETs (Intel, CRL, Portland Group), Ongoing (2006-2008): Through this collaboration with the CRL group Intel, the circuit design challenges and the use of multi-gates in circuit design are being ssstematically investigated for logic as well as mixed-signal applications.
  • Optimization of Power Transistors (International Rectifier Corporation & Vishay Siliconix–USA) (2006-2007): As part of this project, IRC’s power transistor designs are being optimized for improved performance.
  • I/O Circuit applications for Novel devices (Infineon, Munich, Germany) (2007-2009) (ongoing): Efforts are made to find circuit solutions which reduce the special requirements for the IO device giving a relief to the process complexity. On the other hand, it is seen that while the technology shrink continues the system requirements to the IO circuit remains constant or even becomes more demanding e.g. by the request of multi GHz interfaces. This means that the gap between the IO voltage and the capability of pn-junctions and dielectrics to handle the higher voltage increases. Novel IO devices are proposed to overcome this problem which are compliant with the processing of the thin gate oxide devices and do not cause large additional process costs.
  • Radiation Sensors/Silicon Drift Detectors (BARC) (2005-2006) - as part of this project, novel detectors are being fabricated on silicon for low noise and high resolution X-ray spectroscopy and other applications.
  • Nitride Based Passive Dosimeters (MHRD, Govt. of India)(2005-2006) - as part of this project a nitride based dosimeter technology will be developed that does not require external power supply during the sensing operation.
  • Sub 65 nm node CMOS - Novel Devices (2005-2009)(Department of Science and Technology, Govt. of India [UNDER THE SWARNAJAYANTI FELLOWSHIP SCHEME](ongoing) - we are looking at realizing novel structures experimentally which would overcome the scaling problems beyond the 65 nm technology node. Various device concepts are currently being looked into using advanced 3-D simulations, before venturing into their experimental realization.
  • CMOS Noise/Device Characterization for Mixed Signal Applications (Department of Science and Technology, Govt. of India (2004-2006) - as part of this sponsored project, extensive experimental characterization of sub 100 nm MOSFETs has been carried out for their noise and other analog/digital device figures of merit.
  • Mixed Signal CMOS: Intel (2003-2005) - through this research collaboration with Intel (CRL-Portland), scaled CMOS technology optimizations have been looked at and a methodology developed for mixed-signal circuits.
  • Biosensors for Cardiac Applications: National Programme on Smart Materials (NPSM), ADA, India (2004-2006) - a full system development containing bio-sensors for myocardial infarction has been initiated as part of this interdisciplinary project, involving faculty and students from EE, Material Science, Bio, Chemistry and Mechanical Engg. departments. The work is currently continuing as part of the Nanoelectronics centre activities with the goal to develop a lab-on-chip for cardiac diagnostics.
  • “Nanotechnology” (Celebration Motion Pictures)(2005-2006)- as a consultant, Prof. Rao advised a company for creation of video content on Naotechnology for children. 13 episodes (of 30 minutes each) addressing different aspects of Nanotechnology were created and are being telecast currently on Doordarshan India (Sunday mornings). The idea for doing this was to make Nanotechnology and the associated areas interesting for children by using lively characters and animation.
  • Molecular Electronics: Cross Disciplinary Research Group (CDRG), IITB (2004-2006) - as part of this interdisciplinary project, various molecules have been chemically synthesized and electrically characterized for various electrical applications. The work is continuing as part of the Nanoelectronics centre activities.
  • Plasma Damage Characterization: Department of Science and Technology, Govt. of India (2002-2004) - as part of this project, plasma implantation induced damage on sub 3 nm gate oxides is investigated
  • Understanding and Modeling of Fringing fields in High-K Gate Dielectric MOSFETs: Intel (2000-2002) - an analytical model has been developed for circuit simulations, by taking into account the fringing fields in high-k gate dielectric MOSFETs. Extensive device optimizations have been carried out to optimize a device employing high-k gate dielectrics.
  • Oxide scaling effects on design issues: Intel (2000-2002) - using an in-house look-up-table simulator, extensive work has been done at optimizing the gate dielectrics for circuit applications.
  • Channel Engineering for Sub 100 nm MOSFETs:Department of Science and Technology, Govt. of India (2000-2002) - process window for Single Halo MOSFETs has been identified for optimum mixed-signal performance using extensive device/circuit simulations

(SELECTED) INVITED TALKS/TUTORIALS

Prof. Rao has delivered over 100 invited/ keynote addresses at various national/international conferences all over the world.

Forthcoming:

  • Italy-India Forum for the opportunities of cooperation in Biotechnology & Nanotechnology, 21-22 April 2008, Taj Westend, Bangalore (Special Plenary lecture)
  • Università della Calabria, Arcavacata di Rende (CS), Italy, May 7-June 30,2008 1)
1)
Invited Lectures under the Distinguished Speaker programme)
  • 5 th International Conference on Smart Materials, Structures and Systems,July 24-26, 2008, Indian Institute of Science, Bangalore (Invited talk)
  • Guest lectures at the School of Materials Science & Engineerng, Nanyang Technological University (NTU), Singapore (Aug 13-17 & Nov 2-7, 2008) (Invited Lectures)
  • International Conference on Biomedical Engineering and Nanotechnology (ICBENT – 2008),Oct 21-23, 2008, Kolhapur (Key note address)
  • International Conference on MEMS (ICMEMS 2009), Indian Institute of Technology Madras, Chennai, INDIA, January 3-5, 2009 (Invited talk)
Selected recent invited talks (2007-2008):
  • 3rd Nanotechnology Conclave, Organized by the Confederation of Indian Industry (CII) jointly with the Nomura Research Institute (NRI) Japan and the Tamil Nadu Technology Deveopment & Promotion Centre, March 19-20, 2008, Hotel Le royal Meridian, Chennai (Invited Plenary talk)
  • Workshop on Science-Society Interface in Emerging Technologies, Jointly organized by the Energy and Resources Institute (TERI)& NISTADS,March 27-28, 2008, New Delhi (Invited plenary talk)
  • Short course, BRNS Basic Sciences School on 'Condensed Matter Interface with Chemistry and Biology' March 3-14, 2008, organized by BARC & the Homi Bhabha Centre for Science Education, Mumbai (Invited Lectures)
  • Symposium on BioNanotechnology & Phamaceuticals, March 13-14, 2008, Organized by the Centre for Cellular & Molecular Biology (CCMB), Hyderabad in association with the Discovery Park, Purdue University (Invited talk)
  • National Science Day-2008 Celebrations, Shivaji University (Popular Lecture)
  • 'MRSI-ICSC Superconductivity & Materials Science Prize' Lecture , Annual General Meeting of MRSI, Thiruvananthapuram, February 14-16, 2008 (Award lecture)
  • “Second Roundtable on Indo-US Perspectives in Science and Technology”, organized at NIAS, IISc Bangalore, Februray 16-17, 2008 (Invited talk)
  • TECHFEST, 25-27 January 2008, IIT Bombay (Invited Lecture)
  • Symposium on “Compact Modeling of Advanced MOSFET structures and Mixed Mode Applications”, New Delhi, India, January 5-6, 2008 (IEEE Electron Devices Society Distinguished Lecture)
  • 21st International Conference on VLSI Design, Jan 4-8, 2008 Hyderabad (Invited))
  • US-India Nanoscience and Engineering Institute (USINSEI), January 9-18, 2008, Chennai
  • National Conference on Applications of Nanotechnology, December 27-29, 2007, Jodhpur (keynote adress)
  • Indo-Australia Symposium on Multifunctional Nanomaterials, Nanostructures and Applications“, University of Delhi, 19 - 21 December 2007 (Invited Talk)
  • Bangalore Nano 2007, Organized by the Department of IT and Biotechnology, Government of Karnataka, JNCASR and MM Activ, December 6-7, 2007, Bangalore (Invited Talk)
  • Tutorial as part of the National Conference on Devices, Intelligent Systems and Communication (MITDISC07), December 6, 2007, Manipal (organized as part of the Manipal Institute of Technology (MIT) Golden Jubilee Celebrations) (Invited Talk)
  • Second National Seminar on IEDs - Targeting the Improvized Explosive Devices (IED), organized by the College of Military Engineering (under the aegis of HQ Army Training Command (ARTRAC), 27-28, November, 2007 (Invited Talk)
  • Applied Materials, Bangalore, Nov 13, 2007 (Invited Lectures)
  • IBM Asia-Pacific University Relations conference, Bangalore, India, Nov 13-14, 2007 (Invited)
  • Indo-Brazil-South Africa (IBSA) Nanotechnology Workshop, Capetown, South Africa (sponsored by the Department of Science & Technology (DST)- South Africa, DST-Govt of India, Ministry of Science & Technology-Federal Republic of Brazil, Nov 18-24, 207 (Invited Talks)
  • Guest lectures at the School of Materials Science & Engineerng, Nanyang Technological University (NTU), Singapore (Aug 13-17 & Oct 2-Nov 7, 2007) (Invited Lectures)
  • 2007 Intel Asia Academic Forum, October 24-26,2007, New Delhi (Invited)
  • Technology Conference, Analog Devices Bangalore, October 26, 2007 (Keynote address)
  • 3 rd International Conference on Nanomedicine & its Applications, October 18-19, 2007, Thanjavur, India (Invited Talk)
  • International Workshop on Nanometrology, October 17-19, 2007, Delhi (Invited Talk)
  • 4th International Conference on Nanotechnology & Healthcare Applications, Mumbai, October 11-13, 2007 (Keynote address)
  • The 10 th International Conference on Advanced Materials (ICAM), organized by the International Union of Materials Research Societies (IUMRS), Bangalore, India, October 8-13, 2007 (Invited Talk)
  • Short-couse for Indian Police Service (IPS) Officers on the latest trends in technology for crime prevention & detection, November 9, 2007, IIT Bombay (Invited Talk) (organized by the CEP Cell, IIT Bombay)
  • 5th Knowledge Millennium Summit on B2B in Biotechnology and Nanotechnology, September 18-21, 2007, New Delhi (organized by the The Associated Chambers of Commerce & Industry of India (ASSOCHAM) in associaton with the Ministry of Science & Technology, Department of Biotechnology, The Council for Scientific & Industrial Research , Government of India, and the Foundation for Innovation and Technology Transfer, IIT Delhi) (Invited Talk)
  • Intel Regional Academic Forum 2007, Bangalore, August 21-22, 2007 (Invited Talk)
  • Applied Materials, Bangalore, July 31, 2007 (Invited Talk)
  • Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT), IEEE EDS Hongkong Chapter, Hongkong, July 23, 2007 (IEEE EDS Distinguished Lecture)
  • Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT), IEEE EDS Singapore Chapter, Singapore, July 25, 2007 (IEEE EDS Distinguished Lecture)
  • University of Melbourne, Australia, July 10, 2007 (Invited Talk)
  • Monash University, Melbourne, Australia, June 20, 2007 (Invited Talk)
  • Conference of “Shanti Swarup Bhatnagar Awardees” (Bhatnagar Laureates Symposium), Organized by the Devi Ahalya University, Indore, March 8-10, 2007 (Invited Talk)
  • Workshop on Nanotechnology – Current Status and Challenges, Indian Institute of Technology (IIT) Delhi, Hauz Khas, New Delhi March 17-18, 2007 (Special Invited Lecture)
  • Banquet speech, “Management Day” celebrations (All India Managament Association, New Delhi), organized by the Rohilkhand Management Association, Bareilly, February 21, 2007 (Keynote address)
  • National Review and Coordination Meeting on Nanoscience & Nanotechnology, Nanoscience and Technology Initiative (NSTI), DST, Govt. of India, Hyderabad, Feb 21-23, 2007 (Plenary talk)
  • International Workshop on Complex Dynamics of Physiological Systems: From Heart to Brain, Organized by Department of Physics, Presidency College, Kolkata, February 12-14, 2007 (Invited Talk)
  • International Conference on MEMS AND NANOTECHNOLOGY, (TIMA 2007), Trichy, India, January 4-6, 2007 (Keynote address)
  • IEEE Electron Devices Society Mini-colloquium, Organized by the IEEE EDS Calcutta Chapter & the North Jersey Chapter (USA), Bhubaneswar, January 3, 2007 (IEEE EDS Distinguished Lecture)
Selected past presentations: 2006:
  • National Conference on Sensors and Actuators: Emerging Technological Challenges (NCSA-06), December 21-22, 2006, Central Glass and Ceramic Research Institute, Kolkata (Invited Talk)
  • National Conference on Current Trends in Technology, November 30-Dec 2, 2006, Nirma University, Ahmedabad (Invited Talk)
  • IITB Continuing Education Program for Indian Police Service (IPS) Officers, November 23, 2006, IIT Bombay (Invited Talk)
  • CBIT, Hyderabad, November 25-26, 2006 (Invited Tutorial)
  • Indo-UK conference in Nanoscience and Technology, Organized by the S.N. Bose National Centre for Basic Sciences and the British council,November 20-21,2006, Calcutta (Invited)
  • Guest lectures at the Nanyang Technological University (NTU), Singapore (Aug 12-19 & Oct 25-28, 2006) (Invited Lectures)
  • Address to the Young Scientists at the 'Group Monitoring Workshop for Fast Track Scheme for Young Scientists', Organized by the Department of Science & Technology (DST), September 25, 2006, Nagpur (Keynote address)
  • IEEE Student Branch, VNIT Nagpur, September 25, 2006 (Invited)
  • International Conclave on Emerging Technologies (Emerge Tech), 28th September 2006, Hotel Le Meridien, New Delhi (Organized by the Confederation of Indian Industry (CII)) (Invited)
  • Colloquium @ Indira Gandhi Centre for Atomic Research (IGCAR), Kalpakkam, September 19, 2006 (Invited)
  • National Workshop for Engineering College Faculty, GMRIT, Andhra Pradesh, Sept 8-10, 2006 (Invited Tutorial)
  • Ideaz Workshop, organised by The Entrepreneurship Cell, IIT Bombay, August 30, 2006 (Invited Talk)
  • Cadence Design Systems India, New Delhi, July 7, 2006 (Invited Talk)
  • DIMENSIONS OF NANOTECHNOLOGY:Science, Technology and Society, sponsored by Department of Science and Technology, Government of India, National Institute of Advanced Studies, Bangalore, June 26-30, 2006 (Invited Talk)
  • Intel Capital CEO Summit, May 26, 2006, Mumbai, India (Invited Talk)
  • Short term course on Nanoelectronics, NIT Calicut, May 8, 2006 (Invited Lectures)
  • Workshop on MEMS and Nanotechnology, May 15-18 2006, NTU Singapore (Invited Talk)
  • Indo-Chinese Workshop on 'MEMS Devices and Related Technologies',April 5-7, 2006, NPL, New Delhi (Invited Talk)
  • World Nano-Economic Congress (WNEC)(www.world-nano.com), Hyatt Regency in Mumbai, India, March 27-29, 2006 (Invited Talk)
  • “Multi-disciplinary Approaches to Nanotechnology R&D”, National Science Day oration, Metcalfe House, Dr. Bhagvantam Auditorium (Organized by Defence Science Forum), February 28, 2006 New Delhi (Plenary talk)
  • Workshop on Fabrication and Packaging of Sensors, Pune University, February 26, 2006 (Invited Talk)
  • International Workshop on Nanoscience and Technology (held jointly with ICTP, Trieste, Italy), Anna University, Madras, February 13-17, 2006 (Invited Talk)
  • 8th CRSI National Symposium in Chemistry, IIT-Bombay, February 3-5 , 2006 (Invited Talk)
  • International Workshop on Nano CMOS, sponsored by IEEE EDS Japan Chapter Jan 30- Feb 1, 2006, Mishima, Shizuoka prefecture, Japan (Invited Talk)
  • BARC, Mumbai, Jan 19, 2006 (Invited Talk)
Selected Talks 2004-2005:
  • 13 th International Workshop on The Physics of Semiconductor Devices (IWPSD), December 13-17, 2005, New Delhi (Invited Talk)
  • School of Materials Science & Engineering, Nanyang Technological University (NTU), Singapore, August 14-20 & October 9-15, 2005 (Invited Lectures)
  • IEEE EDS Distinguished Lecture, September 17-18, 2005, Kalyani University, Sponsored by the IEEE EDS Calcutta Chapter
  • Workshop on Nanotechnology, Satellite Symposium under the aegis of Platinum Jubilee Celebrations of the National Academy of Sciences, India, September 8-9,2005, IIT Bombay (Invited Talk)
  • Tokyo Institute of Technology, Japan, sponsored by the IEEE EDS Japan Chapter, July 19, 2005 (IEEE EDS Distinguished Lecture)
  • Tokyo Institute of Technology, Japan, July 6, 2005 (Invited Talk)
  • IEEE Workshop on Low Power Design Techniques, Indian Institute of Science, Bangalore, Feb 25-26, 2005 (IEEE Distinguished Lecture)
  • Tutorial conducted (along with Prof. Mukhopadhyay and Prof. Basu, Jadavpur University) at the 18 th International Conference on VLSI Design, January 3-7, 2005, Calcutta, India
  • Indo-US Worskhop on “Nanotechnology: Issues in Interdisciplinary Research and Education” August 11-13, 2004, IISc Bangalore (Invited Talk)
  • AMD India Centre, January 24-27, 2004 (Invited Lectures)
  • Infineon, Munich, Germany, July 7, 2003 (Invited Talk)
  • Universitaet der Bundeswehr, Munich, Germany, July 1, 2003 (Invited Talk)
  • Nanyang Technological University, Singapore, July 9, 2001 (Invited Talk)
  • Circuit Research Lab, Intel, Portland, USA, June 30, 2001 (Invited Talk)
====Ph.D. STUDENTS===== (as Guide/Co-guide): Graduated:
  • C.R.Manoj (Guide: V.Ramgopal Rao/M.B.Patil)- Optimization and Scaling of FinFet Structures (Graduating in 2008)
  • Venkanarayan Hariharan (Guides: V.Ramgopal Rao/J.Vasi)- Simulation & Modeling of Multi-gate FETs (Graduating in 2008)
  • Shree prakash Tiwari (Guide: V.Ramgopal Rao) - Novel Device Structures for Polymer Electronics (Graduating in 2008)
  • Nitin Kale (Guide:V.Ramgopal Rao)- Making Hotwire CVD a Viable Technology Alternative for Bio-MEMS applications: System Design, Fabrication & Characterization (Graduated in 2008 - joined TSMC, Taiwan)
  • Manoj Joshi (Guides: S.Mukherji/V.Ramgopal Rao)-Micro-fabricated Biosensors for Cardiac Diagnostics (Graduated in 2007 - joined TSMC, Taiwan)
  • K.Narasimhulu (Guide: V.Ramgopal Rao)- CMOS Device Design & Optimization for Mixed Signal Applications (Graduated in 2006- joined IBM Hopewell Junction, NY, USA)
  • Neeraj K. Jha (Guides: V.Ramgopal Rao/M.B.Patil)-Reliability Studies on Deep Sub-micrometer MOSFETs under Analog Operating Conditions (Graduated in 2005-joined TSMC, Taiwan)
  • D.Vinay Kumar (Guides: M.B.Patil/V.Ramgopal Rao)- Development of a Look Up Table Simulator for Advanced Applications (Graduated in 2005-currently with Synopsis, India)
  • Manjula Rani (Guides: J.Vasi/V.Ramgopal Rao)-Border Trap Characterization for Sub 100 nm MNSFETs (Graduated in 2004 - joined Cypress, Bangalore)
  • Nihar Ranjan Mohapatra (Guides: V.Ramgopal Rao/M.P.Desai)-CMOS Scaling and Optimization for Logic and Memory Applications (Graduated in 2004-currently with AMD, Dresden, Germany)
  • Najeeb-Ud-Din (Guides: J.Vasi/V.Ramgopal Rao)- Single Halo Deep Submicron SOI MOSFETs for Analog Applications (Graduated in 2003 under the QIP Programme for college teachers, rejoined NIT-Srinagar)
Currently pursuing their Ph.D.:
  • Mrunal. A. K (Guide: V.Ramgopal Rao) - Bottoms-Up Approaches for Nano-scale CMOS Scaling
  • Mayank Srivastava (Guides: V.Ramgopal Rao/Dr. Maryam Shojaei): I/O Device Optimization for the sub 32 nm Node CMOS Technologies
  • Angada B Sachid (Guides: V.Ramgopal Rao/Dr. Maryam Shojaei): Multi-Gate MOSFETs
  • V.Seena (Guides: V.Ramgopal Rao/S.Mukherji) - Micro-fabricated Novel Sensor Structures for Medical Diagnostics
  • R.Ramesh (Guides: V.Ramgopal Rao/M.B.Patil)– ASIC Design using Polymer Transistors
  • Ravi Shankar Dudhe (Guides: V.Ramgopal Rao/Anil Kumar) - Polymer Based Sensors for Explosive Detection
  • Debabrata Maji (Guides:S.D.Gupta/V.RamgopalRao)-Gate Dielectrics for Germanium CMOS
  • Brajesh Pandey (Guides: A.N.Chandorkar/V.Ramgopal Rao) - I/O Optimization Issues for Nano-CMOS
Post-graduate Students * Prof. Ramgopal Rao has supervised over 75 post-graduate/dual degree theses in the area of microelectronic/nanoelectronics at IIT Bombay till date. ====INTERNATIONAL COLLABORATIONS==== PAST/ONGOING INTERACTIONS/RESEARCH COLLABORATIONS: (interactions that resulted in joint publications/projects)
  • Intel-(Circuit Research Lab) (high-k modeling, mixed-signal CMOS, Multi-gate MOSFETs) (Current)
  • IBM (Technology Aware Design Challenges) (Current)
  • Infineon, Munich, Germany (IO Circuit Optimizations using Novel Devices) (Current)
  • Università della Calabria, Italy (High-k characterization for CMOS)(Current)
  • Tokyo Institute of Technology-Japan (Finfets) (Current)
  • Nanyang Technological University-Singapore (Organic Electronics) (Current)
  • IMEC-Belgium (Multi-gate MOSFETs)
  • Vishay Siliconix - USA (Super-junction Power MOSFETs)
  • International Rectifier Corporaton (Super-junction Power MOSFETs)
  • National University of Singapore (High-k Dielectric Characterization)
  • University of California -Los Angeles (Single Halo MOSFETs & Mixed signal CMOS)
  • Yale University (JVD nitrides)
  • Universitaet der Bundeswehr Munich-Germany (Vertical transistors)
====BOOKS WRITTEN==== Book Chapters:
  • “Impact of high-K gate dielectrics on the device and circuit performance of Nano-scale MOSFETs”, Manoj CR, V.Ramgopal Rao, “Dielectric Materials: Research, Technology and Applications”, Edited by Dr. Frank Columbus, Nova Science Publishers, Inc. (to be published)
  • “Development of a Bio-Chip for Cardiac Diagnostics”, Manoj Joshi, Nitin Kale, R.Lal, S. Mukherji and V. Ramgopal Rao; to be published in a CRC Handbook of Biomedical Engineering (3rd ed.), Edited by David Reisner, CRC Press, 2008
  • “Rare Earth Oxides in Microelectronics”, Kuniyuki Kakushima, Kazuo Tsutsui, Sun-ichiro Ohmi, V. Ramgopal Rao, and Hiroshi Iwai; RARE EARTH OXIDE THIN FILMS: GROWTH, CHARACTERIZATION , AND APPLICATIONS - TOPICS IN APPLIED PHYSICS 106: 345-365 2007 (Springer-Verlag Series on “Topics in Applied Physics”, Edited by M. Fanciulli and G. Scarel, Ed. 2007)
  • “Polymers in Electronics”, Saurabh Goyal, V.Ramgopal Rao; Specialty Polymers: Materials and Applications, I.K. International Private Limited, Edited by Dr. Faiz Mohammad, Ed. 2007, Category : Physical Sciences, ISBN : 8188237655
====LIST OF PUBLICATIONS==== ==INTERNATIONAL JOURNALS /INTERNATIONAL CONFERENCE PROCEEDINGS:== (Journal papers are listed first followed by the conference papers)
  1. Debabrata Maji, Felice Crupi, Gino Giusi, Calogero Pace, Eddy Simoen, Cor Claeys, V. Ramgopal Rao,”DC and Noise Properties of the Gate Current in Epitaxial Ge p-Channel Metal Oxide Semiconductor Field Effect Transistors with TiN/TaN/HfO2/SiO2 Gate Stack“, Accepted for publication, Applied Physics Letters (published by the American Institute of Physics), 2008
  2. Mayank Shrivastava, Maryam Shojaei Baghini,Dinesh Kumar Sharma,V. Ramgopal Rao, “A Novel and Robust Approach for Common Mode FeedBack using IDDG FinFET”, To appear in IEEE Transactions on Electron Devices, 2008
  3. S.P. Tiwari, Srinivas P, Shriram S, Nitin S. Kale, Subodh G Mhaisalkar, V. Ramgopal Rao, “Organic FETs with Hot-wire CVD (HWCVD) Silicon Nitride as a Passivation and Gate Dielectric Layer”, Volume 516, Issue 5, Pages 770-772, Thin Solid Films, January 2008
  4. Mrunal A. Khaderbad, S. Mukherji and V. Ramgopal Rao, “DNA Based Nanoelectronics”, To appear in Recent Patents on Electrical Engineering, Bentham Science Publishers, 2008 (Invited review article)
  5. C.R.Manoj, Meenakshi N, Dhanya V. and V. Ramgopal Rao, “Device Design & Optimization Considerations for Bulk FinFETs”, IEEE Transactions on Electron Devices, Vol. 55, No.2, p. 609-615, February 2008
  6. Angada B. Sachid, Manoj C. R., Dinesh K. Sharma, V. Ramgopal Rao, “Gate Fringe Induced Barrier Lowering in Underlap FinFET Structures and its Optimization”, IEEE Electron Device Letters, Vol. 29, Issue 1, pp.128-130, January 2008
  7. T. Cahyadi, H. S. Tan, S. G. Mhaisalkar, P. S. Lee, F. Boey, Z.K. Chen, C. M. Ng, V. Ramgopal Rao, G. J. Qi, “Electret mechanism, hysteresis, and ambient performance of sol-gel silica gate dielectrics in pentacene field-effect transistors”, APPLIED PHYSICS LETTERS (published by the American Institute of Physics), vol. 91, 242107, 2007
  8. S.R. Rajwade, P.D. Kulkarni, S. Mukherji, K.K. Rao, V. Ramgopal Rao,” Polymerization on DNA Templates for Nanoelectronics Applications“, Journal of Scanning Probe Microscopy, Volume 2, No.1, June, 2007 , pp. 32-35(4), American Scientific Publishers
  9. S.P. Tiwari, E. B. Namdas, V. Ramgopal Rao, and S.G. Mhaisalkar “Solution processed n-type Organic Field Effect Transistors with high ON/OFF current ratios based on fullerene derivatives” IEEE Electron Device Letters, Vol. 28, Issue: 10, p. 880, 2007
  10. Debabrata Maji, S. P Duttagupta, V. Ramgopal Rao, Chia Ching Yeo, and Byung-Jin Cho, “Border Trap Characterization in High-k strained-Si MOSFETs”, IEEE Electron Device Letters, Vol. 28, p. 731, Issue:8, August 2007
  11. Yusuke Kobayashi, C. Raghunathan Manoj, Kazuo Tsutsui, Venkanarayan Hariharan, Kuniyuki Kakushima, V. Ramgopal Rao, Parhat Ahmet, and Hiroshi Iwai, “Parasitic effects in multi-gate MOSFETs”, IEICE Transactions on Electronics (Japan), Vol. E90-C, No.10, October 2007
  12. C.R.Manoj, V. Ramgopal Rao, “Impact of High K Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs”, IEEE Electron Device Letters, Vol. 28, Issue: 4, p.295, April 2007
  13. S.P. Tiwari, Ramesh R.N., Srinivas P., Harshil N. Raval, Yuan Yuan Zhang,S.G. Mhaisalkar, V. Ramgopal Rao, “Ambipolar Organic FETs with semi-conducting blends for CMOS-type Organic circuits”, Accepted for publication, Thin Solid Films, 2007
  14. S.P. Tiwari, D. Maji, Srinivas P., Ramesh R.N., Harshil N. Raval, Nitin S. Kale, S.G. Mhaisalkar, V. Ramgopal Rao, “Patterned gate Organic FETs and Inverter Circuits with Hafnium Oxide Gate dielectric”, Accepted for publication, Thin Solid Films, 2007
  15. Manoj Joshi, Nitin Kale,S.Mukherji, R.Lal, V.Ramgopal Rao, “Affinity Cantilever Sensors for Cardiac Diagnostics”, Indian Journal of Pure & Applied Physics, Vol 45, pp. 287-293, April 2007
  16. Manoj Joshi, Nitin Kale, Rakesh Lal, V. Ramgopal Rao, Soumyo Mukherji, “A Novel Dry Method for Surface Modification of SU-8 for Immobilization of Biomolecules in Bio-MEMS,” Biosensors and Bioelectronics, vol. 22, no.11,pp. 2429-2435, May 2007
  17. T. Cahyadia, J. N. Tey, S. G. Mhaisalkar,V. Ramgopal Rao, R. Lal, Z. H. Huang and G. J. Qi, “Investigations of enhanced device characteristics in pentacene-based field-effect transistors with sol-gel interfacial layer”, Applied Physics Letters, 90(11): 056711, 2007
  18. S.Chakraborty, A.Mallik, C.K.Sarkar and V. Ramgopal Rao, “Impact of Halo Doping on the Subthreshold Performance of Deep Submicrometer CMOS Devices and Circuits for Ultra Low Power Analog/Mixed-Signal Applications,” IEEE Transactions on Electron Devices,Vol. 54, pages 241-248, February 2007
  19. Manoj Joshi, Richard Pinto, V. Ramgopal Rao, Soumyo Mukherji, “Silanization and Antibody Immobilization on SU-8”, Applied Surface Science, Vol.253,No.6, pp.3127-3132, January, 2007
  20. K. Narasimhulu, I.Venkata Suryam Setty, V. Ramgopal Rao, “The Effect of Single Halo Doping on the Low-Frequency Noise Performance of Deep Sub-micron MOSFETs”, IEEE Electron Device Letters,Volume 27,Issue 12, Pages:995-997,December 2006
  21. Nitin S. Kale, V. Ramgopal Rao, “Design and Fabrication Issues in Affinity Cantilevers for bio-MEMS applications”, (IEEE/ASME) Journal of Microelectromechanical Systems (J-MEMS),Volume 15, Issue 6, Pages:1789 - 1794, December 2006
  22. Nitin Kale, Ashwani Mehta, Manoj Joshi, Soumyo Mukherjee, Rakesh Lal, R. Pinto, P. R. Apte, V. Ramgopal Rao, “Affinity cantilever and EIS based biosensors for Cardiac Diagnostics”, ISRAPS (Indian Society for Radiation and Photochemical Sciences) Bulletin, Vol. 18, p. 24-29, October 2006 (Invited)
  23. Mayank Gupta, V.Vidya, V.Ramgopal Rao, Kun H. To, J.C.S.Woo, “Optimization of Sub-100 nm Gamma-gate Si-MOSFETs for RF Applications”, Wireless Design and Development magazine (Featured Technology Article), December 2005 (Invited)
  24. Neeraj K. Jha, P. Sahajananda Reddy, D.K. Sharma and V. Ramgopal Rao, “NBTI Degradation and its Impact for Analog Circuit Reliability”, IEEE Transactions on Electron Devices,pp. 2609-2615, December 2005
  25. Amarchand Sathyapalan, Anup Lohani, Sangita Santra, Saurabh Goyal, M. Ravikanth, Soumyo Mukherj, V. Ramgopal Rao, “Preparation, characterization and electrical properties of a novel self-assembled meso-pyridyl pophyrin monolayer on gold surfaces”, Australian Journal of Chemistry, Vol.58, pp. 810-816, 2005
  26. Neeraj K.Jha, V.Ramgopal Rao, “A New Oxide Trap Assisted NBTI Degradation Model”, IEEE Electron Device Letters, Volume: 26, Issue: 9, September 2005, pp.687-689
  27. M. V. Rammohan Reddy, D. K. Sharma, M.B.Patil and V. Ramgopal Rao, “Power-Area Evaluation of Various Double-Gate RF Mixer Topologies”, IEEE Electron Device Letters, Volume: 26, Issue: 9, June 2005, pp.664 – 666
  28. D. V. Kumar, K.Narasimhulu, P. S. Reddy, M.Shojaei, D. K. Sharma, M. B. Patil, V.Ramgopal Rao, “Evaluation of the Impact of Layout on Device and Analog Circuit Performance with Lateral Asymmetric Channel MOSFETs”, IEEE Transactions on Electron Devices, Volume 52, Issue 7, July 2005 Pages:1603 - 1609
  29. Najeeb-ud-din, V.Ramgopal Rao, J.Vasi, “Design of 0.1 um single halo (SH) thin film silicon-on-insulator (SOI) MOSFETs for analog applications”, Semiconductor Science and Technology, vol. 20, p.895-902, 2005 (IOP Publishing Ltd, UK)
  30. Najeeb-ud-din, V.Ramgopal Rao, J.Vasi, and J.C.S.Woo, “Superior Hot Carrier Reliability of Single Halo (SH) Silicon-on-Insulator (SOI) nMOSFET in Analog Applications”, IEEE Transactions on Device and Materials Reliability, Volume 5, Issue 1, Pages: 127 - 132, 2005
  31. Pradeep Kumar Chawda, Bulusu Anand, and V. Ramgopal Rao, “Optimum Body Bias Constraints for Leakage Reduction in High–K CMOS Circuits”, Japanese Journal of Applied Physics, April, 2005
  32. K. Narasimhulu, V. Ramgopal Rao, “Deep Sub-micron Device and Analog Circuit Parameter Sensitivity to Process Variations with Halo Doping and Its Effect on Circult Linearity”, Japanese Journal of Applied Physics, April, 2005
  33. K. Narasimhulu, Madhav P. Desai, Siva G. Narendra and V. Ramgopal Rao, “The Effect of Lateral Asymmetric Channel (LAC) Doping on Deep Sub-micron Transistor Capacitances and its Influence on Device RF Performance”, IEEE Transactions on Electron Devices, Volume: 51, Issue: 9, Sept. 2004, pp. 1416 – 1423
  34. B.Anand, M.P.Desai, and V.Ramgopal Rao, “Silicon Film Thickness Optimization for SOI-DTMOS from Circuit Performance considerations”, IEEE Electron Device Letters, Volume: 25, Issue: 6 , June 2004, pp.436 – 438
  35. V.Ramgopal Rao, “Nanotechnology-A revolution in progress”, 'Electrical & Electronics' magazine, June, 2004 (Invited)
  36. K.N.Manjularani, V.Ramgopal Rao, J.Vasi, “Reliability of Ultrathin JVD Silicon Nitride MNSFETs under High Field Stressing” IEEE Transactions on Device and Materials Reliability, Vol.4,pp.18 - 23, March 2004
  37. V.Ramgopal Rao, Nihar R. Mohapatra, “Device and Circuit Performance issues with Deeply Scaled High-K MOS Transistors”, Journal of Semiconductor Technology and Science (JSTS), Korea, Special issue on Scaled Nano Devices, pp.52-62, Vol. 4, No. 1, March,2004.(Invited)
  38. Samadhan B. Patil, Anand V. Vairagar, Alka A. Kumbhar, Laxmi K. Sahu, V. Ramgopal Rao, N. Venkatramani, R. O. Dusane and B. Schroeder, “Highly Conducting P+- PolySi Deposited by HWCVD and its Applicability As Gate Material for CMOS Devices” Thin Solid Films, Vol.430, 2003, pp.63-66
  39. Nihar R. Mohapatra, Madhav P. Desai, Siva.G.Narendra, V. Ramgopal Rao, “Modeling of Parasitic Capacitances in Deep Sub-micrometer Conventional and High-K dielectric MOS Transistors” IEEE Transactions on Electron Devices, vol. 50, No.4, pp. 959-966, 2003
  40. K.N.Manjularani, V.Ramgopal Rao, and J.Vasi, “A New Method to Characterize Border Traps in Sub-Micron Transistors using Hysteresis in the Drain Current”, IEEE Transactions on Electron Devices, vol. 50, No.4, pp. 973-979, 2003
  41. Parag C. Waghmare, Samadhan B. Patil, Alka A. Kumbhar, Laxmi Sahoo, V. Ramgopal Rao, and R.O. Dusane, “Nitrogen dilution effects on structural and electrical properties of hot wire deposited a-SiN:H films for Deep Sub-micron CMOS Technologies”, Thin Solid Films, Vol.430, 2003, pp.189-191
  42. N.R.Mohapatra, D.R.Nair, S.Mahapatra, V.Ramgopal Rao, S.Shukuri, J.D.Bude, “CHISEL programming Operation of Scaled NOR Flash EEPROMs-Effect of Voltage Scaling, Device Scaling, and Technological Parameters”, IEEE Transactions on Electron Devices, vol. 50, pp.2104-2111, October 2003
  43. K.Narasimhulu, D.K.Sharma and V.Ramgopal Rao, “Impact of Lateral Asymmetric Channel Doping on Deep Sub-Micrometer Mixed-Signal Device and Circuit Performance”, IEEE Transactions on Electron Devices vol. 50, pp.2481-2489, December 2003
  44. Parag C.W, Samadhan Patil, Alka Kumbhar, R.O.Dusane, V.Ramgopal Rao, “Ultra thin Silicon Nitride by Hot Wire CVD for Deep Sub-Micron CMOS Technologies”, Microelectronic Engineering, Vol. 61-62, p. 625-629, 2002
  45. Najeeb-ud-din, Mohan V. Dunga, Aatish Kumar, J.Vasi, V.Ramgopal Rao, Baohong Cheng, J.C.S.Woo, “Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs using the GIDL Current Technique”, IEEE Electron Device Letters, vol. 23, p. 209-211, April 2002
  46. D.G.Borse, Manjula Rani K.N., Neeraj K. Jha, A.N. Chandorkar, J.Vasi, V. Ramgopal Rao, B.Cheng, J.C.S. Woo, “Optimization and Realization of Sub 100nm Channel Length Single Halo p-MOSFETs” IEEE Transactions on Electron Devices, vol.49, (no.6), June 2002.
  47. Nihar R. Mohapatra, Madhav P. Desai, Siva G. Narendra, V. Ramgopal Rao, “The Effect of High-K Gate Dielectrics on Deep Sub-micrometer CMOS Device and Circuit Performance” IEEE Transactions on Electron Devices, vol.49, (no.5), May 2002, p.826- 831
  48. Shantanu Rastogi, Ritesh Jhaveri, S.Mukherji, M.Ravikanth, and V.Ramgopal Rao, “Status and Trends in Molecular Electronics”, Special issue of IETE Technical Review on Nano Technology, Volume 19, No.5, pp 305-313, October 2002 (Invited)
  49. Abhay Porwal, Mayur Narsude, Soumyo Mukherji, and V.Ramgopal Rao, “Microcantilever Based Biosensors”, Special issue of IETE Technical Review on Nano Technology, Volume 19, No.5, pp 293-303, October 2002 (Invited)
  50. S. Mahapatra, V. Ramgopal Rao, B. Cheng, M. Khare, C. D. Parikh, J. C. S. Woo and J. Vasi, “Performance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor Deposited Si3N4 MNSFETs”, IEEE Transactions on Electron Devices, vol.48, (no.4), April 2001. p.679-84
  51. S. Mahapatra, V.Ramgopal Rao, B.Cheng, J.Vasi and J.C.S.Woo “A Study of Hot-Carrier Induced Interface-Trap Profiles in Lateral Asymmetric Channel MOSFETs Using a Novel Charge Pumping Technique”, Solid State Electronics, Vol. 45, p.1717-1723, 2001
  52. Nihar.R.Mohapatra, A.Dutta, G.Sridhar, M.P.Desai and V.Ramgopal Rao “Sub 100 nm CMOS Circuit Performance with High-K Gate Dielectrics” Microelectronics Reliability, Vol. 41, p.1045-1048, 2001
  53. Aatish Kumar, Souvik Mahapatra, Rakesh Lal, and V. Ramgopal Rao, “Multi-Frequency Transconductance Technique for Interface Characterization of Deep Sub-Micron SOI-MOSFETs”, Microelectronics Reliability, Vol. 41, p. 1049-1051, 2001
  54. Samadhan B.Patil, A.Kumbhar, P.Waghmare, V.Ramgopal Rao, and R.O.Dusane, “Low Temperatue Silicon Nitride deposited by Hot-Wire CVD for Deep Sub-micron CMOS Devices”, Thin Solid Films, Vol. 395, p 270-274, 2001
  55. Aatish Kumar, Rakesh Lal, and V. Ramgopal Rao, “A Simple and Direct Technique for Interface Characterization of SOI MOSFETs and its Application in Hot Carrier Degradation Studies in Sub 100 nm JVD MNSFETs”, Microelectronic Engineering, Vol. 59, p. 429-433, 2001
  56. Kottantharayil Anil, Souvik Mahapatra, V.Ramgopal Rao and I. Eisele, “Comparison of Sub-Bandgap Impact Ionization in Sub-100 nm Conventional and Lateral Asymmetrical Channel nMOSFETs”, Japanese Journal of Applied Physics, Vol. 40 (2001) 2621-2626, Part 1, No. 4B, 30 April 2001
  57. S.Mahapatra, C.D.Parikh, V.Ramgopal Rao, C.R.Viswanathan, and J.Vasi, “A Comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique”, IEEE Transactions on Electron Devices, vol. 47, p. 171-178, January, 2000
  58. S.Mahapatra, C.D.Parikh, V.Ramgopal Rao, C.R.Viswanathan, and J.Vasi, “Device Scaling Effects on Hot-Carrier Induced Interface and Oxide Trap Distributions in MOSFETs”, IEEE Transactions on Electron Devices, vol. 47, p. 789-796, April 2000
  59. B.Cheng, V.Ramgopal Rao and J.C.S.Woo, “Exploration of Velocity Overshoot in a High-Performance Deep sub 100 nm SOI MOSFET with Asymmetric Channel Profile” IEEE Electron Device Letters, vol. 20, p. 538-540, October 1999
  60. B.Cheng, M.Cao, V.Ramgopal Rao, A.Inani, P.V.Voorde, W.Greene, Z.Yu, H.Stork, and J.C.S.Woo, “The impact of high-k gate dielectrics and metal gate electrode on sub 100 nm MOSFETs”, IEEE Transactions on Electron Devices, vol. 46, p. 1537, 1999
  61. A.Inani, V.Ramgopal Rao, B.Cheng, and J.C.S. Woo, “Gate Stack Architecture Analysis and Channel Engineering in Deep Sub-Micron MOSFETs”, Japanese Journal of Applied Physics, Part 1, April 1999, vol.38, (no.4B): p. 2266-71
  62. S.Mahapatra, C.D.Parikh, J.Vasi, V.Ramgopal Rao, and C.R.Viswanathan, “A Direct Charge Pumping Technique for Spatial Profiling of Hot-Carrier Induced Interface and Oxide Traps in MOSFETs”, Solid State Electronics, p. 915, vol. 43, 1999
  63. V. Ramgopal Rao, W.Hansch, S. Mahaptra, D.K. Sharma, J.Vasi, T.Grabolla, and I.Eisele, “Low Temperature-High Pressure Grown Thin Gate Dielectrics for MOS Applications” Microelectronic Engineering, vol. 48, p.223-226, 1999
  64. S. Mahapatra, V. Ramgopal .Rao, C.D.Parikh, J.Vasi, B.Cheng, and J.C.S.Woo, “A Study of 100 nm Channel Length Asymmetric MOSFETs by Using Charge Pumping”, Microelectronics Engineering, vol. 48, p. 193-196, 1999
  65. W.Hansch, V.Ramgopal Rao, C.Fink, F.Kaesen, and I.Eisele, “Electric Field Tailoring in MBE Grown Vertical Sub-100 nm MOSFETs”, Thin Solid Films, vol..321, p. 206-214, 1998
  66. T.Brozek, V. Ramgopal Rao, A.Sridharan, J. Werking, D.Chan, and C.R.Viswanathan, “Charge Injection using Gate-Induced-Drain-Leakage Current for Characterization of Plasma Edge Damage in CMOS Devices” IEEE Transactions on Semiconductor Manufacturing, vol. 11 (2), May 1998
  67. C.R. Viswanathan, and V. Ramgopal Rao “Application of charge pumping technique for sub-micron MOSFET characterization” Microelectronic Engineering, vol.40, (no.3-4):p. 131-46, Nov. 1998
  68. A.Balandin, S.Cai, R.Li, K.L.Wang, V.Ramgopal Rao, and C.R.Viswanathan, “Flicker Noise in GaN/Al0.15Ga0.85N Doped Channel Heterostructure Field Effect Transistors”, IEEE Electron Device Letters, p. 475, Vol. 19, 1998
  69. V. Ramgopal Rao, W. Hansch, H. Baumgartner, I. Eisele, D. K. Sharma and J. Vasi “Charge Trapping Behavior in Deposited and Grown Oxides”, Thin Solid Films, vol. 296, p. 37, 1997
  70. V. Ramgopal Rao, I. Eisele, R. M. Patrikar, D. K. Sharma, J. Vasi, and T. Grabolla “High-Field Stressing of LPCVD Gate Oxides”, IEEE Electron Device Letters, vol.18, p.84, 1997
  71. V. Ramgopal Rao, F. Wittmann, H. Gossner, and I. Eisele, ” Hysteresis Behaviour in 85 nm Channel Length Vertical MOSFETs Grown by MBE“, IEEE Trans. on Electron Devices, vol. 43(6), p. 973, 1996
  72. V. Ramgopal Rao, D. K. Sharma, and J. Vasi, “Neutral Electron Trap Generation under Irradiation in Reoxidised Nitrided oxide Gate Dielectrics”, IEEE Trans. on Electron Devices, vol. 43, p. 1467, 1996
  73. V. Ramgopal Rao and J. Vasi, “Radiation induced interface state generation in reoxidised nitrided oxides”, Journal of Applied Physics, 71(2), 1992 ———————————————————————————————————————————————————————————————————————————-IN INTERNATIONAL CONFERENCE PROCEEDINGS—————————————————————————————————–
  74. Mrunal A. Khaderbad, Kaushik Nayak, M. Yedukondalu, M. Ravikanth, S.Mukherji and V.Ramgopal Rao, “Metallated Porphyrin Self Assembled Monolayers as Cu Diffusion Barriers for the Nano-scale CMOS Technologies”, Accepted, 8th IEEE Conference on Nanotechnology (IEEE NANO 2008), August 18-21, 2008, Arlington, Texas USA
  75. Nitin S. Kale, Sudip Nag, R. Pinto, V. Ramgopal Rao, “Photoplastic NEMS with an Encapsulated Polysilicon Piezoresistor”, Accepted, 8th IEEE Conference on Nanotechnology (IEEE NANO 2008), August 18-21, 2008, Arlington, Texas USA
  76. V. Seena, P. Nageswararao, S.Mukherji, Anil Kumar, V.Ramgopal Rao, “Polymer microcantilever biochemical sensors with integrated polymer composites for electrical detection”,Accepted, European Materials Research Society Symposium, E-MRS spring meeting, Strasbourg, 25-29, May 2008
  77. V.Hariharan, R. Thakker, M. B. Patil, J. Vasi and V. Ramgopal Rao, “Closed Form Current and Conductance Model for Symmetric Double-Gate MOSFETs using Field-dependent Mobility and Body Doping”, Accepted, 2008 NSTI Nanotechnology Conference and Trade Show, June 1-5, 2008, Boston, Massachusetts, U.S.A
  78. G. Naga Siva Kumar, Sushanta K. Mitra, V. Ramgopal Rao, “Simulating Selective particle Seperation in a Dielectrophoretic Microchannel”, Accepted, 2 nd International ASME Conference on Integration & Commercialization of Micro & Nanosystems (MicroNano08), June 3-5, 2008, Clear Water Bay, Kowloon, Hong Kong
  79. V. Hariharan, Juzer Vasi, and V. Ramgopal Rao, “Drain Current Model for Undoped Symmetric Double-Gate FETs using a Velocity Saturation Model with Exponent n=2”, Proceedings of the 2007 International Semiconductor Device Research Symposium (ISDRS), Dec 12-14, 2007,Universit of Maryland,College Park, USA
  80. Nitin S. Kale, Manoj Joshi, S. Mukherji, V. Ramgopal Rao, “Bio-functionalization of Silicon Nitride based Piezoresistive Microcantilevers”, Proceedings of the 10 th International Conference on Advanced Materials (ICAM), organized by the International Union of Materials Research Societies (IUMRS), October 8-13, 2007, Bangalore, India
  81. S.P. Tiwari, D. Maji, Srinivas P., Ramesh R.N., Harshil N. Raval, V. Ramgopal Rao, “Low Voltage Organic Circuits with Polythiophene Semiconductor and High-k Gate Dielectrics”, Proceedings of the 10 th International Conference on Advanced Materials (ICAM), organized by the International Union of Materials Research Societies (IUMRS), October 8-13, 2007, Bangalore, India
  82. K. Nayak, Prasanna Kulkarni, Deepu A., V. Sitaraman, S. Punidha, A. Saha, M. Ravikanth, Sushanta Mitra, S. Mukherji, V. Ramgopal Rao, “Patterned Microfluidic Channels using Self-assembled Hydroxy-phenyl Porphyrin Monolayer”, Proceedings of the 7th IEEE International Conference on Nanotechnology, August 2-5, 2007 Hong Kong
  83. C.R. Manoj, Meenakshi. N, Dhanya V. and V.Ramgopal Rao, “Optimization of Nano-scale Bulk FinFETs”, Proceedings of the 14 th International Workshop on the Physics of Semiconductor Devices, Mumbai, December 16-20, 2007
  84. S. R. Rajwade, P.D. Kulkarni, S. Mukherji, V.Ramgopal Rao, “Polymerization on DNA Templates for Nanoelectronics Applications”, Proceedings of the International Conference on Materials for Advanced Technologies (ICMAT), July 1-6, 2007, Singapore
  85. Manoj Joshi, Gajanan Nagre, Seena V., V. Ramgopal Rao, Soumyo Mukherji, “Functionalization of Hydrogen Silsesquioxane (HSQ) surface for biosensor applications”, Proceedings of the European Materials Research Society (EMRS)Spring Meeting, MAY 28 to JUNE 1, 2007, Congress Center - STRASBOURG (France)
  86. A. V. Govindarajan, M. Joshi, S. Mukherji, V.Ramgopal Rao and K. F. Böhringer, “Engineering The Hydrophobicity Oxide Surfaces By Controlling The Dehydration Temperature Of Silanization”, Proceedings of the European Materials Research Society (EMRS)Spring Meeting, MAY 28 to JUNE 1, 2007, Congress Center - STRASBOURG (France)
  87. S.P. Tiwari, Subodh G. Mhaisalkar, V. Ramgopal Rao, “Ambipolar Organic Field Effect Transistors with semi conducting blends for CMOS-type Organic circuits”, Proceedings of the European Materials Research Society (EMRS)Spring Meeting, MAY 28 to JUNE 1, 2007, Congress Center - STRASBOURG (France)
  88. Srinivas P, S.P. Tiwari, Tommy Cahyadi, S. G. Mhaisalkar and V. Ramgopal Rao, “A Simple and Direct Method for Interface Characterization of OFETs”, Proceedings of the 14th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 11-13 July 2007, Bangalore, India
  89. C.R Manoj, N. Meenekshi, V.Ramgopal Rao, “Optimum Body Doping for Improving the Bulk FinFETs Performance”, Proceedings of the 14th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 11-13 July 2007, Bangalore, India
  90. S. P. Tiwari, D. Maji, Srinivas P., Nitin S. Kale and V. Ramgopal Rao, “Patterned gate OFETs with inorganic High-K gate dielectric materials for all P-type Organic circuits”, Proceedings of the European Materials Research Society (EMRS)Spring Meeting, MAY 28 to JUNE 1, 2007, Congress Center - STRASBOURG (France)
  91. Y. Kobayashi, K. Tsutsui, K. Kakushima, V. Hariharan, V. Ramgopal Rao, P. Ahmet and H. Iwai, “Parasitic Effects Depending on Shape of Spacer Region on FinFETs,” Proceedings of the 211 th Meeting of the Electrochemical Society, Hilton Chicago, Chicago, Illinois, May 6-10, 2007
  92. Bulusu Anand, V. Ramgopal Rao, M. P. Desai, “Circuit Performance Improvement Using PDSOI-DTMOS Devices with a Novel Optimal Sizing Scheme Considering Body Parasitics”, Proceedings of the 2007 International Symposium on VLSI Design, Automation & Test (VLSI-DAT) Hsinchu, Taiwan, April 25-27, 2007
  93. S.P. Tiwari, V. Ramgopal Rao, Huei Shaun Tan, E. B. Namdas, Subodh G Mhaisalkar, “Pentacene Organic Field Effect Transistors on Flexible substrates with polymer dielectrics”, Proceedings of the 14 th International Symposium on VLSI Technology, Systems, and Applications (2007 VLSI-TSA), April 23-25, 2007 Hsinchu, Taiwan
  94. C. Sandhya, N.Mani Bharath, and V Ramgopal Rao, “Back-interface Characterization of SOI MOSFETs using Transient Charge Pumping”, Proceedings of the 37th IEEE Semiconductor Interface Specialists Conference (SISC), December 7-9, 2006, San Diego, USA
  95. Nitin S.Kale, Vamsi Krishna, R. Pinto, P. R.Apte, R.Lal, V. Ramgopal Rao, “Fabrication of Cantilever Structures for Bio-MEMS applications using Hotwire CVD Silicon Nitride”, Proceedings of the 4th International Conference on Hot-Wire CVD (Cat-CVD) Process, Japan, October 4 - 8, 2006
  96. S.P. Tiwari, Srinivas P., Shriram S., Nitin S. Kale, Subodh Mhaisalkar, V. Ramgopal Rao, “Organic FETs with HWCVD Silicon Nitride as Passivating Layer and Gate Dielectric”, Proceedings of the 4th International Conference on Hot-Wire CVD (Cat-CVD) Process, Japan, October 4 - 8, 2006
  97. Partha Sarkar, Abhijit Mallik, Chandan Kumar Sarkar, V. Ramgopal Rao, “The Effects of Varying Tilt Angle of Halo Implant on the Performance of Sub 100nm LAC MOSFETs”, International Conference on Industrial and Information Systems, Srilanka, August 8-11, 2006
  98. M Joshi, N Kale, S Mukherji, R Lal, V Ramgopal Rao, “Affinity Cantilever Sensors for Cardiac Diagnostics”, Indo Chinese Workshop on MEMS and Related Technologies, New Delhi, April 5-7, 2006 (Invited)
  99. K. Narasimhulu and V. Ramgopal Rao, “Analog Device and Circuit Performance Degradation under Substrate Enhanced Hot Carrier Stress Conditions”, 44th Annual International Reliability Physics Symposium (IRPS), March 26-30, 2006, San Jose, California, USA
  100. Manoj C.R, Abhinav Mangal, V.Ramgopal Rao, Hiroshi Iwai,”Parasitic Effects in Multi-gate MOSFETs“, International Workshop on Nano CMOS, Jan 30- Feb 1, 2006, Mishima, Shizuoka prefecture, Japan (Invited)
  101. K.Narasimhulu, V.Ramgopal Rao, “Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies”, Proceedings of the 19 th International Conference on VLSI Design, January 3 - 7, 2006, Hyderabad, India
  102. Partha Sarkar, A.Mallik, C.K.Sarkar, V.Ramgopal Rao, “Performance of Channel Engineered SDODEL MOSFET for Mixed Signal Applications”, Proceedings of the 2005 IEEE International Conference on Electron Devices and Solid-State Circuits, Hong Kong, December 19-21, 2005
  103. M.V.Rammohan Reddy, D.K.Sharma,M.B.Patil, V.Ramgopal Rao, “Multigate FETs for sub 65nm CMOS Technologies- Implications for Circuit Design”, 13 th International Workshop on The Physics of Semiconductor Devices (IWPSD), December 13-17, 2005, New Delhi (Invited)
  104. K.Narasimhulu, V.Ramgopal Rao,”Forward Body-biased Single Halo MOS Devices for Low Voltage Analog Circuits“, Proceedings of the 2005 International Conference on Simulation of Semiconductor Processes and Devices, September 1-3, 2005, Tokyo, Japan
  105. A. Sathyapalan, A. Lohani, Sangita Santra, M. Ravikanth, S.Mukherji, V.Ramgopal Rao, “Meso-pyridyl Porphyrin Self-assembled Monolayers on Gold Substrates for Molecular Electronics Applications”, Proceedings of the 5 th IEEE Conference on Nanotechnology, July 11-15,2005, Nagoya, Japan
  106. M. Joshi, R.Pinto, V.Ramgopal Rao, S.Mukherji, “Silanization and Antibody Immobilization on SU8”, Proceedings of the 3rd International Conference on Materials for Advanced Technologies (ICMAT 2005), 3 - 8 July 2005, Singapore
  107. Neeraj K. Jha, P. Sahajananda Reddy and V.Ramgopal Rao, “A New Drain Voltage Enhanced NBTI Degradation Mechanism”, Proceedings of the 2005 (43 rd Annual) International Reliability Physics Symposium (IRPS), April 17 – 21, 2005, San Jose, California, USA
  108. M.Joshi, S.Singh, B.Swain, S.Patil, R.Dusane, V.Ramgopal Rao, S.Mukherji, “Anhydrous silanization and antibody immobilization on hotwire CVD deposited silicon oxynitride films”, Proceedings of the IEEE INDICON 2004, Dec. 20-22, 2004 Pages:538 - 541
  109. K. Narasimhulu, V. Ramgopal Rao, “Understanding the Impact of Process Variations on Analog Circuit Performance with Halo Channel Doped Deep Sub-Micron CMOS Technologies”, Proceedings of the 35th International Conference on Solid State Devices and Materials (SSDM 2004), Tokyo, Japan, September 15-17, 2004
  110. Pradeep Kumar Chawda, B. Anand, and V.Ramgopal Rao, “Effectiveness of Optimum Body Bias for Leakage Reduction in High K CMOS Circuits”, Proceedings of the 35 th International Conference on Solid State Devices and Materials (SSDM 2004), Tokyo, Japan, September 15-17, 2004
  111. M.Joshi, V.Ramgopl Rao, S.Mukherji, “AFM characterization and selectivity of immobilization of antibodies for Bio-MEMS applications” Proceedings of the International Bio-engineering Conference, September 8-10, 2004, Singapore
  112. Bhawna Tomar, V. Ramgopal Rao, “Sub-threshold Swing Degradation due to Localized Charge Storage in SONOS Memories”, Proceedings of the 11 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, July 5-8, 2004 Hinshcu, Taiwan
  113. Neeraj Jha, V.Ramgopal Rao, “Understanding the NBTI Degradation in Halo- Doped Channel p-MOSFETs” Proceedings of the 11th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, July 5-8, 2004 Hinshcu, Taiwan
  114. K. Narasimhulu,Siva G.Narendra, and V. Ramgopal Rao, “Effect of Process Variations on Device and Circuit Parameters with LAC/DH MOSFETs”, Proceedings of the 17 th IEEE International Conference on VLSI Design, January 7-9, 2004, Mumbai, India
  115. A.Dixit, and V. Ramgopal Rao, “A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep sub-micrometer CMOS Regime”, Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003,NewDelhi,India.
  116. N.R Mohapatra, M.P.Desai, and V. Ramgopal Rao “Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics”, Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003, New Delhi, India
  117. D. Vinay Kumar, N. R.Mohapatra, V. Ramgopal Rao, and M. B. Patil, “Application of the look-up table approach to high-K dielectric MOS transistor circuits,” Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003, New Delhi, India
  118. Najeeb-ud-Din, V.Ramgopal Rao, and J.Vasi, “Small Signal Characteristics of Thin Film Single Halo SOI MOSFETs for Mixed Mode Applications”, Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003, New Delhi, India
  119. Nihar. R. Mohapatra, S. Mahapatra, V. Ramgopal Rao, S. Shukuri and J. Bude, “Effect of Programming Biases on the Reliability of CHE and CHISEL Flash EEPROMs”, Proceedings of the International Reliability Physics Symposium (IRPS) 2003, March 30 - April 3, 2003, Dallas, Texas, USA
  120. Nihar Mohapatra, Deleep Nair, Souvik Mahapatra, V. Ramgopal Rao, Shoji Shukuri, “The Impact of Channel Engineering on the Performance Reliability and Scaling of CHISEL NOR Flash EEPROMs”, 33rd European Solid-State Device Research Conference (ESSDERC) 2003: 16 - 18 September 2003, pp. 541-544, Lisbon, Portugal
  121. K.N.Manjularani, V.Ramgopal Rao, J.Vasi, “Relaibility of Ultrathin JVD Silicon Nitride MNSFETs under High Field Stressing” Proceedings of the 10 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 7-11 July 2003, Singapore
  122. Najeeb-ud-Din, V. Ramgopal Rao, and J. Vasi, “Thin Film Single Halo (SH) SOI nMOSFETs - Hot Carrier Reliability for Mixed Mode Applications” IEEE TENCON 2003, Convergent Technologies for the Asia-Pacific, October 14-17, 2003,Bangalore, India
  123. K.N.Manjularani, V.Ramgopal Rao, J.Vasi, “Characterization of High-Field Stress-Induced Border Traps in JVD Si3N4 Transistors by Drain urrent Transient and 1/f Methods” 34th IEEE Semiconductor Interface Specialists Conference (SISC), December 4-6, 2003, Washington, D.C., USA
  124. Najeeb-ud-Din, Aatish Kumar, Mohan V.Dunga, V.Ramgopal Rao, J.Vasi, “Suppression of Parasitic BJT Action in Single Pocket Thin Film Deep Sub-micron SOI MOSFETs”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)
  125. Nihar. R. Mohapatra, M. P. Desai, V. Ramgopal Rao, “Effect of Technology Scaling on MOS Transistors with High-K Gate Dielectrics”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)
  126. Krishna K. Bhuwalka, Nihar. R. Mohapatra, Siva G.Narendra, V. Ramgopal Rao, “Effective dielectric thickness Scaling for High-K Gate Dielectric MOSFETs”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)
  127. P.C.Waghmare, S.B.Patil, A.Kumbhar, R.O.Dusane, and V.Ramgopal Rao, “Improvement of Gate Dielectric Quality of MNS Capacitors by Hydrogen Etching for Ultra Thin Gate Dielectrics”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)
  128. K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi, “Degradation Study of Ultra-Thin JVD Silicon Nitride MNSFET”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)
  129. Nihar. R. Mohapatra, Souvik Mahapatra and V. Ramgopal Rao, “Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)
  130. A.Dixit, R.O.Dusane, and V.Ramgopal Rao, “Electrically Induced Junction MOSFET for High Performance Sub 50 nm CMOS Technology”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)
  131. Yatin Mutha, K.N.ManjulaRani, R.Lal and V.Ramgopal Rao, “Polarity Dependence of Degradation in Ultra Thin Oxide and JVD Nitride Gate Dielectrics”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)
  132. A.V. Vairagar, S.B. Patil, D.J. Pete, R.O. Dusane,, N. Venkatramani and V.Ramgopal Rao, “Suppression of Boron Penetration by Hot Wire CVD Polysilicon” Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore
  133. N.R Mohapatra, S. Mahapatra and V. Ramgopal Rao, “Bias and Time Dependene of Damage Generation in n-Channel MOS Transistors Operating in the Substrate Enhanced Gate Current Regime” Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore
  134. Yatin M. Mutha, R. Lal and V.Ramgopal Rao, “Physical Mechanisms for Pulsed AC Stress Degradation in Thin Gate Oxide MOSFETs” Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July2002,Singapore.
  135. Neeraj .K. Jha, M. Shojaei, V.Ramgopal Rao, “Performance and Reliability of Single Pocket Deep Submicron MOSFETs for Analog Applications”, Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore
  136. Neeraj K. Jha, V. Ramgopal Rao, and J.C.S.Woo, “Optimization of Single Halo p-MOSFET Implant Parameters for Improved Analog Performance and Reliability”, Proceedings of the 32 nd European Solid-State Device Research Conference (ESSDERC), 24 - 26 September 2002, Florence, Italy
  137. Parag C. Waghmare, Samadhan B. Patil, Alka A. Kumbhar, Laxmi Sahoo, V. Ramgopal Rao, and R.O. Dusane, “Nitrogen dilution effects on structural and electrical properties of hot wire deposited a-SiN:H films for Deep Sub-micron CMOS Technologies”, Proceedings of the International Conference on Cat-CVD (Hot-Wire CVD) Process, Denver, CO, USA, September 10-13, 2002
  138. Samadhan B. Patil, Anand V. Vairagar, Alka A. Kumbhar, Laxmi K. Sahu, V. Ramgopal Rao, N. Venkatramani, R. O. Dusane and B. Schroeder, “Highly Conducting P+- PolySi Deposited by HWCVD and its Applicability As Gate Material for CMOS Devices” Proceedings of the International Conference on Cat-CVD (Hot-Wire CVD) Process, Denver, CO, USA, September 10-13, 2002
  139. D. Vinay Kumar, R. A. Thakker, M. B. Patil, and V. Ramgopal Rao, “Simulation study of non quasi static behaviour of MOS transistors,” Proc. 5th International Conference on Modeling and Simulation of Microsystems, San Juan, Puerto Rico, April 22, 2002
  140. P.Poornima, S.K.Tripathy, V.Ramgopal Rao, and D.K.Sharma, “Resolution Enhancement Techniques for Optical Lithography”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India (Invited)
  141. Najeeb-ud-Din, V.Ramgopal Rao, and J.Vasi, “Characterization and simulation of Lateral Asymmetric Channel Silicon-on-Insulator MOSFETs”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India
  142. K.N.ManjulaRani, V.Ramgopal Rao, and J.Vasi, “High Field Stressing Effects in JVD Nitride Capacitors”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India
  143. A.Dixit, D.K.Pal, J.N.Roy, and V.Ramgopal Rao, “Channel Engineering for Sub-micron CMOS Technologies”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India
  144. D. Vinay Kumar, M. B. Patil, N. R. Mohapatra, V. Ramgopal Rao, B. Anand, and M. P. Desai, “A new look-up table circuit simulator,” Proc. Chandigarh Symp. on Microelectronics, Punjab University, February, 2001 (Invited)
  145. Mohan V. Dunga, Aatish Kumar, and V. Ramgopal Rao, “Analysis of Floating Body Effects in Thin Film SOI MOSFETs using the GIDL Current Technique”, Proceedings of 8 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 9-13 July 2001, Singapore
  146. Nihar. R. Mohapatra, M. P. Desai, Narendra Siva, V. Ramgopal Rao, “The Impact of High-K Gate Dielectrics on Sub 100nm CMOS Circuit Performance”, Proceedings of the 31 st European Solid-State Device Research Conference (ESSDERC), 11 - 13 September 2001, Nuremberg, Germany, September, 2001.
  147. Nihar Mohapatra, Souvik Mahapatra, V.Ramgopal Rao, “”Study of Degradation in Channel Initiated Secondary Electron Injection Regime“, Proceedings of the 31 st European Solid-State Device Research Conference (ESSDERC), 11 - 13 September 2001, Nuremberg, Germany, September, 2001.
  148. Aatish Kumar, Rakesh Lal, and V. Ramgopal Rao, “A Simple and Direct Technique for Interface Characterization of SOI-MOSFETs and its Application in Sub 100nm JVD-MNSFETs”, 12 th Bi-annual conference on Insulating Films on Semiconductors, INFOS, June 20-23, 2001, Italy
  149. Parag C.W, Samadhan Patil, Alka Kumbhar, R.O.Dusane, V.Ramgopal Rao, “Ultra thin Silicon Nitride by Hot Wire CVD for Deep Sub-Micron CMOS Technologies”, Proceedings of the Micro and Nanoengineering (MNE’01) Conference, September16-19, 2001,France
  150. Najeebuddin, Aatish Kumar, Mohan V.Dunga, V.Ramgopal Rao, J.Vasi, “Characterization of Lateral Asymmetric Channel (LAC) Thin Film SOI MOSFETs”, 6 th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Shanghai, China, 22-25 th October, 2001 (Invited)
  151. P.C.Waghmare, S.B.Patil, A.Kumbhar, R.O.Dusane, and V.Ramgopal Rao, “Reliability Issues of Ultra Thin Silicon Nitride by Hot-Wire CVD for Deep Sub-Micron CMOS Technologies”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India
  152. Mayank Gupta, V.Vidya, V.Ramgopal Rao, Kun H. To, Jason C.S. Woo, “Optimization of Sub 100 nm Gamma-Gate Si-MOSFETs for RF Applications” Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India
  153. Nihar. R. Mohapatra, Souvik Mahapatra and V. Ramgopal Rao, “A Comparative Study of Degradation for NMOSFET's in CHE and CHISEL Injection Regime”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India
  154. K.N. Manjularani, V.Ramgopal Rao, J.Vasi, “Border Trap Generation in JVD Nitride Capacitors Under High Field Stressing”, 31 st IEEE Semiconductor Interface Specialists Conference, November 28 - December 1, 2001, Washington D.C, USA
  155. G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele “Performance Optimization of 60 nm Channel Length Vertical MOSFETs Using Channel Engineering”, Proceedings of the 14th International Conference on VLSI Design, January 2001, Bangalore, INDIA
  156. Nihar.R.Mohapatra, A.Dutta, M.P.Desai and V. Ramgopal Rao, “Effect of Fringing Capacitances in Sub 100 nm MOSFET's with High-K Gate Dielectrics” Proceedings of the 14th International Conference on VLSI Design, January 2001, Bangalore, INDIA
  157. N.Mahapatra, M.P.Desai, and V.Ramgopal Rao, “Device and Circuit Performance Issues with High-K Gate Dielectrics”, Proceedings of the National seminar on VLSI: Systems, Design and Technology, IIT Bombay, Dec 2000.
  158. Samadhan B.Patil, A.Kumbhar, P.Waghmare, V.Ramgopal Rao, and R.O.Dusane, “Low Temperatue Silicon Nitride deposited by Cat CVD for Deep Sub-micron CMOS Devices”, Proceedings of the International Conference on Cat-CVD (Hot-Wire CVD) Process, Kanazawa, Japan, November 2000
  159. Nihar.R.Mohapatra, A.Dutta, G.Sridhar, M.P.Desai and V.Ramgopal Rao “Sub 100 nm CMOS Circuit Performance with High-K Gate Dielectrics” Proceedings of the 11th Workshop on Dielectrics in Microelectronics (WoDiM), November 13-15, 2000, Munich, Germany
  160. Aatish Kumar, Souvik Mahapatra, Rakesh Lal, and V. Ramgopal Rao, “Multi-Frequency Transconductance Technique for Interface Characterization of Deep Sub-Micron SOI-MOSFETs”, Proceedings of the 11th Workshop on Dielectrics in Microelectronics (WoDiM), November 2000, Munich, Germany
  161. K.G. Anil, S. Mahapatra, I. Eisele, V.Ramgopal Rao, and J. Vasi “Drain Bias Dependence of Gate Oxide Reliability in Conventional and Asymmetrical Channel MOSFETs in the Low Voltage Regime”, Proceedings of the 30 th European Solid-State Device Research Conference (ESSDERC), Ireland, September, 2000
  162. K.G. Anil, S. Mahapatra, V. Ramgopal Rao and I. Eisele, “Comparison of Sub-Bandgap Impact Ionization in Deep-Sub-Micron Conventional and Lateral Asymmetrical Channel nMOSFETs”, Proceedings of the International Conference on Solid state Devices and Materials (SSDM) Sendai, Japan, August 28-31, 2000
  163. S.Mahapatra, V.Ramgopal Rao, J.Vasi, B.Cheng, and J.C.S. Woo, “Reliability Studies on Sub 100 nm SOI-MNSFETs”, Proceedings of the International Integrated Reliability Workshop, October 23-26, 2000, California, USA.
  164. V. Ramgopal Rao, S. Mahapatra, J.Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele, “Hot-Carrier Performance of 60 nm Channel Length Delta-Doped Vertical MOSFETs with High-pressure Grown Oxide as a Gate Dielectric”, Proceedings of the 30th IEEE Semiconductor Interface Specialists Conference, 2000, San Diego, California, USA
  165. Samadhan B. Patil , Sangeeta Vaidya, Alka Kumbhar, R. O. Dusane, A. N. Chandorkar and V. Ramgopal Rao, “Low Temperature Hot-Wire CVD Nitrides for Deep Sub-Micron CMOS Technologies” Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec.1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.879-82
  166. M. Hemkar, J.Vasi, V. Ramgopal Rao, B. Cheng, J.C.S. Woo, “Optimization and realization of sub 100 nm channel length lateral asymmetric channel p-MOSFETS” Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec. 1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.584-7.
  167. Sharad Sharma, and V. Ramgopal Rao, “Performance Trade-offs by the Use of High-K Gate Dielectrics in Sub 100 nm CMOS Technologies”, Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec. 1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.896-9
  168. Sushant S. Suryagandh, and V. Ramgopal Rao, “Dynamic Threshold Voltage MOSFETs for Future Low Power Sub 1V CMOS Applications”, Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec. 1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.655-8
  169. S. Mahapatra, K. N. Manjularani, V. Ramgopal Rao, J. Vasi, ” ULSI MOS Transistors with Jet Vapour Deposited (JVD) Silicon Nitride for the Gate Insulator“, Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec. 1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.803-10
  170. C.R.Viswanathan, V.Ramgopal Rao and T.Brozek, “Localized Charge Injection-A Tool to Investigate Plasma Damage in CMOS Devices” (invited) Proceedings of the 9 th International Conference on Physics of Semiconductor Devices, December, 1997, New Delhi, India
  171. S. Mahapatra, V. Ramgopal Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S.Woo, “Hot-Carrier Induced interface Trap Distributions in Conventional and Asymmetric Channel MOSFETs as Determined by a novel Charge Pumping Technique” Presented at the 30 th Semiconductor Interface Specialists Conference (SISC), South Carolina, USA, December 1999
  172. S. Mahapatra, V. Ramgopal .Rao, C.D.Parikh, J.Vasi, B.Cheng, and J.C.S.Woo, “A Study of 100 nm Channel Length Asymmetric MOSFETs by Using Charge Pumping”, Proceedings of the Insulating Films on Semiconductors (INFOS), June 1999, Kloster Banz,Germany.
  173. S.Mahapatra, V.Ramgopal Rao, K.N. Manjularani, C.D. Parikh, J. Vasi, B. Cheng, M. Khare, and J.C.S. Woo, “100 nm Channel Length MNSFETs using a Jet Vapor Deposited Ultra-thin Silicon Nitride Gate Dielectric”, Technical Digest, 1999 Symposium on VLSI Technology, June 14-19, Kyoto, Japan
  174. B.Cheng, A.Inani, V.Ramgopal Rao, and J.C.S.Woo, “Channel Engineering for High Speed Sub-1.0 V Power Supply Deep Sub-Micron CMOS” Technical Digest, 1999 Symposium on VLSI Technology, June 14-19, Kyoto, Japan
  175. S. Mahapatra, V. Ramgopal Rao, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo , “Hot-Carrier Induced Interface Degradation in Jet Vapor Deposited SiN MNSFETs as Studied by a Novel Charge Pumping Technique” p. 592-595, 29 th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium 13 - 15September,1999.
  176. A. Inani, V. Ramgopal Rao, B. Cheng, P. Zeitzoff, and J. C. S. Woo, “Capacitance Degradation due to Fringing Fields in Deep Sub-Micron MOSFETs with High-K Gate Dielectrics” p.160-163, 29 th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium 13 - 15 September, 1999
  177. V. Ramgopal Rao, W.Hansch, S.Mahaptra, D.K.Sharma, J.Vasi, T.Grabolla, and I.Eisele, “Low Temperature-High Pressure Grown Thin Gate Dielectrics for MOS Applications”, Proceedings of the Insulating Films on Semiconductors (INFOS), June 1999, Kloster Banz,Germany
  178. V. Ramgopal Rao, I. Eisele, and T. Grabolla, “Alternative Gate Insulators for Future Deep Submicron Channel Length MOSFETs”, Proc. of VIII International Conference on Physics of Semiconductor Devices, December, 1995, New Delhi, India
  179. A. Mallik, V. Ramgopal Rao, A.N. Chandorkar, and J. Vasi, “Trap generation upon irradiation in reoxidised nitrided oxide gate dielectrics”, Proc. of VII International conference on Physics of Semiconductor Devices, December, 1993 New Delhi, India
  180. V. Ramgopal Rao, G. Wijeratne, D. Chu, T. Brozek, and C.R. Viswanathan, “Plasma Process Induced Abnormal 1/f Noise Behavior in Deep Sub-Micron MOSFETs”, 3 rd International Symposium on Plasma Process-Induced Damage (P2ID), Hawaii, USA, June,1998
  181. W.Hansch, A.Nakajima, K.Shibahara, V. Ramgopal Rao and I.Eisele, “Observation of Periodic Current Oscillations in Vertical sub-100nm MOS-PDBFETs with Wide Channels”, 1998 IEEE Silicon Nanoelectronics workshop, (Satellite Workshop, VLSI T.echnology Symposium) Honolulu, Hawaii, USA, June, 1998
  182. C.R. Viswanathan and V. Ramgopal Rao, “Application of charge pumping technique for sub-micron MOSFET characterization” Presented at the Electrical and Physical Characterization of Materials and Devices for Silicon Microelectronics. MIGAS, Autrans, France, 29 June -5 July 1998
  183. A.Inani, B.Cheng, V. Ramgopal Rao, and J.C.S.Woo, “Gate Stack Architecture Analysis in sub 100 nm Channel Length MOSFETs” , 5 th National SRC Conference TECHCON, 1998, Las Vegas, USA
  184. B.Cheng, V. Ramgopal Rao, B.Ikegami, and J.C.S.Woo, “Realization of sub 100 nm asymmetric Channel MOSFETs with Excellent Short-Channel Performance and Reliability” Technical Digest, 28 th European Solid-State Device Research Conference (ESSDERC), Bordeaux, France, 1998
  185. R.Sachdev, G.Wijeratne, V. Ramgopal Rao, and C.R.Viswanathan, “A study of the effect of Plasma Damage on Sub-micron MOSFET’s Flicker Noise Properties”, Technical Digest, 28th European Solid-State Device Research Conference (ESSDERC), Bordeaux, France,1998.
  186. A.Inani, V.Ramgopal Rao, B.Cheng, M.Cao, P.V.Voorde, W.Greene, and J.C.S. Woo, “Performance Considerations in Using High-k Dielectrics for Deep Sub-Micron MOSFETs”, Proceedings of the Solid state Devices and Materials (SSDM) Research Conference, Hiroshima, Japan, 7-10 Sept., 1998
  187. B. Cheng, V. Ramgopal Rao, and J. C. S. Woo, “Sub 0.18 um SOI MOSFETs Using Lateral Asymmetric Channel Profile and Ge Pre-amorphization Salicide Technology”, Proceedings of the IEEE SOI Conference, October 5-8, Stuart, Florida, USA, 1998
  188. W. Hansch, V.Ramgopal Rao, and I.Eisele, “The Planar-Doped-Barrier FET:MOSFET Overcomes Conventional Limitations”, Technical Digest, p. 624, 27 th European Solid-State Device Research Conference (ESSDERC), Stuttgart, Germany, September, 1997
  189. W. Hansch, F. Kaesen, V.Ramgopal Rao, and I. Eisele, “Electric field-tailoring in MBE-grown MOSFETs”, Technical Digest, p. 117, 7th International Symposium on Silicon Molecular Beam Epitaxy, Banff, Canada, July 1997
  190. V. Ramgopal Rao, W. Hansch, and I. Eisele, “Simulation, Fabrication and Characterization of High Performance Planar-Doped-Barrier Sub 100 nm Channel MOSFETs” Technical Digest, IEEE International Electron Devices Meeting (IEDM), p. 811-814, Washington DC, USA, December, 1997
  191. Anand Sridharan, V.Ramgopal Rao, Tomasz Brozek, J. Werking, and C.R.Viswanathan, “Charge Injection using Gate-Induced-Drain-Leakage Current for Characterization of Plasma Edge Damage in CMOS Devices”, Technical Digest, p. 560, 27 th European Solid-State Device Research Conference (ESSDERC), Stuttgart, Germany, September, 1997
  192. V.Ramgopal Rao, W.Hansch, H.Baumgartner, I.Eisele, D.K.Sharma, J.Vasi, and T.Grabolla, “Charge Trapping Behavior in Deposited and Grown Thin MOS Gate Dielectrics”, Proceedings of the European Materials Research Society (EMRS) Symposium, 1996 Spring Meeting, Strasbourg, France
==NATIONAL CONFERENCE PROCEEDINGS==
  1. Manoj Joshi, Nitin Kale, Sheetal Patil, Harshal Rokade, Soumyo Mukherji, R.Pinto, .P.R.Apte, Rakesh Lal and V.Ramgopal Rao, “Affinity Cantilever sensors for Myocardial Infarction”,International Microelectronics and Packaging Society (IMAPS) India National Conference, Dec 20-21, 2005, Mumbai
  2. M. V. Rammohan Reddy, D. Vinay Kumar, D. K. Sharma, M. B. Patil and V. Ramgopal Rao, “FinFET based Low Power Gilbert Cell Mixer”, International Microelectronics and Packaging Society (IMAPS) India National Conference, Dec 20-21, 2005, Mumbai
  3. Seena V., Mahendra K. Jain, V. Ramgopal Rao,S.Praveenkumar, Anita Topkar, “ONO based Triple dielectric passive dosimeters”, DAE-BARC National Symposium on Compact Nuclear instruments and Radiation Detectors, March 2-4, 2005, Jodhpur, India
  4. V.Ramgopal Rao, K.Narasimhulu, “CMOS Device Design and Optimization for System-on-Chip Applications”, Emerging Trends in Electronics (Electro -2005), February, 03-05, 2005, Banaras Hindu University, Varanasi (Invited)
  5. V.Ramgopal Rao, K.Narasimhulu,”Novel Device Architectures and Processes for the 65 nm CMOS Technology Node and Beyond“, Indian National Academy of Engineering (INAE) Conference on Nanotechnology (ICON-2003), Dec. 22-23, 2003, Chandigarh, India (Invited)
==(SELECTED) TECHNICAL REPORTS:==
  1. V.Ramgopal Rao, “MOS Noise/Device Characterization for Mixed Signal Applications” Department of Science and Technology, Govt. of India, 2006
  2. R.Lal, V.Ramgopal Rao, S.Mukherji, et al., “Biosensors for Cardiac Applications”, National Programme on Smart Materials (NPSM), ADA, India, 2006
  3. Vijay Mishra, Pourus Mehta, S. K. Kataria and V. Ramgopal Rao, “Development of Silicon Drift Detectors with Integrated Front End Electronics”, Design Basis Report, BARC, Mumbai, 2004
  4. V.Ramgopal Rao, “Channel engineering for Sub 100 nm MOSFETs”, Department of Science and Technology, Govt. of India, 2003
  5. C.R.Viswanathan and V. Ramgopal Rao, “Plasma Damage Studies Using SPIDER Structures”, Microelectronic Innovation and Computer Research Opportunities (MICRO), University of California, 1998
  6. V. Ramgopal Rao “Radiation Induced Interface State Generation in Nitrided and Reoxidized Nitrided Gate Oxides” Department of Electronics, MHRD, Govt. of India 1992
===PATENTS:===
  1. Manoj Joshi, Nitin Kale, S.Mukherji, R.O.Dusane, V. Ramgopal Rao, Rakesh Lal, “A novel dry method of surface modification of SU8 for immobilisation of biomolecules using hotwire induced pyrolytic process”, Indian Patent No.213504, March 25, 2008
  1. H. Gossner, F. Wittmann, I. Eisele, and V.Ramgopal Rao, “SRAM Memory Cell”, United States Patent No. 6,067247, May 23, 2000
==== PAPER CITATIONS==== Prof. Rao's papers in the area of Electron Devices (published during the last 10 years) have received over 500 citations till date (as indexed in the Google scholar/Scopus). A few well cited papers are listed below: 1. The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFET's, IEEE TRANSACTIONS ON ELECTRON DEVICES 46 (7): 1537-1544 JUL 1999 Times Cited: 145 2. Flicker noise in GaN/Al0.15Ga0.85N doped channel heterostructure field effect transistors, IEEE ELECTRON DEVICE LETTERS 19 (12): 475-477 DEC 1998 Times Cited: 33 3. The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 5, MAY 2002 Times Cited: 28 4. The Planar-Doped-Barrier-FET: MOSFET Overcomes Conventional Limitations, Proceedings of the 27th European Solid-State Device Research Conference (ESSDERC), 1997, page(s): 624- 627 Times Cited: 25 5. Exploration of velocity overshoot in a high-performance deep sub 0.1um SOI MOSFET with asymmetric channel profile, IEEE ELECTRON DEVICE LETTERS 20 (10): 538-540, OCT 1999 Times Cited: 21 6. Channel Engineering for High Speed Sub-1.0 V Power Supply Deep Sub-Micron CMOS, Technical Digest, 1999 Symposium on VLSI Technology, June 14-19, Kyoto, Japan Times cited: 21 7. A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFET's using a novel charge pumping technique, IEEE TRANSACTIONS ON ELECTRON DEVICES 47 (1): 171-177 JAN 2000 Times Cited: 20 8. Sub 0.18 um SOI MOSFETs Using Lateral Asymmetric Channel Profile and Ge Pre-amorphization Salicide Technology, Proceedings of the IEEE SOI Conference, October 5-8, Stuart, Florida, USA, 1998 Times Cited: 16 9. Impact of Lateral Asymmetric Channel Doping on Deep Submicrometer Mixed-Signal Device and Circuit Performance, IEEE TRANSACTIONS ON ELECTRON DEVICES, 50 (12), pp. 2481-2489, 2003 Times Cited: 15 10. Realization of sub 100 nm asymmetric Channel MOSFETs with Excellent Short-Channel Performance and Reliability, 28th European Solid-State Device Research Conference (ESSDERC),1998 Times Cited: 12 11. Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, 47 (4), pp. 789-796, 2000 Times Cited: 12 12. Electric Field Tailoring in MBE Grown Vertical Sub-100 nm MOSFETs, THIN SOLID FILMS, vol..321, p. 206-214, 1998 Times Cited: 12 13. 100 nm channel length MNSFET’s using a Jet Vapor Deposited ultra-thin Silicon Nitride Gate Dielectric, 1999 VLSI Technology Symposium, Kyoto, Japan, Digest of Technical Papers Times Cited: 12 14. Gate Stack Architecture Analysis and Channel Engineering in Deep Sub-Micron MOSFETs, Japanese Journal of Applied Physics, Part 1, April 1999, vol.38, (no.4B): p. 2266-71 Times Cited: 12 15. Optimization and realization of sub-100-nm channel length singlehalo p-MOSFETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, June 2002, Volume: 49, Issue: 6, page(s): 1077-1079 Times Cited: 9 16. A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs, SOLID- STATE ELECTONICS, Volume 43, Issue 5, May 1999, Pages 915-922 Times Cited: 8 17. CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters, IEEE TRANSACTIONS ON ELECTRON DEVICES, Oct. 2003, Volume: 50, Issue: 10, page(s): 2104- 2111 Times Cited: 8 18. Analysis of floating body effects in thin film conventional and single pocket SOI MOSFETs using the GIDL current technique, IEEE ELECTRON DEVICE LETTERS, 23 (4), 2002, pp. 209-211 Times Cited: 8 19. Performance and hot-carrier reliability of 100 nm channel length jet vapor deposited Si3N4 MNSFETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, April 2001, Volume: 48, Issue: 4, page(s): 679-684 Times Cited: 8 20. The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance, IEEE TRANSACTIONS ON ELECTRON DEVICES, Volume 51, Issue 9, Sept. 2004 Page(s):1416 - 1423 Times Cited: 7 21. Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs, 41st Annual IEEE International Reliability Physics Symposium (IRPS) Proceedings, 2003. page(s): 518- 522 Times Cited: 7 22. Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors, IEEE TRANSACTIONS ON ELECTRON DEVICES, 50 (4), pp. 959-966 2003 Times Cited: 7 23. High-field stressing of LPCVD gate oxides, IEEE Electron Device Letters, Volume 18, Issue 3, March 1997 Page(s):84 - 86 Times Cited: 6 24. The Impact of High-K Gate Dielectrics on Sub 100 nm CMOS Circuit Performance, Proceeding of the 31 st European Solid-State Device Research Conference, 2001, page(s): 239- 242 Times Cited: 5 25. Rare Earth Oxides in Microelectronics; RARE EARTH OXIDE THIN FILMS: GROWTH, CHARACTERIZATION , AND APPLICATIONS - TOPICS IN APPLIED PHYSICS 106: 345-365 2007 (Springer-Verlag Series on “Topics in Applied Physics”, Edited by M. Fanciulli and G. Scarel, Ed. 2007) Times Cited: 5 26. Power-Area Evaluation of Various Double-Gate RF Mixer Topologies, IEEE Electron Device Letters, Volume: 26, Issue: 9, June 2005, pp.664 – 666 Times Cited: 5 27. NBTI Degradation and its Impact for Analog Circuit Reliability, IEEE Transactions on Electron Devices,pp. 2609-2615, December 2005 Times Cited: 5 28. A new oxide trap-assisted NBTI degradation model, IEEE Electron Device Letters, Volume 26, Issue 9, Sept. 2005 Page(s):687 - 689 Times Cited: 5
====POSITIONS AVAILABLE====
  • If you have topped your university/college, or qualified in GATE with a respectable score or NET exam, please send your CV to rrao@ee.iitb.ac.in. There are always positions available for good students.
  • If you are aspiring to be a summer intern at IIT Bombay, please visit the web page for IIT Bombay Research Fellowship scheme.
====CONTACT INFORMATION==== Prof. V.Ramgopal Rao
Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email : rrao@ee.iitb.ac.in
Phone (Office) : (++91-22) - 2576 7456
Microelectronics office: ++91-22-25764482 Office room no: AA204
(EE Annnex, second floor) Fax: (++91-22)- 25723707
Microelectronics Group Homepage Nanoelectronics Centre Homepage Centre or Research in Nanotechnology & Science ====OTHER INFORMATION==== For personal details of Prof V.Ramgopal Rao, please click (**here**).
faculty/rrao_complete.txt · Last modified: 2021/09/06 08:38 (external edit)

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