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V. Ramgopal Rao

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RESEARCH INTERESTS

  • Technology Aware Design Challenges with Emerging Technologies (Multigate MOSFETs, Polymer Transistors, Molecular Electronics etc.)
  • CMOS Reliability
  • Bio-MEMS

BRIEF PROFILE


COURSES OFFERED

ACADEMIC BACKGROUND

  • M.Tech, IIT Bombay, 1991
  • Dr.Ingenieur (magna-cum-laude), Faculty of Electrical Engineering, Universitaet der Bundeswehr Munich, Germany, 1997. (Doctoral thesis:Planar-Doped-Barrier Sub 100 nm Channel Length MOSFETs)
  • EE Department, University of California, Los Angeles: 1997-1998 (Post-doctoral fellow)

WORK EXPERIENCE

  • Professor, EE Department, IIT Bombay, Powai, Mumbai (current)
  • Visiting Professor, Nanyang Technological University, Singapore (since 2005)
  • Head, ("Centre for Research in Nanotechnology & Science"), IIT Bombay (Jan 2006-Jan 2007)
  • EE Department, University of California, Los Angeles: 1997-1998 (Post-doctoral fellow)
  • Prof. Rao has held short term visiting positions (May-July) at the University of California,Los Angeles (2001), Universitaet der Bundeswehr, Munich (2003), Tokyo Institute of Technology, Tokyo (2005), & Monash University, Melbourne (2007).

AWARDS & HONOURS

  • 2005 “Dr. Shanti Swarup Bhatnagar Prize in Engineering Sciences” presented by the Hon'ble Prime Minister, Govt.of India(S.S.Bhatnagar Prize) (the highest scientific award for researchers in India)
  • 2008 'The Materials Research Society of India (MRSI)-ICSC Superconductivity & Materials Science Prize' (presented at the 19th Annual General body meeting of the MRSI by Dr. R.A.Mashelkar, President, MRSI)
  • 'Swarnajayanti Fellowship' Award (2003-04), Department of Science and Technology, Govt. of India (Swarnajayanti Fellowship) (this prestigious fellowship is instituted by Govt. of India in 1997 to mark 50 years of India's independance)
  • Editor, IEEE Transactions on Electron Devices (since 2004)

(IEEE T-ED Editorial Board)

  • IETE M.N.Saha Memorial Award for the best application oriented paper in 2004 in a IETE journal & the Best paper award, 2005 IMAPS India National conference
  • Over 200 Research Publications in refereed International Journals and Conference Proceedings and two patents (US patent No. 6,067247 on SRAM Cell) & Over 100 keynote & invited talks at various international conferences, workshops, academic institutions and industries all over the world in the area of Nanoelectronics
  • Prof. Rao interacts closely with semiconductor industries such as Intel, IBM, Infineon, International Rectifier Corporation,IMEC etc., and has many ongoing industry sponsored projects in the area of Silicon CMOS devices. Prof. Rao’s work on fringing field effects in high-k gate dielctric MOSFETS & circuits is widely cited by the industry, while his work on Lateral Asymmetric Channel (LAC) devices has been successfully applied in reducing the sub-threshold leakage in mobile devices by the semiconductor industries. For an industrial applicaton of his work, please click (here).

NATIONAL LEVEL ADVISORY COMMITTEES

  • Member, Nano Applications and Technology Advisory Group (NATAG),NANO MISSION, Department of Science & Technology (DST),Govt. of India
  • Member, “Working Group on Nanotechnology”, Department of Information Technology (DIT), Ministry of Communication & Information Technology, Government of India
  • Member, Programme Advisory Committee (PAC), Electrical, Electronics & Computer Engineering, Department of Science & Technology (DST), Govt. of India (since 2007)
  • Member, Programme Advisory & Review Committee (PARC-4), National Programme on Micro and Smart Systems (NPMASS), Govt. of India
  • Member, Academic and R&D Initiatives in the area of Info-Nano-Biotechnology for the 11 th Five Year plan, Govt of India
  • Member of Academic Planning, Advisory & Evaluation Boards of various Universities and Educational Institutions in India
  • Member/Chairman of various research project monitoring committees including the (i) Electronic Design Centre project, SAMEER, Chennai (ii) Nano-Metrology facility at the National Physical Laboratories, Delhi (iii) Nano-device Characterization project at VNIT, Nagpur (iv)Nano-scale MOSFET project at Punjab University etc.

PROFESSIONAL SOCIETY ACTIVITIES/EDITORIAL BOARD MEMBER

  • Editor, IEEE Transactions on Electron Devices (since 2004)

(IEEE T-ED Editorial Board)

  • Member of the technical subcommittee “Characterization, Reliability, and Yield”, (2008 IEEE International Electron Devices Meeting (IEDM)), San Francisco, USA, December 2008.
  • Honorary Editor, IETE Journal of Research in the area of “Electronics Devices & Components (since March 2007)
  • Member, Editorial Board, The Open Applied Physics Journal (OAP) (a peer reviewed international Open Access journal) & “Recent Patents in Electrical Engineering”, (Bentham Science Publishers)
  • Vice-Chair, IEEE Asia-Pacific Regions/Chapters Subcommittee (w.e.f.Jan 2007)
  • Editor, VSI Vision, VLSI Society of India (2005-2006)
  • Distinguished Lecturer (DL), IEEE Electron Devices Society (EDS) (IEEE-EDS Distinguished Lecturer Program)
  • Panel member, IEEE Electron Devices Society (EDS) Industry Short Course program (IEEE-EDS Industry Short Course Program)
  • Chairman, IEEE AP/ED Bombay Chapter (2003-2004)
  • Member, Executive Committee, IEEE Bombay Section (2005-2006)
  • Member, Executive Committee, IETE Bombay Section (2002-2003)
  • Member, IEEE Electron Device Society (EDS) Membership Committee (2006-2007)
  • Chairman, Organizing Committee, 17 th International Conference on VLSI Design, Mumbai, 2004
  • Chairman, Organizing Committee, 2005 IMAPS India National Conference on “Microelectronics & VLSI”
  • Chairman, Organizing Committee, 14 th International Workshop on Physics of Semiconductor Devices (IWPSD), Dec 16-20, 2007, Mumbai (IWPSD 2007)
  • Co-chair, Organizing Committee, International Conference on Nanotechnology & Health Care Applications (NateHCA - 07), Oct 11-13, 2007, Mumbai
  • Member, Emerging Applications and Technologies (EA&T) sub-committee, Asian Solid-State Circuits Conference (Asian Solid-State Circuits Conference)
  • Publicity Co-chair, Nano-Net 2006: International Conference on Nano-Networks, Lausanne, Switzerland, September 14-16, 2006
  • Member, Technical Program Committee, (Chairman, Technology Sub-committee), 20 th International Conference on VLSI Design, January 6 – 10, 2007, Bangalore
  • Member, Technical Program Committee, 2007 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'06), Portland, USA, August 27-29, 2007
  • Member, Technical Program Committee, IEEE VLSI Design & Test Symposium (VDAT) (2007- )
  • Organizing/Advisory committee member for various national/international conferences/workshops held in India
  • Reviewer for various International Journals/IEEE Transactions & Conferences.

SPONSORED/CONSULTANCY PROJECTS

Principal Investigator/Co-Investigator for the following funded sponsored / consultancy projects:
  • (Nanoelectronics Centre project) (Ministry of Communications and Information Technology, Govt. of India (ongoing) (2006-2010) - As part of this US $ 25 Million project between IIT Bombay & IISc Bangalore, supported by MCIT, two Centres of Excellence in Nanoelectronics are being established at these two institutions. These centres will have state-of-the art facilities for nano-fabrication. A close industry interaction is also envisaged as part of these centre activites involving substantial funding from leading semiconductor industries. For example, at IIT Bombay, Applied Materials has created a “Nano-manufacturing laboratory” with state of the art equipment for CMOS fabricaton. The equipment involves cluster tools for high-k, PVD & etching (for 8-inch diameter wafers) with the total cost of donation amounting to US $ 7.5 Milion. IIT Bombay has also generously funded this project as part of its internal thrust area activities. Overall, at IIT Bombay, a 100 crore facility with active involvement of Government, industry & IIT is coming up. Many of the facilities are either commissioned already or going to be comissioned in the first quarter of 2008.
  • Technology aware Design Challenges in Nano-scale CMOS Technologies (IBM Corporation) (ongoing) (2007-2008) - As part of this effort (sponsored as a IBM Faculty Award ), technology aware design challenges specific to the Finfets are currently being investigated.
  • MEMS Switches for Power Electronics Applications (Larsen & Toubro (L&T) Limited) (ongoing) (2008-2009) - As part of this project various MEMS switches are being developed for power electronics applications
  • Multigate MOSFETs (IMEC, Belgium) (2005-2007) - As part of this interaction with IMEC Belgium, Multi-gate MOSFETs are being optimized from both the device and circuit performance point of view. Novel characterization techniques are also being developed for interface characterization in MuGFETs. The Taurus TCAD tools are optimized for the IMEC process flow based on the extensive device characterization data. These optimized TCAD tools are being used for understanding the device-circuit level interactions using look-up-table based ciruit simulation approaches. A comprehensive MuGFET device-circuit simulation framework has been developed as part of this activity.
  • Novel Circuit Design Approaches with Multi-gate MOSFETs (Intel, CRL, Portland Group), Ongoing (2006-2008): Through this collaboration with the CRL group Intel, the circuit design challenges and the use of multi-gates in circuit design are being ssstematically investigated for logic as well as mixed-signal applications.
  • Optimization of Power Transistors (International Rectifier Corporation & Vishay Siliconix–USA) (2006-2007): As part of this project, IRC’s power transistor designs are being optimized for improved performance.
  • I/O Circuit applications for Novel devices (Infineon, Munich, Germany) (2007-2009) (ongoing): Efforts are made to find circuit solutions which reduce the special requirements for the IO device giving a relief to the process complexity. On the other hand, it is seen that while the technology shrink continues the system requirements to the IO circuit remains constant or even becomes more demanding e.g. by the request of multi GHz interfaces. This means that the gap between the IO voltage and the capability of pn-junctions and dielectrics to handle the higher voltage increases. Novel IO devices are proposed to overcome this problem which are compliant with the processing of the thin gate oxide devices and do not cause large additional process costs.
  • Radiation Sensors/Silicon Drift Detectors (BARC) (2005-2006) - as part of this project, novel detectors are being fabricated on silicon for low noise and high resolution X-ray spectroscopy and other applications.
  • Nitride Based Passive Dosimeters (MHRD, Govt. of India)(2005-2006) - as part of this project a nitride based dosimeter technology will be developed that does not require external power supply during the sensing operation.
  • Sub 65 nm node CMOS - Novel Devices (2005-2009)(Department of Science and Technology, Govt. of India [UNDER THE SWARNAJAYANTI FELLOWSHIP SCHEME](ongoing) - we are looking at realizing novel structures experimentally which would overcome the scaling problems beyond the 65 nm technology node. Various device concepts are currently being looked into using advanced 3-D simulations, before venturing into their experimental realization.
  • CMOS Noise/Device Characterization for Mixed Signal Applications (Department of Science and Technology, Govt. of India (2004-2006) - as part of this sponsored project, extensive experimental characterization of sub 100 nm MOSFETs has been carried out for their noise and other analog/digital device figures of merit.
  • Mixed Signal CMOS: Intel (2003-2005) - through this research collaboration with Intel (CRL-Portland), scaled CMOS technology optimizations have been looked at and a methodology developed for mixed-signal circuits.
  • Biosensors for Cardiac Applications: National Programme on Smart Materials (NPSM), ADA, India (2004-2006) - a full system development containing bio-sensors for myocardial infarction has been initiated as part of this interdisciplinary project, involving faculty and students from EE, Material Science, Bio, Chemistry and Mechanical Engg. departments. The work is currently continuing as part of the Nanoelectronics centre activities with the goal to develop a lab-on-chip for cardiac diagnostics.
  • “Nanotechnology” (Celebration Motion Pictures)(2005-2006)- as a consultant, Prof. Rao advised a company for creation of video content on Naotechnology for children. 13 episodes (of 30 minutes each) addressing different aspects of Nanotechnology were created and are being telecast currently on Doordarshan India (Sunday mornings). The idea for doing this was to make Nanotechnology and the associated areas interesting for children by using lively characters and animation.
  • Molecular Electronics: Cross Disciplinary Research Group (CDRG), IITB (2004-2006) - as part of this interdisciplinary project, various molecules have been chemically synthesized and electrically characterized for various electrical applications. The work is continuing as part of the Nanoelectronics centre activities.
  • Plasma Damage Characterization: Department of Science and Technology, Govt. of India (2002-2004) - as part of this project, plasma implantation induced damage on sub 3 nm gate oxides is investigated
  • Understanding and Modeling of Fringing fields in High-K Gate Dielectric MOSFETs: Intel (2000-2002) - an analytical model has been developed for circuit simulations, by taking into account the fringing fields in high-k gate dielectric MOSFETs. Extensive device optimizations have been carried out to optimize a device employing high-k gate dielectrics.
  • Oxide scaling effects on design issues: Intel (2000-2002) - using an in-house look-up-table simulator, extensive work has been done at optimizing the gate dielectrics for circuit applications.
  • Channel Engineering for Sub 100 nm MOSFETs:Department of Science and Technology, Govt. of India (2000-2002) - process window for Single Halo MOSFETs has been identified for optimum mixed-signal performance using extensive device/circuit simulations

Ph.D. STUDENTS

(as Guide/Co-guide):

Graduated:

  • C.R.Manoj (Guide: V.Ramgopal Rao/M.B.Patil)- Optimization and Scaling of FinFet Structures (Graduating in 2008)
  • Venkanarayan Hariharan (Guides: V.Ramgopal Rao/J.Vasi)- Simulation & Modeling of Multi-gate FETs (Graduating in 2008)
  • Shree prakash Tiwari (Guide: V.Ramgopal Rao) - Novel Device Structures for Polymer Electronics (Graduating in 2008)
  • Nitin Kale (Guide:V.Ramgopal Rao)- Making Hotwire CVD a Viable Technology Alternative for Bio-MEMS applications: System Design, Fabrication & Characterization (Graduated in 2008 - joined TSMC, Taiwan)
  • Manoj Joshi (Guides: S.Mukherji/V.Ramgopal Rao)-Micro-fabricated Biosensors for Cardiac Diagnostics (Graduated in 2007 - joined TSMC, Taiwan)
  • K.Narasimhulu (Guide: V.Ramgopal Rao)- CMOS Device Design & Optimization for Mixed Signal Applications (Graduated in 2006- joined IBM Hopewell Junction, NY, USA)
  • Neeraj K. Jha (Guides: V.Ramgopal Rao/M.B.Patil)-Reliability Studies on Deep Sub-micrometer MOSFETs under Analog Operating Conditions (Graduated in 2005-joined TSMC, Taiwan)
  • D.Vinay Kumar (Guides: M.B.Patil/V.Ramgopal Rao)- Development of a Look Up Table Simulator for Advanced Applications (Graduated in 2005-currently with Synopsis, India)
  • Manjula Rani (Guides: J.Vasi/V.Ramgopal Rao)-Border Trap Characterization for Sub 100 nm MNSFETs (Graduated in 2004 - joined Cypress, Bangalore)
  • Nihar Ranjan Mohapatra (Guides: V.Ramgopal Rao/M.P.Desai)-CMOS Scaling and Optimization for Logic and Memory Applications (Graduated in 2004-currently with AMD, Dresden, Germany)
  • Najeeb-Ud-Din (Guides: J.Vasi/V.Ramgopal Rao)- Single Halo Deep Submicron SOI MOSFETs for Analog Applications (Graduated in 2003 under the QIP Programme for college teachers, rejoined NIT-Srinagar)

Currently pursuing their Ph.D.:

  • Mrunal. A. K (Guide: V.Ramgopal Rao) - Bottoms-Up Approaches for Nano-scale CMOS Scaling
  • Mayank Srivastava (Guides: V.Ramgopal Rao/Dr. Maryam Shojaei): I/O Device Optimization for the sub 32 nm Node CMOS Technologies
  • Angada B Sachid (Guides: V.Ramgopal Rao/Dr. Maryam Shojaei): Multi-Gate MOSFETs
  • V.Seena (Guides: V.Ramgopal Rao/S.Mukherji) - Micro-fabricated Novel Sensor Structures for Medical Diagnostics
  • R.Ramesh (Guides: V.Ramgopal Rao/M.B.Patil)– ASIC Design using Polymer Transistors
  • Ravi Shankar Dudhe (Guides: V.Ramgopal Rao/Anil Kumar) - Polymer Based Sensors for Explosive Detection
  • Debabrata Maji (Guides:S.D.Gupta/V.RamgopalRao)-Gate Dielectrics for Germanium CMOS
  • Brajesh Pandey (Guides: A.N.Chandorkar/V.Ramgopal Rao) - I/O Optimization Issues for Nano-CMOS

Post-graduate Students

* Prof. Ramgopal Rao has supervised over 75 post-graduate/dual degree theses in the area of microelectronic/nanoelectronics at IIT Bombay till date.

INTERNATIONAL COLLABORATIONS

PAST/ONGOING INTERACTIONS/RESEARCH COLLABORATIONS: (interactions that resulted in joint publications/projects)

  • Intel-(Circuit Research Lab) (high-k modeling, mixed-signal CMOS, Multi-gate MOSFETs) (Current)
  • IBM (Technology Aware Design Challenges) (Current)
  • Infineon, Munich, Germany (IO Circuit Optimizations using Novel Devices) (Current)
  • Università della Calabria, Italy (High-k characterization for CMOS)(Current)
  • Tokyo Institute of Technology-Japan (Finfets) (Current)
  • Nanyang Technological University-Singapore (Organic Electronics) (Current)
  • IMEC-Belgium (Multi-gate MOSFETs)
  • Vishay Siliconix - USA (Super-junction Power MOSFETs)
  • International Rectifier Corporaton (Super-junction Power MOSFETs)
  • National University of Singapore (High-k Dielectric Characterization)
  • University of California -Los Angeles (Single Halo MOSFETs & Mixed signal CMOS)
  • Yale University (JVD nitrides)
  • Universitaet der Bundeswehr Munich-Germany (Vertical transistors)

BOOKS WRITTEN

Book Chapters:

  • “Impact of high-K gate dielectrics on the device and circuit performance of Nano-scale MOSFETs”, Manoj CR, V.Ramgopal Rao, “Dielectric Materials: Research, Technology and Applications”, Edited by Dr. Frank Columbus, Nova Science Publishers, Inc. (to be published)
  • “Development of a Bio-Chip for Cardiac Diagnostics”, Manoj Joshi, Nitin Kale, R.Lal, S. Mukherji and V. Ramgopal Rao; to be published in a CRC Handbook of Biomedical Engineering (3rd ed.), Edited by David Reisner, CRC Press, 2008
  • “Rare Earth Oxides in Microelectronics”, Kuniyuki Kakushima, Kazuo Tsutsui, Sun-ichiro Ohmi, V. Ramgopal Rao, and Hiroshi Iwai; RARE EARTH OXIDE THIN FILMS: GROWTH, CHARACTERIZATION , AND APPLICATIONS - TOPICS IN APPLIED PHYSICS 106: 345-365 2007 (Springer-Verlag Series on “Topics in Applied Physics”, Edited by M. Fanciulli and G. Scarel, Ed. 2007)
  • “Polymers in Electronics”, Saurabh Goyal, V.Ramgopal Rao; Specialty Polymers: Materials and Applications, I.K. International Private Limited, Edited by Dr. Faiz Mohammad, Ed. 2007, Category : Physical Sciences, ISBN : 8188237655

LIST OF PUBLICATIONS

POSITIONS AVAILABLE

  • If you have topped your university/college, or qualified in GATE with a respectable score or NET exam, please send your CV to rrao@ee.iitb.ac.in. There are always positions available for good students.
  • If you are aspiring to be a summer intern at IIT Bombay, please visit the web page for IIT Bombay Research Fellowship scheme.

CONTACT INFORMATION

Prof. V.Ramgopal Rao
Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email : rrao@ee.iitb.ac.in
Phone (Office) : (++91-22) - 2576 7456
Microelectronics office: ++91-22-25764482 Office room no: AA204
(EE Annnex, second floor) Fax: (++91-22)- 25723707
Microelectronics Group Homepage Nanoelectronics Centre Homepage Centre or Research in Nanotechnology & Science

OTHER INFORMATION

For personal details of Prof V.Ramgopal Rao, please click (**here**).

faculty/rrao_cropped.txt · Last modified: 2021/09/06 08:38 (external edit)