Professor, Electrical Engineering, IIT Bombay
PI, IIT Bombay Nanofabrication Facility
Professor-in-charge, IIT-OSU Frontier Research Center
Co-Professor-in-charge, IIT Bombay Research Park
Senior Member, IEEE

606, Nanoelectronics Building, 6th Floor
Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email : slodha[AT]ee.iitb.ac.in
Phone (Office): +91-22-25767460
Fax: +91 22 2572 3707

https://www.ee.iitb.ac.in/~slodha

• Ph.D. Electrical Engineering, Purdue University, 2004
• M.S. Electrical and Computer Engineering, Purdue University, 2001
• B. Tech. Electrical Engineering, Indian Institute of Technology Bombay, 1999

• Dec 2018 - present: Professor at Department of Electrical Engineering, IIT Bombay
• Sep 2014 - Nov 2018: Associate Professor at Department of Electrical Engineering, IIT Bombay
• Jul 2010 - Aug 2014: Assistant Professor at Department of Electrical Engineering, IIT Bombay
• Apr 2010 - Jul 2010: Staff Engineer (14nm and 22nm process integration) at PTD (Portland Tech. Dev.), Intel Corporation.
• Apr 2005 - Mar 2010: Senior Process Integration Engineer (32nm and 45nm technologies) at PTD (Portland Tech. Dev.), Intel Corporation.

• EE 101: Introduction to Electrical and Electronic Circuits (Under Graduate)
• EE 224: Digital Systems (Under Graduate)
• EE 227: Introduction to Microelectronics (Under Graduate)
• EE 733: Solid State Devices (Post Graduate)
• EE 207M: Electronic Devices and Circuits (Under Graduate Minor)
• EE 207: Electronic Devices and Circuits

• EE 214: Digital Systems Lab (Under Graduate)
• EE 318: Electronic Design Lab (Under Graduate)
• EE 672: Microelectronics Fabrication Lab (Post Graduate)

Google Scholar Profile (h-index: 26, i-index: 45)

• 2D materials and devices
• Wide bandgap power devices
• CMOS process integration and device physics
• Metal-semiconductor interfaces
• Molecular devices

• High speed 2D electronic and optoelectronic devices, DST Swarnajayanti Fellowship, 2018-2023, PI
• Nanoelectronics Network for Research and Applications (NNeTRA), 2018-2022, PI
• ALD Process Development for Carbon and Low-K Dielectrics, Applied Materials, 2018-2019, PI
• Silicon solar cells with carrier selective contacts, DST, 2016-2019, PI
• Si/SiGe/Ge Vertical Gate All Around Transistor Pathfinding Project, Applied Materials, 2013-2018, PI
• Indian Nanoelectronics Users’ Program (Phase II), DeitY, 2013-2018, PI
• IIT Bombay Research Park, MHRD, 2014-2017, co-PI

• Ge Transistor Pathfinding Project, Applied Materials, 2011-2012, PI
• Ge-based device development for sub-22nm node CMOS logic, DST, 2011-2014, PI (rated Excellent by DST)
• Hardware and process development for ALEt of various thin films using different process chemistries, Applied Materials, 2015-2016, PI
• Modelling and simulation of Germanium-based devices, Synopsys Inc., 2011-2013, co-PI
• Nanoscale Selection Device Dev for sub-20nm node High-Density Embedded Non-Volatile Memory, DST, 2011-2014, co-PI
• Material screening for memory and logic applications, Applied Materials, 2013-2014, co-PI
• Monolithic Integration of High Performance Germanium based Infrared Detector on Silicon, DST, 2013-2016, co-PI
• Inkjet Printed Flexible Thin TFTs, DST, 2013-2016, co-PI
• Centre of Excellence in Nano-electronics (Phase II), DeitY, 2011-2016, Investigator

• Prof. Siddharth Rajan, Ohio State University
• Dr. Dirch Hjorth Petersen, Technical University of Denmark (DTU), Copenhagen
• Prof. Mandar Deshmukh TIFR, Mumbai
• Prof. Viswanath Balakrishnan, IIT Mandi
• Prof. Debjani Karmakar BARC, Mumbai
• Prof. Dattatray Late NCL, Pune

69. A. Varghese, D. Saha, K. Thakar, V. Jindal, S. Ghosh, N. Medhekar, S. Ghosh, S. Lodha, “Near-direct bandgap WSe₂/ReS₂ type-II pn heterojunction for enhanced ultrafast photodetection and high-performance photovoltaics”, to appear in Nano Letters, 2020.

68. S. Dev, K. Khiangte, S. Lodha, “Wafer-scale mono-crystalline GeSn alloy on Ge by sputtering and solid phase epitaxy”, to appear in Journal of Physics D, 2020.

67. N. Goyal, D. MA Mackenzie, V. Panchal, H. Jawa, O. Kazakova, D. H. Petersen, S. Lodha, “Enhanced thermally aided memory performance using few-layer ReS₂ transistors”, Applied Physics Letters, 116 (5), 052104, 2020. Link

66. K. Thakar and S. Lodha, “Optoelectronic and Photonic Devices based on Transition Metal Dichalcogenides”, invited review article in Materials Research Express, 7 (1), 014002, 2020. Link

65. S. Dev, N. Pradhan, N. Variam and S. Lodha, “Impact of N2 Co-implant on Phosphorus Diffusion and Activation for n+/p Ge Junctions”, IEEE Transactions on Electron Devices, 67 (2), 419-423, 2020. Link

64. D. Saha, A. Varghese and S. Lodha, " Atomistic Modeling of van der Waals Heterostructures with Group-6 and Group-7 Monolayer Transition Metal Dichalcogenides for Near Infrared/Short-wave Infrared Photodetection” ACS Applied Nano Materials, 3 (1), 820-829, 2019. Link

63. J. F. McGlone, Z. Xia, C. Joishi, S. Lodha, S. Rajan, S. A. Ringel, and A. R. Arehart, “Identification of Critical Buffer Traps in Si Delta-dopedβ-Ga₂O₃ MESFETs”, Applied Physics Letters, 115 (15), 153501, 2019. Link

62. N. Goyal, S. Mahapatra and S. Lodha, " Ultra-fast Characterization of Hole Trapping Near Black Phosphorus (BP)/SiO₂ Interface During NBTI Stress in 2D BP p-FETs,” (Invited paper) IEEE Transactions on Electron Devices, 66 (11), 4572-4577, 2019. Link

61. K. Deka, A. Guleria, D. Kumar, J. Biswas, S. Lodha, S. D. Kaushik, S. Dasgupta, P. Deb, “Exclusive T2 MRI contrast enhancement by mesoporous carbon framework encapsulated manganese oxide nanoparticles”, Current Applied Physics 20 (1), 89-95, 2019. Link

60. S. Dev and S. Lodha, “Process Variation-Induced Contact Resistivity Variability in Nanoscale MS and MIS Contacts”, IEEE Transactions on Electron Devices, vol. 66, no. 10, 4320 - 4325, 2019. Link

59. P. Kumar, J. Biswas, J. Pandey, K. Thakar, A. Soni, S. Lodha and V. Balakrishnan”Selective oxidation of WS2 defect domain with sub monolayer thickness leads to multi-fold enhancement in Photoluminescence” Advanced Material Interfaces, 1900962, 2019. Link

58. N. Goyal, N. Parihar, H. Jawa, S. Mahapatra, S. Lodha “Accurate Threshold Voltage Reliability Evaluation of Thin Al₂O₃ Top Gate Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses”, ACS Applied Materials and Interfaces, 11, 26, 23673-23680, 2019. Link

57. C. Joishi, Y. Zhang, Z. Xia, W. Sun, A. R. Arehart, S. Ringel, S. Lodha, and S. Rajan, “Breakdown characteristics of β-(Al_0.22Ga_0.78)₂O₃/Ga₂O₃ field-plated modulation doped field effect transistors with SiNx passivation”, IEEE Electron Device Letters, 40 (8), 1241-1244, 2019. Link

56. Z. Xia, H. Xuu, C. Joishi, J. McGlone, N. K. Kalarickal, S. H. Sohel, M. Brenner, S. Ringel, S. Lodha, W. Lu, S. Rajan, “β-Ga₂O₃ Delta-Doped Field Effect Transistors with Current Gain Cutoff Frequency of 27 GHz“, IEEE Electron Device Letters, 40 (7), 1052-1055, 2019. Link

55. D. Biswas, C. Joishi, J. Biswas, K. Thakar, S. Rajan and S. Lodha, “Enhanced n-type β-Ga₂O₃ (201) gate stack performance using Al₂O₃/SiO₂ bi-layer dielectric”, Applied Physics Letters, 114, 212106, 2019. Link

54. J. Biswas, N. Pradhan, D. Biswas, S. Das, S. Mahapatra, S. Lodha, “Impact of punch-through stop implants on channel doping and junction leakage for Ge p-FinFET applications”, IEEE Transactions on Electron Devices, 66 (4), 1635-1641, 2019. Link

53. A. Tyagi, K. Ghosh, A. Kottantharayil, S. Lodha, “An Analytical Model for the Electrical Characteristics of Passivated Carrier-Selective Contact Solar Cell”, IEEE Transactions on Electron Devices, 66 (3), 1377-1385, 2019. Link

52. K. Deka, A. Guleria, D. Kumar, J. Biswas, S. Lodha, S. Kaushik, S. Choudhary, S. Dasgupta and P. Deb, “Janus Nanoparticles for Contrast Enhancement of T1-T2 Dual Mode Magnetic Resonance Imaging”, Dalton Transactions, 48 (3), 1075-1083, 2019. Link

51. K. Thakar, B. Mukherjee, S. Grover, N. Kaushik, M. Deshmukh, S. Lodha, ““Multilayer ReS₂ Photodetectors with Gate Tunability for High Responsivity and High Speed Applications”, ACS Applied Materials and Interfaces, 10, 42, 36512 (2018). Link

50. K. Saikia, K. Bhattacharya, D. Sen, S. D. Kaushik, J. Biswas, S. Lodha, B. Gogoi, A. K. Buragohain, W. Kockenberger, P. Deb, “Solvent evaporation driven entrapment of magnetic nanoparticles in mesoporous frame for designing a highly efficient MRI contrast probe”, Applied Surface Science, 464, 567-576 (2018). Link

49. C. Joishi, Z. Xia, J. MacGlone, Y. Zhang, A. R. Arehart, S. Ringel, S. Lodha, S. Rajan, “Effect of Buffer Iron Doping on Delta-Doped β-Ga2O3 Metal Semiconductor Field Effect Transistors”, Applied Physics Letters, 113, 123501 (2018). Link

48. C. Joishi, S. Ghosh, S. Kothari, N. Parihar, S. Mukhopadhyay, S. Mahapatra, S. Lodha, “Understanding PBTI in replacement metal gate Ge n-channel FETs with ultrathin Al₂O₃ and GeO_x ILs using ultrafast charge trap-detrap techniques”, IEEE Transactions on Electron Devices, 65 (10), 4245-4253 (2018). Link

47. D. Vaidya, S. Lodha, S. Ganguly, “Electrical-equivalent van der Waals gap for two-dimensional bilayers”, to appear in Physical Review Applied, (2018).

46. S. Singh, K. Thakar, N. Kaushik, B. Muralidharan, S. Lodha, “Performance Projections for Two-dimensional Materials in Radio-Frequency Applications” Physical Review Applied, 10 (1), 014022, (2018). Link

45. N. Kaushik, S. Ghosh and S. Lodha, “Low-Frequency Noise in Supported and Suspended MoS₂ Transistors”, IEEE Transactions on Electron Devices, 65 (10), 4135-4140 (2018). Link

44. S. Dev, M. Meena, Harshvardhan, S. Lodha, “Statistical Simulation Study of Metal Grain Orientation Induced MS and MIS Contact Resistivity Variability for 7 nm FinFETs”, IEEE Transactions on Electron Devices, 65 (8), 3104-3111 (2018).Link

43. Y. Zhang, C. Joishi, Z. Xia, M. Brenner, S. Lodha, S. Rajan, “Demonstration of β-(Al_xGa_1-x)₂O₃/Ga₂O₃ Double Heterostructure Field Effect Transistors”, Applied Physics Letters, 112 (23), 233503 (2018). Link

42. J. McGlone, Z. Xia, Y. Zhang, C. Joishi, S. Lodha, S. Rajan, S. Ringel, A. Arehart, “Trapping effects in Si δ-doped β-Ga₂O₃ MESFETs on an Fe-doped β-Ga₂O₃ substrate” IEEE Electron Device Letters, 39 (7), 1042-1045 (2018). Link

41. N. Goyal, N. Kaushik, H. Jawa, and S. Lodha, “Enhanced Stability and Performance of Few-Layer Black Phosphorus Transistors by Electron Beam Irradiation”, Nanoscale, vol. 10, issue 24, pp. 11616-11623 (2018). Link

40. S. Kothari, D. Vaidya, H. Nejad, N. Variam, S. Ganguly, and S. Lodha, “Plasma-assisted As Implants For Effective Work Function Modulation of TiN/HfO2 Gate Stacks on Germanium”, Applied Physics Letters, 112 (20), 203503 (2018). Link

39. Z. Xia, C. Joishi, S. Krishnamoorthy, S.Bajaj, Y. Zhang, M. Brenner, S. Lodha, S. Rajan. “Delta doped β-Ga2O3Field Effect Transistors with Regrown Ohmic Contacts”, IEEE Electron Device Letters, vol. 39, issue 4, pp. 568 - 571 (2018). Link

38. C. Joishi, S. Rafique, Z. Xia, L. Han, S. Krishnamoorthy, Y. Zhang, S. Lodha, H. Zhao, S. Rajan, “LPCVD grown β-Ga2O3 Bevel Field-plated Schottky Barrier Diodes”, Applied Physics Express, vol. 11, no. 3 (2018). Link

37. P. Kumar, N. Verma, N. Goyal, J. Biswas, S. Lodha, C. Nandi, V. Balakrishnan, “Phase engineering of seamless heterophase homojunctions with co-existing 3R and 2H phases in WS2 monolayers”, Nanoscale, 10, pp. 3320-3330 (2018). Link

36. K. Deka, A. Guleria, D. Kumar, J. Biswas, S. Lodha, S. D. Kaushik, S. Dasgupta, P. Deb, “Mesoporous 3D Carbon Framework Encapsulated Manganese Oxide Nanoparticles as Biocompatible T 1 MR Imaging Probe”, Colloids and Surfaces A: Physicochemical and Engineering Aspects, Vol. 539, pp. 229–236 (2018). Link

35. A. Tyagi, K. Ghosh, A. Kottantharayil, S. Lodha, “Performance Evaluation of Passivated Silicon Carrier Selective Contact Solar Cell”, IEEE Transactions on Electron Devices, Vol. 65, 1 (2018). Link

34. N. Kaushik, D. Mackenzie, K. Thakar, N. Goyal, B. Mukherjee, P. Boggild, D. H. Petersen, and S. Lodha, “Reversible Hysteresis Inversion in MoS2 Field Effect Transistors”, Nature 2D Materials and Applications, 1 (1), 34 (2017). Link

33. S. Krishnamoorthy, Z. Xia, C. Joishi, Y. Zhang, J. McGlone, J. Johnson, M. Brenner, A. Arehart, J. Hwang, S. Lodha, S. Rajan, “Modulation-doped β-(Al0.2Ga0.8)2O3/ Ga2O3 Field-Effect Transistor”, Appl. Phys. Lett., 111, 023502 (2017). Link

32. D. Vaidya, S. Lodha and S. Ganguly, “Ab-initio Study of NiGe/Ge Schottky Contact”, Journal of Applied Physics 121 (14), 145701 (2017). Link

31. D. Biswas, J. Biswas, S. Ghosh, B. Wood, and S. Lodha, “Enhanced thermal stability of Ti/TiO2/n-Ge contacts through plasma nitridation of TiO2 interfacial layer”, Applied Physics Letters, 110, 052104 (2017). Link

30. B. Mukherjee, N. Kaushik, R. P. N. Tripathi, A. M. Joseph, P. K. Mohapatra, S. Dhar, B. P. Singh, G. V. Pavan Kumar, E. Simsek, and S. Lodha, “Exciton Emission Intensity Modulation of Monolayer MoS2 via Au Plasmon Coupling” Scientific Reports, 7, 41175 (2017). Link

29. S. Karande, N. Kaushik, D. Narang, D. Late, and S. Lodha, “Thickness Tunable Transport in Alloyed WSSe Field Effect Transistors”, Applied Physics Letters, 109, 142101 (2016) Link

28. S. Ghosh, P. Bhatt, Y. Tiwari, C. Joishi, and S. Lodha, “Temperature and Field Dependent Low Frequency Noise Characterization of Ge n-FETs”, Journal of Applied Physics, 120, 095703 (2016). Link

27. S. Kothari, C. Joishi, H. Nejad, N. Variam, and S. Lodha, “Plasma-assisted low energy N2 implant for Vfb tuning of Ge gate stacks”, Applied Physics Letters, 109 (7), 072105. Link

26. S. Kothari, C. Joishi, D. Biswas, D. Vaidya, S. Ganguly, and S. Lodha, “Improved n-channel Ge gate stack performance using HfAlO high-k dielectric for varying Al concentration”, Applied Physics Express, 9 (7), 071302 (2016). Link

25. S. Dev, N. Remesh, Y. Rawal, P. P. Manik, B. Wood, and S. Lodha, “Low resistivity contact on n-type Ge using low work-function Yb with a thin TiO2 interfacial layer”, Applied Physics Letters, 108 (10), 103507 (2016). Link

24. A. Nipane, D. Karmakar, S. Karande, N. Kaushik and S. Lodha, “Few Layer MoS2 p-Type Devices Enabled by Selective Doping Using Low Energy Phosphorus Implantation”, ACS Nano, 10 (2), pp. 2128–2137 (2016). Link

23. N. Kaushik, D. Karmakar, A. Nipane, S. Karande, and S. Lodha, “Interfacial n-Doping using an Ultra-Thin TiO2 Layer for Contact Resistance Reduction in MoS2”, ACS Applied Materials and Interfaces, 8 (1), pp 256–263 (2016). Link

22. P. Paramahans Manik, and S. Lodha, “Contacts on n-type Germanium using variably doped ZnO and highly doped ITO interfacial layers”, Applied Physics Express, vol. 8, no. 5, 051302 (2015). Link

21. P. Bhatt, P. Swarnkar, A. Misra, J. Biswas, C. Hatem, A. Nainani, and S. Lodha, “Enhanced Ge n+/p Junction Performance Using Cryogenic Phosphorous Implantation”, IEEE Transactions on Electron Devices 62 (1),69 (2015). Link

20. A. Ray, R. Nori, P. Bhatt, S. Lodha, R. Pinto, V. R. Rao, F. Jomard, M. Neumann-Spallart, “Optimization of a plasma immersion ion implantation process for shallow junctions in silicon”, Journal of Vacuum Science & Technology A 32 (6), 061302 (2014). Link

19. S. Mukherjee, R. Singh, S. Gopinathan, S. Murugan, S. Gawali, B. Saha, J. Biswas, S. Lodha, A. Kumar,”Solution Processed Poly(3,4-ethylenedioxythiophene) thin films as transparent Conductor: Effect of p-Toluenesulphonic Acid in Dimethyl Sulfoxide”, ACS Applied Materials & Interfaces, 6 (20), 17792–17803 (2014). Link

18. N. Kaushik, A. Nipane, F. Basheer, S. Dubey, S. Grover, M. Deshmukh, S. Lodha, “Schottky Barrier Heights for Au and Pd Contacts to MoS2”, Applied Physics Letters, 105, 113505 (2014). Link

17. P. Bhatt, P. Swarnkar, F. Basheer, C. Hatem, A. Nainani, S. Lodha, “High Performance 400 ºC p+/n Ge Junctions Using Cryogenic Boron Implantation”, IEEE Electron Device Letters, 35 (7), 717-719 (2014). Link

16. S. Mittal, S. Gupta, A. Nainani, M.C. Abraham, K. Schuegraf, S. Lodha, and U. Ganguly “Epitaxially Defined (ED) FinFET: Variability Resistant and High Performance Technology”, IEEE Transactions on Electron Devices, 61 (8), 2711 - 2718 (2014). Link

15. P. Bhatt, K. Chaudhuri, S. Kothari, A. Nainani, S. Lodha, “Germanium oxynitride gate interlayer dielectric formed on Ge(100) using decoupled plasma nitridation”, Applied Physics Letters, 103, 172107 (2013). Link

14. R. Mandapati, A. Borkar, V. S. S. Srinivasan, P. Bafna, P. Karkare, S. Lodha, B. Rajendran, and U. Ganguly, “On Pairing of Bipolar RRAM Memory with NPN Selector based on Set/Reset Array Power Considerations”, IEEE Transactions in Nanotechnology, 12, no. 6 , 1178-1184 (2013).Link

13. R. Mandapati, A. Borkar, V. S. S. Srinivasan, P. Bafna, P. Karkare,S. Lodha, U. Ganguly, “The Impact of n-p-n Selector-Based Bipolar RRAM Cross-Point on Array Performance”, IEEE Transactions on Electron Devices, vol. 60, no. 10, 3385-3392 (2013). Link

12. S. Gupta, P. Paramahans Manik, R. K. Mishra, A. Nainani, M. C. Abraham, S. Lodha, “Contact resistivity reduction through interfacial layer doping in metal-interfacial layer-semiconductor contacts”, Journal of Applied Physics, 113, 234505 (2013). Link

11. S. Sant, S. Lodha, U. Ganguly, S. Mahapatra, S. Ganguly, V. Moroz, L. Smith, and F. Heinz, “Calculations of band gap bowing and band offsets in relaxed and strained Si1−xGex alloys by employing a new nonlinear interpolation scheme,” Journal of Applied Physics, 113, 033708 (2013). Link

10. P. Paramahans, R. K. Mishra, V. Pavan Kishore, P. Ray, A. Nainani, Y-C. Huang, M. C. Abraham, U. Ganguly, and S. Lodha, “Fermi-level unpinning and low resistivity in contacts to n-type Ge with a thin ZnO interfacial layer”, Applied Physics Letters, 101, 182105 (2012). Link

9. V. S. Srinivasan, S. Chopra, P. Karkare, P. Bafna, S. Lashkare, P. Kumbhare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, U Ganguly, “Punch-through Diode based Bipolar RRAM Selector by Si Epitaxy”, IEEE Electron Devices Letters, 33, 1396 (2012). Link

8. V. Pavan Kishore, P. Paramahans, S. Sadana, U. Ganguly, and S. Lodha, “Nanocrystal-based Ohmic contacts on n and p-type germanium”, Applied Physics Letters, 100, 142107 (2012). Link

7. P. D. Carpenter, S. Lodha, D. B. Janes, A. V. Walker, “Characterization of gold contacts in GaAs-based molecular devices: Relating structure to electrical properties”, Chemical Physics Letters, 472, 220 (2009).

6. S. Lodha and D. B. Janes, “Metal/Molecule/P-type GaAs Heterostructure Devices,” Journal of Applied Physics, 100, 024503 (2006).

5. S. Lodha, P. Carpenter and D. B. Janes, “Effect of Contact Properties on Current Transport in Metal/Molecule/GaAs Devices,” Journal of Applied Physics, 99, 024510 (2006).

4. S. Ghosh, H. Halimun, A. Mahapatro, J. Choi, S. Lodha and David Janes, “Device structure for electronic transport through individual molecules using nanoelectrodes,” Applied Physics Letters, 87, 233509 (2005).

3. S. Lodha and David B. Janes, “Enhanced current densities in Au/molecule/GaAs devices,” Applied Physics Letters, 85, 2809 (2004).

2. S. Lodha, David B. Janes and Nien-Po Chen, “Unpinned interface Fermi level in Schottky contacts to n-GaAs capped with low-temperature-grown GaAs; experiments and modeling using defect state distributions,” Journal of Applied Physics, 93, 2772 (2003).

1. S. Lodha, David B. Janes and Nien-Po Chen, “Fermi level unpinning in ex-situ Schottky contacts on n-GaAs capped with low-temperature-grown GaAs,” Applied Physics Letters, 80, 4452 (2002).

1. S. Ghosh, S. Dhara, A. Varghese, K. Thakar, S. Lodha, " Tunable WSe2 phototransistor enabled by electrostatically doped lateral p-n homojunction”, 77th Device Research Conference, Ann Arbor, June 23-26, 2019.
2. K. Thakar, S. Lodha, “Photo-amplification in Bipolar WSe2 Transistors with Electrostatic Gating”, 77th Device Research Conference, Ann Arbor, June 23-26, 2019.
3. S. Dhara, K. Thakar, S. Ghosh, A. Varghese, S. Mahapatra, S. Lodha, “Comparative Evaluation of vdW Materials Based PN Junction and FET for Gas Sensing” , 77th Device Research Conference, Ann Arbor, June 23-26, 2019.
4. S. Lodha, K. Thakar, S. Singh, B. Mukherjee, N. Kaushik, S. Grover, B. Muralidharan, M. Deshmukh, “Physics and Modeling of Two-dimensional (2D) RF Transistors and Photodetectors”, Invited paper, 3rd Electron Devices Technology and Manufacturing Conference (EDTM), Singapore, March 2019.
5. S. Kothari, J. S. Rathore, K. Khiangte, S. Mahapatra and S. Lodha, “Interlayer Engineering in GeSn Gate Stacks for Advanced CMOS”, 4th IEEE ICEE, Bengaluru, Dec. 2018. Best paper award
6. S. Dev, N. Pradhan, N. Variam, S. Lodha, “Impact of N2 implant on Phosphorus diffusion for shallow n+/p Ge junctions”, 4th IEEE ICEE, Bengaluru, Dec. 2018. Best poster award
7. K. Thakar, A. Varghese, S. Dhara, S. Ghosh and S. Lodha, “Low-EOT MoS 2 FET for Efficient Photodetection and Gas Sensing”, 4th IEEE ICEE, Bengaluru, Dec. 2018. Best manuscript award
8. B. Mukherjee, S. Roy, E. Simsek, S. Ghosh, V. G. Achanta, S. Lodha, “Plasmonic Enhancement in Anisotropic Thin Films of Rhenium Disulphide (ReS2), 31st Annual Conference of the IEEE Photonics Society, Reston, VA, USA, Sept. 30- Oct 4, (2018).
9. A. Varghese, D. Joseph, S. Ghosh, K. Thakar, N. Medhekar, S. Lodha, “WSe2/ReS2 vdW Heterostructure for Versatile Optoelectronic Applications”, 76th Device Research Conference, Santa Barbara, June 24-27, 2018.
10. N. Goyal, D. M.A. Mackenzie, V. Panchal, H. Jawa, O. Kazakova, D. H. Petersen, S. Lodha, “Thermally Aided Nonvolatile Memory Using ReS2 Transistors”, 76th Device Research Conference, Santa Barbara, June 24-27, 2018.
11. H. Jawa, S. Dhara, K. Thakar, S. Ghosh, S. Lodha, “Evaluating Performance of Dual-Gate InSe FETs”, 76th Device Research Conference, Santa Barbara, June 24-27, 2018.
12. C. Joishi, Z. Xia, J. McGlone, Y. Zhang, A. R. Arehart, S. Ringel, S. Lodha, S. Rajan, “Substrate Effects on Transport and Dispersion in Delta-Doped β-Ga2O3 Field Effect Transistors”, 60th Electronic Materials Conference, Santa Barbara, June 27-29, 2018.
13. Z. Xia, C. Joishi, S. Krishnamoorthy, S. Bajaj, Y. Zhang, M. Brenner, S. Lodha, S. Rajan, “Delta-doped β-Ga 2 O 3 Field Effect Transistors for Radio Frequency Operation”, 60th Electronic Materials Conference, Santa Barbara, June 27-29, 2018.
14. D. M. A. Mackenzie, P. R. Whelan, A. Shivayogimath, N. Kaushik, N. Goyal, J. M. Caridad, J. D. Thomsen, T. J. Booth, L. Gammelgaard, B. S. Jessen, S. Lodha, P. Bøggild, D. H. Petersen, “Quality Assessment of 2D Materials: continuity, uniformity and accuracy of mobility measurements”, GraphIn2018, Bilbao, Spain, March 13-15, 2018.
15. D. Vaidya, S. Lodha and S. Ganguly, “Comparison of Basis Sets for Efficient Ab-initio Modeling of Semiconductors”, SISPAD, Japan, 2017.
16. S. Kothari, H. Nejad, N. Variam, S. Lodha, “Multi-VT with metal gate work-function modulation by PLAD implants for Ge FinFET applications”, SSDM, Japan, 2017.
17. S. Krishnamoorthy, Z. Xia, C. Joishi, S. Bajaj, Y. Zhang, M. Brenner, S. Lodha, S. Rajan, “Towards Modulation-doped β-(AlGa)2O3/ Ga2O3 Field Effect Transistors for High Frequency Electronics”, 2nd International Workshop on Gallium Oxide and Related Materials Parma (Italy) – September 12-15, 2017.
18. Z. Xia, S. Krishnamoorthy, C. Joishi, S. Bajaj, Y. Zhang, M. Brenner, S. Lodha, S. Rajan, “ Delta-doped β-Ga2O3 Metal Semiconductor Field Effect Transistors with Regrown Ohmic Contacts”, 2nd International Workshop on Gallium Oxide and Related Materials Parma (Italy) – September 12-15, 2017.
19. Z. Xia, S. Krishnamoorthy, C. Joishi, S. Bajaj, Y. Zhang, M. Brenner, S. Lodha, S. Rajan “Delta-doped β-Ga2O3 Field Effect Transistors with Patterned Regrown Ohmic Contacts,” MRS Fall Meeting, Boston, 2017.
20. S. Das, A. Singh, T. Kundu, S. Lodha, V. R. Rao, “Off-stoichiometry thiol-ene polymer with tunable localized surface-plasmon resonance for flexible optoelectronic Lab-on Chip device application”, International Conference on Smart Materials, Structure & System (ISSS2017), IISc, Bangalore, July 2017.
21. B. Mukherjee, K. Thakar N. Kaushik and S. Lodha, “Suspended ReS2 FET for Improved Photocurrent-time Response”, 75th DRC, June 25-28, Notre Dame, USA 2017.
22. N. Goyal, N. Kaushik, H. Jawa and S. Lodha, “Effect of Electron Beam Irradiation on Black Phosphorus Field EffectTransistor Performance”, 75th DRC, June 25-28, Notre Dame, USA 2017.
23. A. Tyagi, K.Ghosh, A. Kottantharayil, and S. Lodha, “Carrier Selective Back Contact (CSBC) Solar Cell using Transition Metal Oxides”, PVSC, June 25-30, Washington DC, USA, 2017.
24. C. Joishi, S. Kothari, S. Ghosh, S. Mukhopadhyay, S. Mahapatra, and, S. Lodha “Ultrafast PBTI characterization on Si-free gate last Ge nFETs with stable and ultrathin Al2O3 IL” accepted at International Reliability Physics Symposium (IRPS), Monterey, CA, April 2017.
25. P. P. Manik, S. Dev, N. Remesh, Y. Rawal, S. Khopkar, S. Lodha, “Ge n-channel FinFET Performance Enhancement Using Low Work Function Metal-Interfacial Layer-Ge Contacts” accepted at VLSI-TSA, Hsinchu, Taiwan, April 2017.
26. S. Bhatia, S. Kothari, N. Raorane, S. Lodha, P.R. Nair, A. Antony, “Minority Carrier Lifetime Enhancement of C-Si/TiO2 Heterojunction by Post Deposition Annealing”, 32nd European Photovoltaic Solar Energy Conference and Exhibition, Munich, 2016.
27. S. Ghosh, P. Bhatt, Y. Tiwari, S. Lodha, “Low Frequency Noise and Mobility Correlation from RT to Low Temperatures for n-Channel Ge MOSFETs”, SSDM, Japan, 2015.
28. D. Vaidya, A. Nainani, N. Yoshida, B. Wood, S. Lodha, S. Ganguly, “Integrated modeling platform for high-k/alternate channel material heterostructure stacks”, SISPAD, September 9-11, Washington DC, USA, 2015.
29. S. Kothari, C. Joishi, D. Vaidya, H. Nejad, B. Colombeau, S. Ganguly, S. Lodha,”Metal Gate VT Modulation Using PLAD N2 Implants for Ge P-FinFET Applications”, ESSDERC, Austria, 2015.
30. Ankur Nipane, Naveen Kaushik, Shruti Karande, Debjani Karmakar and Saurabh Lodha, “P-type doping of MoS2 with phosphorus using a plasma immersion ion implantation (PIII) process”, Device Research Conference, June 22-24, Ohio, 2015.
31. Naveen Kaushik, Ankur Nipane, Shruti Karande and Saurabh Lodha, “Contact resistance reduction in MoS2 FETs using ultra-thin TiO2 interfacial layers”, Device Research Conference, June 22-24, Ohio, 2015.
32. Shraddha Kothari, Chandan Joishi, Dipankar Biswas, Dhirendra Vaidya, Swaroop Ganguly, Saurabh Lodha, “Enhanced Ge n-channel gate stack performance using HfAlO high-k dielectric”, Device Research Conference, June 22-24, Ohio, 2015.
33. N. Remesh, S. Dev, Y. Rawal, S. Khopkar, P. P. Manik, B. Wood, A. Brand, S. Lodha, “Contact barrier height and resistivity reduction using low work-function metal (Yb)-interfacial layer-semiconductor contacts on n-type Si and Ge”, Device Research Conference, June 22-24, Ohio, 2015.
34. S. Dutta, S. Mittal, S. Lodha, U. Ganguly, J. Schulze, “A Bulk Planar SiGe Quantum-Well based ZRAM with Low VT Variability”, IMW, Monterey, CA, 2015.
35. P. Bhatt, P. Swarnkar, S. Mittal, F. Basheer, C. Thomidis, C. Hatem, B. Colombeau, N. Variam, A. Nainani, and S. Lodha, “Cryogenic implantation for source/drain junctions in Ge p-channel (Fin)FETs,” Device Research Conference, June 22-26, Santa Barbara, USA.
36. P. P. Manik, R. K. Mishra, U. Ganguly, S. Lodha, “Indium tin oxide (ITO) and Al-doped ZnO (AZO) interfacial layers for Ohmic contacts on n-type Germanium,” Device Research Conference, June 22-26, Santa Barbara, USA.
37. N. Kaushik, A. Nipane, F. Basheer, S. Dubey, S. Grover, M. Deshmukh, S. Lodha, “Evaluating Au and Pd contacts in mono and multilayer MoS2 transistors,” Device Research Conference, June 22-26, Santa Barbara, USA.
38. S. Mittal, S. Kurude, S. Dutta, P. Debashis, S. Ganguly, S. Lodha, A. Laha, U. Ganguly, “Epitaxial Rare Earth Oxide (EOx) FinFET: a variability-resistant Ge FinFET architecture with multi VT,” Device Research Conference, June 22-26, Santa Barbara, USA.
39. Yaksh Rawal, Debashree Burman*, Prashanth P. Manik, Piyush Bhatt, Anoop C., Saurabh Lodha, Swaroop Ganguly, Maryam Shojaei Baghini, “Performance Comparison of MIM and MIS Diodes for Energy Harvesting Applications,” IEEE International Conference of Electron Devices and Solid-State Circuits, Chengdu, June 18-20, 2014.
40. P. Bhatt, P. Swarnkar, A. Misra, J. Biswas, C. Hatem, A. Nainani, S. Lodha, “Ge n+/p junctions using temperature-based phosphorous implantation,” accepted in 7th International SiGe Technology and Device Meeting (ISTDM 2014), 2 – 4 June 2014, Singapore.
41. R. Meshram, B. Das, R. Mandapati, S. Lashkare, S. Deshmukh, J. Schulze, S. Lodha, U. Ganguly, “High Performance Triangular Barrier Engineered NIPIN Selector for Bipolar RRAM”, International Memory Workshop, Taiwan, 2014.
42. P. Bhatt, P. Swarnkar, A. Misra, C. Hatem, A. Nainani and S. Lodha, “Cryo Implanted High Performance n+/p Junctions in Ge for future CMOS”, IEEE VLSI TSA, Hsinchu, Taiwan, April 2014. (Shortlisted for best paper award).
43. P. Debashis, S. Mittal, S. Lodha and U. Ganguly “Dopant Deactivation: A new challenge in sub-20nm Scaled FinFETs”, IEEE VLSI TSA, Hsinchu, Taiwan, April 2014.
44. D. Vaidya, S. Sant, A. Hegde, S. Lodha, U. Ganguly, S. Ganguly, “Modeling Charge Control in Heterostructure Nanoscale Transistors”, invited talk at IWPSD, New Delhi, December 2013.
45. S. Mittal, P. Debashis, A. Nainani, M. C. Abraham, S. Lodha and U. Ganguly " Epi Defined (ED) FinFET with Dynamic Threshold: Reduced VT Variability, Enhanced Performance, and a novel Multiple VT”, IEEE INDICON, Mumbai, December 2013. (Best Paper Award)
46. R. K. Mishra, P. P. Manik, A. Nainani, S. Lodha, “Contacts to N-Type Si/Ge/Si:C Using Rare Earth Metals”, MRS Fall Meeting, Boston, Dec, 2013.
47. H. Mehta, S. Lodha, U. Ganguly, S. Ganguly, “Calibration of the Density-Gradient TCAD Model for Germanium FinFETs”, IEEE Regional Symposium on Micro and Nanoelectronics, Malaysia, Sept, 2013.
48. R. K. Mishra, U. Ganguly, S. Ganguly, S. Lodha, A. Nainani, M. Abraham, “Nickel germanide with rare earth interlayers for Ge CMOS applications”, IEEE International Conference of Electron Devices and Solid-State Circuits, Hong Kong, Jun, 2013.
49. S. Lashkare, P. Karkare, P. Bafna, M.V.S. Raju, V.S.S. Srinivasan, J. Schulze, S. Chopra, S. Lodha, U. Ganguly, “A Bipolar RRAM Selector with Designable Polarity Dependent On-Voltage Asymmetry”, International Memory Workshop, 2013.
50. P. Bhatt, K. Chaudhuri, Maharaja P., A. Nainani, M. Abraham, M. Subramaniam, U. Ganguly, S. Lodha, “Improved Nitridation of GeO2 Interfacial layer for Ge Gate Stack Technology”, vol. 1561, MRS Online Proceedings Library, 2013.
51. S. Mittal, S. Gupta, A. Nainani, M. Abraham, K. Schuegraf, S. Lodha, and U. Ganguly, “Epi Defined (ED) FinFET: An alternate device architecture for high mobility Ge channel integration in PMOSFET”, 5th IEEE International Nanoelectronics Conference (INEC), Jan. 2-4, 367 (2013).
52. R. Mandapati, A. Borkar, S. Srinivasan, P. Bafna, P. Karkare, S. Lodha, and U.Ganguly, “On Pairing Bipolar RRAM memory element with novel punchthrough diode based selector: Compact modeling to array performance”, 5th IEEE International Nanoelectronics Conference (INEC), Jan. 2-4, 309 (2013).
53. K. Chaudhuri, P. Bhatt, A. Nainani, M. Abraham, M Subramaniam, S. Kapadia, K. Schuegraf, U. Ganguly, S. Lodha, “Comparison of plasma and thermal nitridation of GeO2 interfacial layer for Ge CMOS”, 43rd IEEE Semiconductor Interface Specialists Conference, San Diego, CA, December 6-8, 2012.http://dx.doi.org/10.1557/opl.2013.877
54. S. Sant, S. Lodha, U. Ganguly, S. Ganguly, “Novel nonlinear interpolation for Si1−xGex bandstructure parameters”, IEEE International Conference of Electron Devices and Solid-State Circuits, Bangkok, Dec, 2012.
55. S. Deshmukh, R. Mandapati, S. Lashkare, A. Borkar, V. S. S. Srinivasan, S. Lodha, U. Ganguly, “Comparison of novel punch-through diode (NPN) selector with MIM selector for Bipolar RRAM”, 2012 12th Non-Volatile Memory Technology Symposium (NVMTS 2012), Singapore, Oct 31st –Nov 2nd, 2012.
56. S. Chopra, P. Bafna, P. Karkare, S. Srinivasan, S. Lashkare, P. Kumbhare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, and U. Ganguly, “A Two Terminal Vertical Selector Device for Bipolar RRAM”, Pacific Rim Meeting on Electrochemical and Solid State Science (PRiME), Honolulu, Hawaii, USA, October 7-12 2012.
57. P. Paramahans, S. Gupta, R. K. Mishra, N. Agarwal, A. Nainani, Y. Huang, M.C. Abraham, S. Kapadia, U. Ganguly, S. Lodha, “ZnO: an attractive option for n-type metal-interfacial layer-semiconductor (Si, Ge, SiC) contacts”, VLSI Symposium on Technology, Hawaii, June 12-15 2012. http://dx.doi.org/10.1109/VLSIT.2012.6242472
58. P. Bafna, P. Karkare, S Srinivasan, S. Chopra, S. Lashkare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, U. Ganguly, “4F2 Two-Terminal Selector for Bipolar RRAM: High on-current density and Random Dopant Fluctuation Effect”, Device Research Conference, Pittsburgh, 2012.
59. S. Mittal, S. Gupta, A. Nainani, M.C. Abraham, K. Schuegraf, S. Lodha, U. Ganguly, “Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT”, Device Research Conference, Pittsburgh, 2012.
60. V. Pavan Kishore, P. Paramahans, S. Sadana, U. Ganguly, S. Lodha, “Contact Resistance Reduction on Germanium through Metal Work Function Engineering”, MRS Spring Meeting, San Francisco, 2012.
61. P. Paramahans, P. Ray, S. Mane, P. Nyaupane, U. Ganguly, S. Lodha, “Ohmic contacts to n-type Germanium using a thin ZnO interfacial layer”, MRS Spring Meeting, San Francisco, 2012.
62. V. Pavan Kishore, P. Paramahans, S. Sadana, U. Ganguly, S. Lodha, “Novel Nanocrystal-based Contacts on n and p-type Germanium”,39th Conference on the Physics and Chemistry of Surfaces and Interfaces (PCSI), Santa Fe, USA, January 2012.
63. P. Packan, S. Akbar, M. Armstrong, D. Bergstrom, M. Brazier, H. Deshpande, K. Dev, G. Ding, T. Ghani,O. Golonzka, W. Han, J. He, R. Heussner, R. James, J. Jopling, C. Kenyon, S.-H. Lee, M. Liu, S. Lodha, B. Mattis, A. Murthy, L. Neiberg, J. Neirynck, S. Pae, C. Parker, L. Pipes, J. Sebastian, J. Seiple, B. Sell, A. Sharma, S. Sivakumar, B. Song, A. St. Amour, k. Tone, T. Troeger, C. Weber, K. Zhang, Y. Luo, S. Natarajan, “High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors”, International Electron Devices Meeting, Baltimore, MD, 2009.
64. S. Natarajan, M. Armstrong; M. Bost., R. Brain, M. Brazier, C.-H. Chang, V. Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He, R. Heussner, R. James, I. Jin, C. Kenyon, S. Klopcic, S.-H. Lee, M. Liu, S. Lodha, B. McFadden, A. Murthy, L. Neiberg, J. Neirynck, P. Packan, S. Pae, C. Parker, C. Pelto, L. Pipes, J. Sebastian, J. Seiple, B. Sell, S. Sivakumar, B. Song, K. Tone, T. Troeger, C. Weber, M. Yang, A. Yeoh, K. Zhang, “A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171um2 SRAM cell size in a 291Mb array”, International Electron Devices Meeting, San Francisco, CA, 2008.
65. P. Carpenter, A. Scott, S. Lodha, D. Janes, C. Risko, M. Ratner, “Substrate and Dipole Effects in Metal-Molecule-Semiconductor Heterostructures”, in Proceedings of the 6th IEEE conference on Nanotechnology, Cincinnati, 2006, vol. 1, pp. 104-107.
66. S. Lodha and D. B. Janes, “Fabrication and electrical characterization of Au/molecule/GaAs devices,” in Proceedings of the 4th IEEE conference on Nanotechnology, Munich, 2004, pp. 278-80.
67. D. B. Janes, S. Ghosh, S. Lodha, J. Choi and S. Bhattacharya, “Metal-Molecule-Metal and Metal-Molecule-Semiconductor Devices,” IEEE Nanoscale Devices and Systems Integration Conference, Miami, FL, Feb. 16-19, 2004.
68. S. Lodha and D. B. Janes, “Metal-molecule-semiconductor heterostructures for nanoelectronic applications,” in Proceedings of the International Semiconductor Device Research Symposium, Washington D.C., 2003, pp. 446-7.
69. J. Choi, D. Janes, H. Halimun, S. Lodha, et al., “Metal-Molecule-Metal Structures with Pre-Fabricated Contacts,” in Proceedings of the 4th International Conference on Intelligent Processing and Manufacturing of Materials, Sendai, Japan, May 18-23, 2003.
70. S. Lodha, J. Choi, S. Bhattacharya and D. B. Janes, “Metal-molecule-semiconductor heterostructures for nano-device applications,” in Proceedings of the 3rd IEEE conference on Nanotechnology, San Francisco, Aug. 12-14, 2003, pp. 311-314.
71. S. Bhattacharya, J. Choi, S. Lodha, D. B. Janes, A. Bonilla, K. Jeong and G. Lee, “Electronic Conduction in DNA attached to Gold Electrodes,” in Proceedings of the 3rd IEEE conference on Nanotechnology, San Francisco, Aug. 12-14, 2003, pp. 79-82.
72. J. Choi, D. B. Janes, S. Lodha, Y. Chen, R. Agarwal, R. P. Andres, S. Burns and C. P. Kubiak, “Conduction through molecule-gold cluster complexes and applications,” in Proceedings of the 3rd IEEE conference on Nanotechnology, San Francisco, Aug. 12-14, 2003, pp. 164-167.
73. D. B. Janes, S. Ghosh, J. Choi, S. Lodha and S. Bhattacharya, “Circuit characteristics of molecular electronic components,” in Proceedings of IEEE international conference on Application-Specific Systems, Architectures, and Processors, Netherlands, June 24-26, 2003, pp. 120-126.
74. S. Bhattacharya, D. B. Janes, G. Lee, J. Choi, S. Lodha, A. Bonilla, “Measuring Electronic Conduction in DNA Attached to Au-Electrodes,” 45th Electronics Materials Conference, Salt Lake City, USA, June 25-27, 2003.
75. J. Choi, D. B. Janes, S. Lodha, Y. Chen, H. Halimun, S. Ghosh, S. Burns, C. P. Kubiak, “Metal-Molecules-Metal Devices with Preformed Metal Contact Structures,” 45th Electronics Materials Conference, Salt Lake City, USA, June 25-27, 2003.
76. S. Lodha, N-P. Chen, D. B. Janes, “Interface Fermi Level Unpinning in Schottky Contacts on N-Type Gallium Arsenide with a Thin Low-Temperature-Grown Cap Layer,” 44th Electronics Materials Conference, Santa Barbara, USA, June 26-28, 2002.
77. S. Lodha, D. B. Janes, S. Howell, M. V. Batistuta, E. H. Chen, R. Reifenberger, “Experimental and Modeling Studies of Schottky Contacts to Low-Temperature-Grown GaAs in Ex-Situ Structures,” 43rd Electronics Materials Conference, Notre Dame, USA, June 27-29, 2001.
78. A.Topkar, S. Lodha and J. Vasi, “Ionizing radiation induced degradation of SiGe HBTs,” in Proceedings of the 10th Intl. Workshop on Physics of Semiconductor Devices, New Delhi, India, Dec. 1999, pp. 659-662.

1. S. Lodha and D. Biswas, “Metal-interfacial layer-semiconductor contact with enhanced thermal stability”, Indian provisional patent (201821003281) filed, Jan 2018.
2. R. R. Arnepalli, P. Goradia, R. Visser, N. Ingle, M. Korolik, J. Biswas, S. Lodha, “Self-limiting atomic thermal etching systems and methods”, US patent US20180226278A1, 2018.
3. A. Tyagi, K. Ghosh, A Kottantharayil, S. Lodha, “Rear structured solar cells with carrier selective contacts”, Indian provisional patent TEMP/E-1/4637/2017-MUM filed, Feb 2016.
4. S. Mittal, S. Gupta, U. Ganguly, A. Nainani, S. Lodha, S. Ganguly, M. Abraham, E.-X. Ping, “Transistor design for improved performance and variability and method of fabrication”, Indian Patent filed.
5. S. Lodha, P. Paramahans, U. Ganguly, A. Nainani, M. Abraham, “Metal-Interfacial Semiconductor Layer-Semiconductor (MISS) Contacts”, Indian Patent filed.
6. U. Ganguly, S. Lodha, P. Bafna, P. Karkare, P. Kumbhare, S. Srinivasan, “Selector device for Bipolar RRAM”, Indian Patent filed.
7. S. Lodha, U. Ganguly, V. Pavan Kishore, “Method of forming low resistance metal contacts simultaneously on n and p-type semiconductors”, Indian Patent filed
8. S. Lodha, P. Ranade, C. Auth, “Method of forming CMOS transistors with dual metal silicide formed through the contact openings and structures formed thereby”, US Patent 7,861,406, 2011.

• Dipankar Saha (Phd from IISc Bangalore)
• Debasree Burman (Phd from IIT Kharagpur)

• Sachin Dev
• Sayantan Ghosh
• Kartikey Thakar (Visvesvaraya Fellowship)
• Astha Tyagi (Visvesvaraya Fellowship)
• Himani Jawa (Visvesvaraya Fellowship)
• Abin Varghese (IITB-Monash)
• Dipankar Biswas
• Srilagna Sahoo

• Ravikiran Lengare
• Prabhans Tiwari
• Abhik Bhattacharya

• Jayeeta Biswas

• Bablu Mukherjee (JSPS Postdoctoral Fellow, National Institute for Materials Science (NIMS), Japan)
• Akanksha Singh (Senior Project Scientist at IIT Kanpur)
• Sandipta Das (Post Doc at Technion-Israel Institute of Technology, Israel)

• Naveen Kaushik, Micron Technology, USA
• Piyush Bhatt, Applied Materials, India
• Prashanth Paramahans, Global Foundries,India
• Shraddha Kothari, Post doctoral fellow at U. of Southampton, UK
• Chandan Joishi, Post doctoral fellow at Ohio State University, USA
• Natasha Goyal, Western Digital, India
• Raju Mandapati (as co-supervisor), Global Foundries, India
• Sushant Mittal (as co-supervisor), Applied Materials, India
• Dhirendra Vaidya (as co-supervisor), TSMC, Taiwan
• Sangya Dutta (as co-supervisor), Max Linear, India
• Bhaskar Das (as co-supervisor), Max Linear, India

• Sushovan Dhara (Physics) 2019, PhD, Ohio State University
• Dennis Joseph (EE) 2018, Intel
• Sukhwinder Singh (EE) 2017, Japan
• Shruti Karande (EE) 2016, KLA Tencor
• Ankur Nipane (EE) 2015, (Best thesis award), TSMC, Columbia University
• Firdous Basheer (EE) 2014, TSMC
• Jitender Dahiya (EE) 2014,
• Ravi Kesh Mishra (EE) 2014, TSMC
• Prashant Swarnkar (EE) 2013, SanDisk
• Krishnakali Chaudhuri (EE) 2013, Purdue University
• V. Pavan Kishore (EE) 2012, TSMC
• Nitai Agarwal (EE) 2012, SONY, Japan
• Sunny Sadana (EE) 2011, Global Foundries, Singapore (with U. Ganguly)
• Shashank Gupta (EE) 2011, Stanford University (with U. Ganguly)

• Ankit Agrawal (EE, Dual Degree) 2016, Sysmex Corp., Japan
• Maneesh Meena (EE, Dual Degree) 2016
• Shyam Sunder Prasad (B. Tech) 2016
• Akash Saini (EE, Dual Degree) 2015, Times Internet
• Tejas Chaudhuri (EE, Dual Degree) 2015, Appsdaily Solutions Pvt. Ltd.
• Siddhant Khopkar (EE, Dual Degree) 2015, Wipro
• Manish Yadav (EE, Dual Degree) 2014
• Sanjesh Meena (EE, B. Tech) 2013, DRDO Labs
• Dev Kishan Chouhan (EE, B. Tech) 2013
• Ashwin Ganapathy (MEMS, Dual Degree) 2013 (with S. Mallick, MEMS), UC Davis
• Hardik Mehta (EE, Dual Degree) 2013, A. T. Kearney (with S. Ganguly)
• Sindhu Hari (EE, Dual Degree) 2013, Barclays (with S. Ganguly)

• Sivaramakrishnan, PhD candidate at IMEC, Belgium
• Dolar Khachariya, PhD candidate at NCSU, USA