Anwesha Mukhopadhyay

Abstract

Active second-harmonic ( 2ω ) filters have become an integral technology for single-phase power converters in high-power density designs. The series-stacked buffer (SSB) has emerged as an attractive topology among the existing solutions due to its low power, high efficiency, and compact design. However, one of the challenges in adopting SSB lies in its control, where hysteresis current control has been adopted conventionally. This results in a wide variation in the switching frequency, making the digital control implementation and filter design complex. On the other hand, fixed-frequency pulsewidth modulation (PWM) control necessitates developing a model for the systematic controller design to ensure stability and desired filtering performance. The assumption of SSB modeled as a second-harmonic current source, independent of the dc bus circuit components, fails to capture the dc bus loading effect on the SSB. In this work, a dynamic model of SSB is developed where the main dc bus and its passive elements are considered. The derived model enables a systematic approach for the controller design while ensuring the desired 2ω filtering. The stability limits and parameter sensitivities of the model are studied analytically and in simulations. The analytical model is validated, and the proposed controller performance and stability limit are verified experimentally on a hardware prototype. A video demonstrating the transition from stable to unstable operation is provided.

IEEE Xplore

Abstract

Second-harmonic ( 2ω ) filter is a critical constituent in the single-phase power conversion system and continues to trigger significant research interest. Due to the design and performance trade-offs between passive and active filters, hybrid filters have emerged as an attractive solution that combines the desired features. Moreover, in an existing system, re-tuning, retrofitting, or replacement of the passive filters becomes inevitable due to degraded filter characteristics with parameter drifts. Considering these requirements, an easily integrable active circuit, named solid state tuning restorer (SSTR), is proposed in this work to enhance the performance of an existing LC filter. Along with SSTR, the second-harmonic tuned passive LC filter forms a hybrid filter with adjustable characteristics capable of maintaining the tuned state over a range of operating frequencies and LC parameters. The low volt-ampere (VA) rating of SSTR, being less than 2% of the main converter, facilitates easy integration with the existing dc bus LC filter. Even in case of SSTR failure, the configuration offers a graceful degradation in the filter characteristics without disrupting the main converter. Thus, it improves the performance of an existing second-harmonic LC filter while not compromising its reliability. The operation, design constraints, and control methodology of the proposed SSTR are discussed, and the performance is validated through experiments on a hardware prototype.

IEEE Xplore

Abstract

Flexible characteristics, tunable parameters, and improved power density are the desired attributes that have led to widespread research on active capacitors and inductors (ACI) in power conversion systems. However, the two-terminal realisation of ACI is challenging due to different trade-offs between power density, device stress, and reliability of the added components. Moreover, the requirement of handling second-harmonic ripple makes bulk electrolytic capacitors nearly indispensable in two-terminal ACIs. Thus, the scope of power density improvement becomes constrained. Hence, active capacitors requiring minimum or no bulk dc capacitance are seen as an attractive technology in recent literature. However, such solutions can mimic either inductive or capacitive behaviour with a single converter unit, restricting their adaptability across different applications. This limitation is addressed in this work with the proposed unified active capacitor and inductor (UACI), realised without any bulk dc capacitor. It emulates variable capacitance and inductance while offering a smooth transition from one characteristic to another. High effective impedance due to a small susceptance at the transition duty prevents undesirable current overshoot during the transition. A laboratory-scale prototype of the proposed ACI is fabricated, and the hardware is verified up to ± 450 VAR.

IEEE Xplore

Abstract

Active Power Decoupling (APD) has emerged as an attractive technique to eliminate large DC bus filter capacitors in single-phase power conversion. For space-constrained circuits with reliable operation, DC capacitor elimination is an advantage as long as the added component count, rating, and control complexities do not outweigh the benefits. The present work focuses on adding a minimum number of active components of low voltage ratings to alleviate bulk DC bus filter capacitors from single-phase power converters. Thus, the driving circuits and control efforts also get proportionally scaled down while yielding the benefits of bulk capacitor reduction. Apart from the minimum component count, the use of low-voltage devices ensures reduced switching and conduction losses, improving the active filter efficiency. A generalized topology synthesis framework is presented that yields a family of low voltage, minimum switch-count APD filter derivatives with identical operational objectives. The control and operational trade-offs of the derived filter topologies are compared and a design-oriented ripple analysis is performed to maximize capacitor utilization. The significant attributes of the derived filters are compared with the state-of-the-art active and hybrid filters. The operations of the synthesized three unique topologies are experimentally validated using laboratory hardware at a 500 W power level. Above 90% reduction in the DC bus second-harmonic ripple is achieved by the action of the proposed filters. With the proposed control, the boost-based SC-BOHF topology exhibits better filtering performance than SC-BUHF and SC-BBHF.

IEEE Xplore

Abstract

This work examines the impact of symmetric twice-per-period sampling frequency on the dynamics of AC-link power converters. A series–series resonant converter, comprising both AC and DC state variables, is considered for the analysis. The AC states, associated with the tank circuit, exhibit half-wave antisymmetry, while the input and output DC states contain double-frequency components. As a result, all DC states can be regarded as half-wave symmetric with respect to the switching period. Discrete-time (DT) modeling is an effective technique for analyzing such high-frequency converters, offering improved prediction of high-frequency dynamics. In conventional DT modeling, sampling is performed once per switching period, resulting in a full-cycle model. However, when the converter states exhibit half-wave symmetry, this property can be leveraged to develop a half-cycle model. Such a model reduces the number of subintervals and, consequently, the number of differential equations to be solved, thereby lowering computational effort. This approach necessitates twice-per-period sampling and allows control updates at twice the switching frequency. This study explores the impact of such double-frequency sampling on the frequency response of the DT model, in comparison to the conventional once-per-period-sampling. The converter dynamics are captured experimentally and compared with the dynamics of half-cycle (hc) and full-cycle (fc) DT model.

IEEE Xplore

Abstract

This paper presents the design and implementation of a closed-loop control to synchronize the switching actions of an active rectifier (AR), as the onboard receiver of a wireless battery charger, with the offboard transmitter. A discrete time model of the wireless charger is used to model the synchronization dynamics. A compensator is designed to achieve stable performance over the full load range. The synchronization controller is designed to achieve a stable transition from passive to active rectification, and to reduce susceptibility to noise. To validate the control design, a GaN-based prototype is constructed and stable startup and low-noise synchronization experimentally demonstrated.

IEEE Xplore

Abstract

This paper focuses on a wireless charger for small autonomous aerial vehicles, where lightweight construction and high power density are essential for maximizing flight time. These requirements favor the use of an active rectifier which introduces the possibility of reverse power flow. This issue becomes particularly significant during constant-voltage (CV) charging, as the low charging current increases the likelihood of power reversal. In unidirectional systems, such as solar PV-fed chargers, reverse power flow must be prevented to avoid overcharging and potential damage to the input capacitor. To address this issue, a cascaded constant-current (CC)–constant-voltage (CV) control loop is developed. The charger is designed for a 6S LiPo battery pack without individual cell balancing circuits. To enhance protection, the proposed control scheme incorporates a modified voltage loop to prevent cell overcharging. The implementation of sensing, monitoring, and control mechanisms is presented in detail with relevant simulation and experimental results for a 200 W wireless charger prototype.

IEEE Xplore

Abstract

This paper presents a comprehensive discrete-time model of a wireless battery charger used to implement constant current (CC) and constant voltage (CV) charging control of the battery. The control objectives pertinent to wireless charging are identified and represented as multiple control loops in a block diagram that aids in visualizing the interactions between different control aspects. The separation of bandwidth is highlighted as a method for decoupling different control loops. An exact discrete-time model of the charger is developed and linearized to obtain the plant models for CC and CV mode charging. The closed-loop control is designed and verified experimentally on a 200 W prototype under steady-state and dynamic conditions.

IEEE Xplore

Abstract

Resonance frequency bifurcation is a common phenomenon in resonant tank circuits used in wireless battery chargers, leading to a drift between the transmitter and receiver frequencies. Studying this drift helps to define the acceptable operating frequency range to ensure efficient power transfer and maintain soft switching conditions. While this understanding aids in improving steady-state performance and efficiency, the control dynamics depend on the small-signal model and the resonant pole locations of the system under control. State-of-the-art literature, based on the discrete-time (DT) model, indicates that the plant resonant poles show up at frequencies much below the coil resonance frequencies. However, the qualitative origin of the poles at the lower frequency range is not apparent. It is also unclear how the resonant poles and the tank resonance frequencies are correlated. In this work, the origin of the resonant poles is investigated and a method is suggested for the quick approximations of the pole locations without numerically solving the discrete-time model. The analysis leads to understanding the relation between the pole locations and the sampling and tank resonance frequencies. A series-series LC resonant converter-based battery charger is considered for the study and experimental validation. The derived conclusions are verified with the results available in the literature. Though the analysis evolves based on a full-bridge converter, the formulation lends itself to complex resonant converter topologies.

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