Publications

Journal / Conference / Workshop

2021

Jaynarayan Tudu, Satyadev Ahlawat, Sonali Shukla, and Virendra Singh, `A framework for configurable for joint-scan design-for-test architecture`, Journal of Electronic Testing: Theory and Application (JETTA), 2021
Abhinish Anand, Winnie Thomas, Suryakant Toraskar, and Virendra Singh, `Predictive warp scheduling for efficient execution in GPGPU`, 31^st ACM Great Lake Symposium on VLSI (GLSVLSI`21), June 2021.
Winnie Thomas, Suryakant Toraskar, and Virendra Singh, `Dynamic optimization in GPU using Roofline model`, Proc. of International Symposium on Circuits and Systems (ISCAS`21), Daegu, Korea, May 2021
Vineesh VS, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, and Virendra Singh, `Enhanced design debugging with assistance from guidance based model checking`, IEEE Transaction on Computer Aided Design (TCAD), Vol. 14, No. 5, May 2021
Arindam Sarkar, Newton, Varun Venkitaraman, and Virendra Singh, `DAM: Deadlock aware migration techniques for STT-RAM based hybrid caches`, IEEE Computer Architecture Letters (CAL), Vol 20, No. 1, Jan 2021
Nirmal Kumar Boran, Shubhankit Rathore, Meet Udeshi, and Virendra Singh, `Fine-grained Scheduling in Heterogeneous-ISA Architectures`, IEEE Computer Architecture Letters (CAL), Vol. 20, No.1, Jan 2021
Harsh Bhargav, Vineesh VS, Binod Kumar and Virendra Singh, `Enhancing testbench quality via genetic algorithm`, Proc. of Mid-West Symposium on Circuits and Systems (MWSCAS) 2021

2020

Newton, Virendra Singh, and Trevor E. Carlson, `PIM-GraphSCC: PIM-based Graph Processing using Graph’s Community Structures`, IEEE Computer Architecture Letters (CAL), 2020
Vinod Guna, Vineesh V.S, Jaynarayan Tudu, Masahiro Fujita, and Virendra Singh, `LUT-based circuit approximation with targeted error guarantees`, 29^th IEEE Asian Test Symposium (ATS20), Penang, Malaysia, Nov 2020
Binod Kumar, Jay Adhaduk, Kanad Basu, Masahiro Fujita, and Virendra Singh, `A methodology to capture fine grained internal visibility during multi-session silicon debug`, IEEE Transaction on Very Large Scale Integrated Systems (TVLSI), vol. 28, No. 4, April 2020
Antara Ganguly, Shankar Balachandran, Anant Nori, Virendra Singh and Sreenivas Subramoney, `Characterization of data generating neural network workloads on x86 server architecture`, Workshop on Benchmarking Machine Learning Loads (MLBench20), Boston, Massachusetts, USA, April 2020.
Antara Ganguly, Shankar Balachandran, Anant Nori, Virendra Singh and Sreenivas Subramoney, `Characterization of data generating neural network application on x86 server architecture`, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Boston, Massachusetts, USA, April 2020.
Jiji Angel and Virendra Singh, `On the DSA key recovery attack with variable partial nonces known`, 3^rd ISEA International Conference on Security and Privacy (ISEA-ISAP), Guwahati, India, Feb 2020.
Binod Kumar, Swapaniel Thakur, Kanad Basu, Masahiro Fujita, and Virendra Singh, `A low overhead methodology for validating memory consistency models in chip multiprocessors`, 33^rd International Conference on VLSI Design (VLSID-20), Bangalore, India, Jan 2020.

2019

Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita and Virendra Singh, “A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors“, 33^rd International Conference on VLSI Design 2020, January 4-8, 2020
Binod Kumar, Akshay Kumar Jaiswal, Vineesh V S and Rushikesh Shinde, “Analyzing Hardware Security Properties of Processors through Model Checking“, 33^rd International Conference on VLSI Design 2020, January 4-8, 2020
Raj Kumar Choudhary, Newton Singh, Harideep Nair, Rishabh Rawat and Virendra Singh, “Freeflow Core: Enhancing Performance of In-order Cores with Energy Efficiency“, 37^th IEEE International Conference on Computer Design (ICCD) , Abu Dhabi, UAE, Nov 17-20, 2019
Varun Venkitaraman, Ashok Sathyan and Virendra Singh, “CBIT – A Synonym Handler for Low-latency and Energy-efficient Cache Hierarchy“, 37^th IEEE International Conference on Computer Design (ICCD) , Abu Dhabi, UAE, Nov 17-20, 2019
Ayush Agrawal and Virendra Singh, “O-Factor: Opportunistic Out of Order Scheduling for GP-GPUs“, 37^th IEEE International Conference on Computer Design (ICCD) , Abu Dhabi, UAE, Nov 17-20, 2019
Binod Kumar, Masahiro Fujita, and Virendra Singh, “SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement“, Journal of Electronic Testing: Theory and Application (JETTA), Oct 2019.
Antara Ganguly, Shankar Balachandran, Anant Nori, Virendra Singh and Sreenivas Subramoney, “Characterization of Data Movement Issues in Generation-based Neural Network Applications on x86 CPU Architecture, International Symposium on Memory Systems (MEMSYS) 2019, Washington DC, USA, October 2019
Antara Ganguly, Rajiv Muralidhar, Virendra Singh and Masahiro Fujita, “Towards Energy-efficient Architectures for Deep Learning“, European Conference on Machine Learning (ECML-PKDD) – Green Data Mining Workshop, Wurzburg, Germany, September 2019
Binod Kumar, Atul Kumar Bhosale, Masahiro Fujita and Virendra Singh, “Validating Multi-processor Cache Coherence Mechanisms Under Diminished Observability” 28^th IEEE Asian Test Symposium(ATS) 2019, Kolkata, India, December 10-13, 2019
Vineesh V S, Binod Kumar, Rushikesh Shinde, Akshay Kumar Jaiswal, Harsh Bhargava and Virendra Singh, “Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification” 28^th IEEE Asian Test Symposium(ATS) 2019, Kolkata, India, December 10-13, 2019
Satyadev Ahlawat, Jaynarayan Tudu, Masahiro Fujita, and Virendra Singh, “Securing Scan Architecture through Test Response Encryption” 32^nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) 2019, ESA-ESTEC & TU Delft, Netherlands, October 02-04, 2019
Nirmal Kumar Boran, Dinesh Kumar Yadav and Rishabh Iyer, “Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA multi-core Architectures” 25^th International Symposium on VLSI Design and Test (VDAT) 2019, Indore, India, July 1-3, 2019
Vineesh V. S., Jay Adhaduk and Binod Kumar, “Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods“, 25^th International Symposium on VLSI Design and Test (VDAT) 2019, Indore, India, July 1-3, 2019
Saurabh Gangurde and Binod Kumar, “A unified methodology for hardware obfuscation and IP watermarking“, 25^th International Symposium on VLSI Design and Test (VDAT) 2019, Indore, India, July 1-3, 2019
Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan Tudu, Masahiro Fujita, and Virendra Singh, “Securing Scan through Plain-text Restriction“, 25^th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Rhode Island, Greece, July 1-3, 2019
Antara Ganguly, Rajeev Muralidhar, and Virendra Singh, “Towards Energy Efficient non-von Neumann Architectures for Deep Learning“, 20^th International Symposium on Quality Electronic Design (ISQED), 2019, Santa Clara, CA, USA, March 6-7, 2019, pp. 335-342
Binod Kumar, Kanad Basu, Masahiro Fujita, and Virendra Singh, “Post-silicon gate-level error localisation with effective & combined trace signal selection“, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. xx, No. xx, 2019 (In press)
Binod Kumar, Masahiro Fujita and Virendra Singh, “A Methodology for SAT-based Electrical Error Debugging during Post-silicon Validation“, 32^nd International Conference on VLSI Design (VLSID) 2019, Delhi, India, Jan 2019
Jaidev Shenoy, Virendra Singh, Kelly Ockunzzi and Kushal Kamal, “On-chip MISR compaction technique to reduce diagnostic effort and test time“, 32^nd International Conference on VLSI Design (VLSID) 2019, Delhi, India, Jan 2010

2018

Antara Ganguly, Virendra Singh, Rajiv Muralidhar, and Masahiro Fujita, “Memory system requirements for convolutional neural networks“, International Symposium on Memory Systems (MEMSYS) 2018, Washington DC, USA, October 2018
Satyadev Ahlawat, Darshit Vaghani, Naveen Bazard, and Virendra Singh, “Using MISR as countermeasure against scan based side channel attacks“, 16^th IEEE International East-West Design and Test Symposium (EWDTS) 2018, Kazan, Russia, September 2018
Satyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, and Virendra Singh, “A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test“, IEEE Transactions on Device and Materials Reliability (TDMR), Vol. 18, No. 2, pp. 321-331, June 2018
Ankit Jindal, Binod Kumar, Masahiro Fujita, and Virendra Singh, “Silicon debug with maximally expanded internal observability using nearest neighbour algorithm“, IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2018, Hongkong, SAR, China, July 2018
Suhit Pai, Newton, and Virendra Singh, “AB-Aware: Application Behavior Aware Management of Shared Last Level Caches“, 28^th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2018, Chicago, Illinois, USA, May 23-25, 2018
Darshit Vaghani, Satyadev Ahlawat, Jaynarayan Tudu, Masahiro Fujita, and Virendra Singh, “On Securing Scan Design Through Test Vector Encryption“, 51^st IEEE International Symposium on Circuits and Systems (ISCAS) 2018, Florence, Italy, May 2018
Nihar Hage, Satyadev Ahlawat, and Virendra Singh, “In-situ Monitoring for Slack Time Violation Without Performance Penalty“, 51^st IEEE International Symposium on Circuits and Systems (ISCAS) 2018, Florence, Italy, May 2018
Rohini Gulve and Virendra Singh, “ATPG Power Guards: On Limiting the Test Power below Threshold“, Proc. of Design Automation and Test in Europe (DATE), Dresden, Germany, March 2018
Toral Shah, Anzhela Matrosova, Masahiro Fujita, and Virendra Singh, “Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design“, Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 34, No. 1, February 2018
Ankit Jindal, Binod Kumar, Kanad Basu, and Masahiro Fujita, “ELURA: A Methodology for Post-silicon Gate-level Error Localization using Regression Analysis“, 31^st International Conference on VLSI Design (VLSID), Pune, India, Jan 2018

2017

Ankush Srivastava, Virendra Singh, Adit Singh, and Kewal Saluja, “A reliability aware methodology to isolate timing critical paths under aging“, Journal of Electronic Testing: Theory and Application (JETTA), Vol. 33, No. 6, December 2017
Newton, Sujit Mahto, Suhit Pai, and Virendra Singh, “DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching“, 35^th International Conference on Computer Design (ICCD), Boston Marriot Newton, Boston, MA, USA, November 2017
Satyadev Ahlawat, Darshit Vaghani, Jaynarayan Tudu, and Virendra Singh, “On Securing Scan Design from Scan-Based Side-Channel Attacks“, 26^th IEEE Asian Test Symposium (ATS) Taipei, Taiwan, Nov 2017

Ankush Srivastava, Adit Singh, Virendra Singh, and Kewal K. Saluja, “Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects“, 48^th IEEE International Test Conference (ITC) 2017, Fort Worth, Texas, USA, Nov 2017

Binod Kumar, Kanad Basu, Masahiro Fujita and Virendra Singh, “RTL Level Trace Signal Selection and Coverage Estimation During Post-Silicon Validation“, 19^th IEEE International High Level Design Validation and Test Workshop (HLDVT) 2017, Santa Cruz, CA, USA, October 2017

Satyadev Ahlawat, Darshit Vaghani, and Virendra Singh, “Preventing Scan-Based Side-Channel Attacks Through Key Masking“, 30^th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) 2017, Cambridge, UK, October 2017

Shoba Gopalkrishnan and Virendra Singh, “REMORA: A Hybrid Low-Cost Soft-Error Reliable Fault Tolerant Architecture 30^th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) 2017, Cambridge, UK, October 2017

Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, and Virendra Singh, “Improving post-silicon error detection with topological selection of trace signals“, 25^th IEEE/IFIP International Conference on on Very Large Scale Integratiion (VLSI-SoC) 2017, Abu Dhabi, UAE, October 2017

Rohini Gulve, Anshu Goel, and Virendra Singh, “PHP: Power hungry pattern generation at higher abstraction level“, 15^th IEEE East-West Design and Test Symposium (EWDTS), Novi Sad, Serbia, Sep 2017

Vineesh VS, Nihar Hage, Kartik B, and Virendra Singh, “On achieving full functional coverage for forwarding units of pipelined processors“, 15^th IEEE East-West Design and Test Symposium (EWDTS), Novi Sad, Serbia, Sep 2017

Satyadev Ahlawat, Darshit Vaghani, Jaynarayan Tudu, and Ashok Suhag, “A Cost Effective Technique for Diagnosis of Scan Chain Faults“, 21^st International Symposium on VLSI Design and Test (VDAT) 2017, Roorkee, India, July 2017

Sujit Kr. Mahto and Newton Singh, “ACAM: Application Aware Adaptive Cache Management for Shared LLC“, 21^st International Symposium on VLSI Design and Test (VDAT) 2017, Roorkee, India, July 2017

Anshu Goel and Rohini Gulve, “Multi-mode Toggle Random Access Scan to Minimize Test Application Time“, 21^st International Symposium on VLSI Design and Test (VDAT) 2017, Roorkee, India, July 2017

Rohini Gulve and Nihar Hage, “On Generation of Delay Test with Capture Power Safety“, 21^st International Symposium on VLSI Design and Test (VDAT) 2017, Roorkee, India, July 2017

Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey and Masahiro Fujita, “A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection“, 21^st International Symposium on VLSI Design and Test (VDAT) 2017, Roorkee, India, July 2017

Toral Shah and Virendra Singh, ‘Test Pattern Generation to Detect Multiple Faults in ROBDD based Combinational Circuits‘, 23^rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2017, Thessaloniki, Greece, July 2017

Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh, ‘Instruction-Based Self-Test for Delay Faults Maximizing Operating Temperature‘, 23^rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2017, Thessaloniki, Greece, July 2017

Binod Kumar, Ankit Jindal, Jaynarayan Tudu, Brajesh Pandey, Virendra Singh, ‘Revisiting Random Access Scan for Effective Enhancement of Post-silicon Observability‘, 23^rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2017, Thessaloniki, Greece, July 2017

Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, and Virendra Singh, ‘A Low Cost Technique for Scan Chain Diagnosis`, 50^th IEEE International Symposium on Circuits & Systems (ISCAS) 2017, Baltimore, MD, USA, May 2017

Abhishek Rajgadia, Newton Singh, and Virendra Singh, ‘EEAL: Processors’ Performance Enhancement Through Early Execution of Aliased Loads`, 27^th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2017, Alberta, Canada, May 2017

Binod Kumar, Ankit Jindal, Masahiro Fujita, and Virendra Singh, ‘Combining Restorability and Error Detection Ability for Effective Trace Signal Selection` 27^th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2017, Alberta, Canada, May 2017

Satyadev Ahlawat, Darshit Vaghani, Virendra Singh, ‘An Efficient Test Technique to Prevent Scan-Based Side-Channel Attacks`, 22^nd IEEE European Test Symposium (ETS) 2017, Limassol, Cyprus, May 2017

Toral Shah, Anzhela Matrosova, Binod Kumar, Masahiro Fujita and Virendra Singh,`Testing Multiple Stuck-at Faults of ROBDD Based Combinational Circuit Design`, 18^th IEEE Latin American Test Symposium (LATS) 2017, Bogota, Colombia, March 2017

Binod Kumar, Ankit Jindal, Masahiro Fujita and Virendra Singh, `Post-silicon Observability Enhancement with Topology Based Trace Signal Selection`, 18^th IEEE Latin American Test Symposium (LATS) 2017, Bogota, Colombia, March 2017

Ankush Srivastava, Virendra Singh, Adit Singh and Kewal Saluja, `Identifying High Variability Speed-Limiting Paths under Aging`, 18^th IEEE Latin American Test Symposium (LATS) 2017, Bogota, Colombia, March 2017

Nihar Hage, Rohini Gulve, Masahiro Fujita, and Virendra Singh, `On testing of superscalar processors in functional mode for delay faults`, 30^th International conference on VLSI Design (VLSID) 2017, Hyderabad, Jan 2017

Binod Kumar, Ankit Jindal, Virendra Singh, and Masahiro Fujita, `A methodology for trace signal selection to improve error detection in post silicon validation`, 30^th International conference on VLSI Design (VLSID) 2017, Hyderabad, Jan 2017

Binod Kumar and Brajesh Pandey, `On Leveraging formal methods to enhance trace mechanisms for efficient post-silicon debug`, 8^th IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) 2017, Hyderabad, India, Jan 2017

Toral Shah, `Multiple fault testability of BDD based circuit synthesi`, 8^th IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) 2017, Hyderabad, India, Jan 2017

Binod Kumar, Ankit Jindal, Jaynarayan Tudu, and Brajesh Pandey, `An Integrated solution for manufacturing testing and post-silicon validation`, 8^th IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) 2017, Hyderabad, India, Jan 2017

Satyadev Ahlawat and Darshit Vaghani, `On securing scan chain from side channel attack, 8^th IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) 2017, Hyderabad, India, Jan 2017

Shoba Gopalkrishnan, `On improving fault tolerance through hardware software techniques`, 8^th IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) 2017, Hyderabad, India, Jan 2017

2016

Binod Kumar, Ankit Jindal, Jaynarayan Tudu, and Virendra Singh, `A methodology for post silicon debug utilizing progressive random access scan architecture`, 17^th IEEE Workshop on RTL and High Level Testing (WRTLT) 2016, Hiroshima, Japan, Nov 2016

Rohini Gulve and Virendra Singh, `R-fill: Timing aware capture power reduction using ZOLP`, 17^th IEEE Workshop on RTL and High Level Testing (WRTLT) 2016, Hiroshima, Japan, Nov 2016

Ankush Srivastava, Virendra Singh, Adit Singh, and Kewal Saluja, `Path-based approach to identify timing critical paths under aging`, 17^th IEEE Workshop on RTL and High Level Testing (WRTLT) 2016, Hiroshima, Japan, Nov 2016

Nirmal Kumar Boran, Rameshwar Prasad Meghwal, Kuldeep Sharma, Binod Kumar, and Virendra Singh, `Performance modelling of heterogeneous ISA multicore architecture`, 14^th IEEE East-West Design and Test Symposium (EWDTS) 2016, Yerevan, Armenia, Oct 2016

Toral Shah, Virendra Singh and Anzhela Matrosova, `ROBDD based path delay fault testable combinational circuit synthesis`, 14^th IEEE East-West Design and Test Symposium (EWDTS) 2016, Yerevan, Armenia, Oct 2016

Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, and Virendra Singh, `Enabling LOS delay test with slow scan enable`, 14^th IEEE East-West Design and Test Symposium (EWDTS) 2016, Yerevan, Armenia, Oct 2016

Rohini Gulve and Virendra Singh, `ILP Based Don`t Care Bits Filling Technique For Capture Power Reduction`, 14^th IEEE East-West Design and Test Symposium (EWDTS) 2016, Yerevan, Armenia, Oct 2016

Binod Kumar, Boda Nehru, Brajesh Pandey, Jaynarayan T Tudu, and Virendra Singh, `A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture`, 14^th IEEE East-West Design and Test Symposium (EWDTS) 2016, Yerevan, Armenia, Oct 2016

Binod Kumar, Ankit Jindal and Virendra Singh, `A trace signal selection algorithm for improved post silicon debug`, 14^th IEEE East-West Design and Test Symposium (EWDTS) 2016, Yerevan, Armenia, Oct 2016

Shoba Gopalkrishnan and Virendra Singh, `REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture`, 22^nd IEEE International Symposium on Online Testing and Robust System Design (IOLTS) 2016, Catalunya, Spain, July 2016

Satyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, and Virendra Singh, `A high performance scan flip-flop design for serial and mixed mode scan test` 22^nd IEEE International Symposium on Online Testing and Robust System Design (IOLTS) 2016, Catalunya, Spain, July 2016

Jaynarayan Tudu and Satyadev Ahlawat, `Guided Shifting of Test Pattern to Minimize Test Time in Multiple Serial Scan`,20^th International Symposium on VLSI Design and Test (VDAT) 2016, Guwahati, India, May 2016

Satyadev Ahlawat and Jaynarayan T. Tudu, `On Minimization of Test Power through Modified Scan Flip-Flop`, 20^th International Symposium on VLSI Design and Test (VDAT) 2016, Guwahati, India, May 2016

Rohini Gulve, Nihar Hage and Jaynarayan T Tudu, `On Determination of Instantaneous Peak and Cycle Peak Switching using ILP`, 20^th International Symposium on VLSI Design and Test (VDAT) 2016, Guwahati, India, May 2016

Binod Kumar, Boda Nehru, Brajesh Pandey and Jaynarayan Tudu, `Skip-Scan: A Methodology for Test Time Reduction`, 20^th International Symposium on VLSI Design and Test (VDAT) 2016, Guwahati, India, May 2016

2015

Ankush Srivastava, Virendra Singh, Adit Singh, and Kewal Saluja, ‘A Methodology for Identifying High Timing Variability Paths in Complex Designs‘, 24^th IEEE Asian Test Symposium (ATS) 2015, Mumbai, India, Nov 2015

Satyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, and Virendra Singh, `A New Scan Flip-Flop Design to Eliminate Performance Penalty of Scan`, 24^th IEEE Asian Test Symposium (ATS) 2015, Mumbai, India, Nov 2015

Adithyalal P.M, Shankar Balachandran, and Virendra Singh, `A Soft Error Resilient Low Leakage SRAM Cell Design`, 24^th IEEE Asian Test Symposium (ATS) 2015, Mumbai, India, Nov 2015

Parth Lathigara, Shankar Balachandran, and Virendra Singh, `Application Behavior Aware Re-Reference Interval Prediction for LLC`, 33^rd IEEE International Conference on Computer Design (ICCD) 2015, New York, USA, October 2015

Toral Shah, Anzhela Matrosova, and Virendra Singh, `PDF Testability of a Combinational Circuit Derived by Covering ROBDD Nodes by Invert-And-Or Graph`, 19^th International Symposium on VLSI Design and Test (VDAT) 2015, Ahmedabad, India, May 2015

2014

D. Nikolov, U. Ingelsson, V. Singh, and E. Larsson, `Evaluation of level of confidence and optimization of roll-back recovery with check pointing for real time systems`, Microelectronics Reliability, vol. 54, 2014, pp. 1022-1049.
Jaynarayan Tudu and Virendra Singh, `Guided shifting of test patterns to minimize the test time in serial scan`, 15^th IEEE Workshop on RTL and High Level Testing (WRTLT) 2014, Hangzhou, China, Nov 2014

Prashant Singh, Toral Shah, and Virendra Singh, `An improved single input change based built-in-self-test for delay testing`, 15^th IEEE Workshop on RTL and High Level Testing (WRTLT) 2014, Hangzhou, China, Nov 2014

Lokesh Siddhu, Amit Mishra, and Virendra Singh, `Operand isolation circuit with reduced overhead for datapath design`, 27^th International Conference on VLSI Design (VLSID) 2014, Mumbai, India, Jan 2014

Anzhela Matrosova, Evgenii Mitrofanov, and Virendra Singh, `Fully delay testable sequential circuit design`, 5^th IEEE International Workshop on Reliability Aware Stystem Design and Test (RASDAT), Mumbai, India, Jan 2014

2013

A.Matrosova, E.Mitrofanov, and V.Singh, ‘Delay Testable Sequential Circuit Design‘, 11^th IEEE East-West Design and Test Symposium (EWDTS) 2013, Rostov-on-Don, Russia, Sept 2013

Jaynarayan Tudu, Deepak Malani, and Virendra Singh, `Level Accurate Peak Power Estimation using BILP`, 17^th International Symposium on VLSI Design and Test (VDAT) 2013, Jaipur, India, July 2013

2012

Suraj Sindia, Vishwani D. Agrawal, and Virendra Singh, `Parametric fault testing of non-linear analog circuits based on polynomial and v-transform coefficients`, Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 28, No. 5, pp. 557-571, 2012

Suraj Sindia, Vishwani D. Agrawal, and Virendra Singh, `Defect level and fault coverage in coefficient based analog circuit testing`, Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 28, No. 4, pp. 541-549, 2012

Satyadev Ahlawat, Ashok Suhag, Jaynarayan Tudu, and Virendra Singh, `Power aware scan flip-flop design for scan test`, 13^th IEEE Workshop on RTL and High Level testing (WRTLT) 2012, Niigata, Japan, Nov 2012

Pawan Kumar, and Virendra Singh, `Efficient regular expression pattern matching for network intrusion detection system using modified word based automata`, 5^th ACM International Conference on Security of Information and Networks (SIN) 2012, Jaipur, India, Oct 2012

Indira Rawat, M.K. Gupta, and Virendra Singh, `Scheduling test for 3D SOCs with temperature constraints`, 10^th IEEE International East West Design and Test Symposium (EWDTS) 2012, Kharkov, Ukrain, Sep 2012

A. Matrosova, E. Nikolaeva, D. Kudin, and V. Singh, `PDF testability of circuits derived by special covering ROBDDs with gates`, 10^th IEEE International East West Design and Test Symposium (EWDTS) 2012, Kharkov, Ukrain, Sep 2012

A. Matrosova, E. Nikolaeva, D. Kudin, and V. Singh, `PDF testability of circuits derived by special covering ROBDDs with gates`, 10^th IEEE International East West Design and Test Symposium (EWDTS) 2012, Kharkov, Ukrain, Sep 2012

Mohammed Shayan, Virendra Singh, Adit Singh, and Masahiro Fujita, `SEU tolerant robust memory cell design`, 18^th IEEE International On-Line Testing Symposium (IOLTS) 2012`, Sitges, Spain, June 2012

Jaynarayan Tudu, Deepak Malani, and Virendra Singh, `ILP based approach for input vector controlled toggle maximization in combinational circuits`, 16^th International Symposium on VLSI Design and Test (VDAT) 2012, Kolkata, India, July 2012

Mohammad Shayan, Virendra Singh, Adit Singh, and Masahiro Fujita, `SEU tolerant robust latch design`, 16^th International Symposium on VLSI Design and Test (VDAT) 2012, Kolkata, India, July 2012

Indira Rawat, M.K. Gupta, and Virendra Singh, `Thermal aware test scheduling of 3D SoCs`, 5^th IEEE International Workshop on Impact of Low Power Design on Test and Reliability (LPonTR) 2012, Annecy, France, May 2012

Suraj Sindia, Vishwani D. Agrawal, and Virendra Singh, `Impact of process variation on computers used for image processing`, IEEE International Symposium on Circuits and Systems (ISCAS) 2011, Seoul, Korea, May 2012

Prasanth V., Rubin Parekhji, and Virendra Singh, `Derating based hardware optimizations in soft error tolerant designs`, 30^th IEEE VLSI Test Symposium (VTS) 2012, Hawai, USA, April 2012

Vijay Sheshadri, Prasanth V., Rubin Parekhji, Vishwani D. Agrawal, and Virendra Singh, `Evaluating impact of soft errors in embedded system`, IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) 2012, Hyderabad, India, Jan 2012

Satyadev Ahlawat, Virendra Singh, Shashidhar Bapat, and Karthik Madhugiri, `Low power scan flip-flop design to eliminate output gating overhead for critical paths`, IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) 2012, Hyderabad, India, Jan 2012

Mohammed Shayan, Virendra Singh, Adit Singh, and Masahiro Fujita, `A highly robust and cost effective SEU tolerant memory cell`, IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) 2012, Hyderabad, India, Jan 2012

2011

Pramod Subramanyan, Virendra Singh, Kewal Saluja, and Erik Larsson, `Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors`, 29^th IEEE International Conference on Computer Design (ICCD) 2011, Amherst, MA, USA, October 2011

Mohammed Abdul Razzaq, Virendra Singh, and Adit Singh, `SSTKR: Secure and testable scan design through test key randomization`, 20^th IEEE Asian Test Symposium (ATS) 2011, New Delhi, India, Nov. 2011

Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `Test and diagnosis of analog circuits using moment generating functions`, 20th IEEE Asian Test Symposium (ATS) 2011, New Delhi, India, Nov. 2011

Manas Puthal, Virendra Singh, MS Gaur and Vijay Laxmi, `C-Routing: An adaptive hierarchical NoC routing methodology`, 19^th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2011, Hongkong, China, October 2011

Harsh Gidra, Israrul Haque, Nitin Kumar, M. Sargurunathan, M.S. Gaur, Vijay Laxmi, Mark Zwolinski, and Virendra Singh, `Parallelizing TUNAMI-N1 using GP-GPU`, 13^th IEEE International Conference on High Performance Computing and communication (HPCC) 2011, Banff, Canada, September 2011

Anzhela Matrosova, Virendra Singh, Alexey Melnikov, and Ruslan Mukhamedov, `Selection of state variables for partially enhanced scan`, 9^th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, September 2011

Mohammad Abdul Razzaq, Alok Baluni, Ram Rakesh Jangir, Virendra Singh, and Masahiro Fujita, `On synthesis of degradation aware circuits at higher level of abstraction`, 9^th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, September 2011

Pawan Kumar and Virendra Singh, `Efficient regular expression pattern matching using cascaded automata architecture for network intrusion detection system`, 9^th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, September 2011

V. Prasanth, Virendra Singh, and Rubin Parekhji, `Reduced overhead soft error mitigation methodology using error control coding technique`, 17^th IEEE International On-Line Test Symposium (IOLTS) 2011, Athens, Greece, July 2011

Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Level of confidence evaluation and its usage for roll-back recovery and checkpoint optimization`, Workshop on Dependable and Secure Nanocomputing (WDSN) 2011, Hongkong, China, May 2011

Vinutha Konandur, Virendra Singh, MS Gaur, and Anzhela Matrosova, `Fault Grading at Higher Level of Abstraction`, IEEE International Workshop on Processor Verification, Test and Debug (IWPVTD) 2011, Trondheim, Norway, May 2011

A. Matrosova, S. Ostanin, A. Milnikov, and Virendra Singh, `Using AND-OR tree for path delay faults`,IEEE International Workshop on Processor Verification, Test and Debug (IWPVTD) 2011, Trondheim, Norway, May 2011

Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Study on level of confidence for rollback recovery with check-pointing`, Workshop on Dependability Issues in Deep-submicron Technologies (DDT) 2011, Trondheim, Norway, May 2011

Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `Nonlinear analog circuit test and diagnosisunder process variation using V-transform coefficients`, 29^th IEEE VLSI Test Symposium (VTS), 2011, California, USA, May 2011

Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `Testing linear and non-linear analog circuits using moment generation functions`, 12^th IEEE Latin American Test Workshop (LATW) 2011, Porto de Galinhas, Brazil, March 2011

Chao Han, Adit Singh, and Virendra Singh, `Efficient partial enhanced Scan for high coverage delay testing`, 2011 Joint IEEE International Conference on Industrial Technology and 43^rd Southeastern Symposium on System Theory (ICIT-SSST) 2011, Auburn, USA, March 2011

Suraj Sindia, Vishwani Agrawal, and Virendra Singh, `Distinguishing process variation induced faults from manufacturing defects in analog circuits using V-transform coefficients`, 2011 Joint IEEE International Conference on Industrial Technology and 43^rd Southeastern Symposium on System Theory (ICIT-SSST) 2011, Auburn, USA, March 2011

Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal Saluja, and Masahiro Fujita, `SEU tolerant SRAM cell`, International Symposium on Quality Electronic Design (ISQED) 2011, Santa Clara, CA, USA, March 2011

Naveen Choudhary, M.S. Gaur, Vijay Laxmi, and Virendra Singh, `Traffic aware topology generation methodology for application specific NoC`, IEEE International Symposium on Electronic Design, Test and Application (DELTA) 2011, Queens Town, New Zealand, Jan 2011

Navaneeth Rameshan, Mark Zwolinski, Vijay Laxmi, M.S. Gaur, Virendra Singh, and Lalith P., `Acceleration of functional validation using GPGPU`, IEEE International Symposium on Electronic Design, Test and Application (DELTA) 2011, Queens Town, New Zealand, Jan 2011

2010

[Book Chapter] Dimitar Nikolov, Mikael Vayrynen, Urban Ingelson, Virendra Singh, and Erik Larsson, `Optimizing Fault Tolerance for Multi-Processor System-on-Chip`, Design and Test Technology for Dependable Systems-on-Chip, Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, 2010, Hardcover, ISBN:978-1-6096-0212-3.
Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal Saluja, and Masahiro Fujita, `SEU tolerant SRAM for FPGA application`, International Conference on Field Programmable Technology (FPT) 2010, Beijing, Dec 2010

Amit Mishra, Nidhi Sinha, Satyadev Ahlawat, Virendra Singh, Sreejit Chakravarty, and Adit Singh, `A modified scan flip-flop for test power reduction`, 19^th IEEE Asian Test Symposium (ATS) 2010, Shanghai, China, Dec 2010

Jaynarayan Tudu, Erik Larsson, and Virendra Singh, `Test Scheduling of modular system-on-chip under capture power constraints`, 11^th IEEE Workshop on RTL and High Level Test (WRTLT) 2010, Shanghai, China, Dec 2010

Naveen Choudhary, M.S. Gaur, Vijay Laxmi, and Virendra Singh, `Energy Aware Design Methodologies for Application Specific NoC`, 28^th Norchip Conference (NORCHIP), 2010, Tampere, Finland, Nov 2010

Anzhela Matrosova, Valeriy Lipsky, Aleksey Melnikov, and Virendra Singh, `Path delay faults and ENF`, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep 2010

Vinay N.S, Indira Rawat, Erik Larsson, M.S. Gaur, and Virendra Singh, `Thermal aware test scheduling for stacked multi-chip modules`, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep 2010

K.R. Vinutha, Virendra Singh, Anzhela Matrosova, and M.S. Gaur, `Fault grading using instruction-execution graph`, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep 2010

Adit Kajala, Gayaprasad Sinsinwar, Rahul Choudhary, Jaynarayan Tudu, and Virendra Singh, `On selection of state variables for delay test of identical functional units`, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep 2010

Gayaprasad Sinsinwar, Rahul Choudhary, Aditi kajala, and Virendra Singh, `Test program generation for simultaneous testing of multiple identical functional units`, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersberg, Russia, Sep 2010

Prasanth V., Virendra Singh, and Rubin Parekhji, `Robust detection of soft errors using delayed capture methodology`, IEEE International Online Testing Symposium (IOLTS) 2010, Corfu, Greece, July 2010

Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `Energy ffficient fault tolerance in chip multiprocessors using critical value forwarding`, 40^th IEEE International Conference on Dependable Systems and Networks (DSN), Chicago, IL, USA, June 2010

Abhishek A., Amanulla Khan, Virendra Singh, Kewal Saluja, and Adit Singh, `Test application time minimization for RAS using basis optimization of column decoder`, IEEE International Symposium on Circuits and Systems (ISCAS) 2010
, Paris, France, May 2010
Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Genetic algorithm based topology generation for application specific network-on-chip`, IEEE International Symposium on Circuits and Systems (ISCAS) 2010, Paris, France, May 2010

Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal Saluja, and Adit Singh, `Modified T-FF bases scan cell for RAS`, 15th IEEE European Test Symposium (ETS) 2010, Prague, Czech Rep., May 2010

Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach`, 15^th IEEE European Test Symposium (ETS) 2010, Prague, Czech Rep., May 2010

Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `Power efficient redundant execution for chip multiprocessors`, Great Lake Symposium on VLSI (GLSVLSI) 2010, Providence, Rhode Island, USA May 2010

Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `Graph theoretic approach for scan cell reordering to minimize peak shift power`, 20^th ACM Great Lake Symposium on VLSI (GLSVLSI) 2010, Providence, Rhode Island, USA May 2010

Dimitar Nikolov, Erik Karlsson, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Mapping and scheduling of jobs in homogeneous NoC-based MPSoC`, 10^th Swedish System-on-Chip Conference, Kolma^rden, Sweden, May 2010

Pramod Subramanyam, Virendra Singh, Kewal Saluja, and Erik Larsson, `A low cost redundant execution architectures for Chip multiprocessors`, Design Automation and Test in Europe (DATE) 2010, Dresden, Germany, March 2010

L. Suresh, N. Rameshan, A. Narayan, M. Zwolinski, M.S. Gaur, V. Laxmi, and V. Singh, `EDA design flow acceleration by GP-GPU`, 2^nd Workshop on Designing for embedded parallel computing plateform: Architectures, design tools, and applications (in conjunction with DATE 2010) 2010, Dresden, Germany, March 2010

Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Fast energy aware application specific network-on-chip topology generator`, IEEE International Advanced Computing Conference 2010, Patiala, India, Feb 2010

Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Estimating error probability and its application for optimizing roll-back recovery with checkpointing`, IEEE Symposium on Electronic Design, Test & Applications (DELTA) 2010, Ho Chi Minh , Vietnam, Jan 2010

Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `On-line techniques to adjust and optimize checkpointing frequency`, IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) 2010, Bangalore, India, Jan 2010

Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal Saluja, Hideo Fujiwara, and Adit Singh, `On Minimization of Test Application Time for RAS`, 23^rd International Conference on VLSI Design (ICVD) 2010, Bangalore, Jan 2010

Suraj Sindia, Virendra Singh, and Vishwani D. Agrawal, `Parametric Fault Diagnosis of Nonlinear Analog Circuits using Polynomial Coefficients`, 23^rd International Conference on VLSI Design (ICVD) 2010, Bangalore, Jan 2010

2009

Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Cojoined Irregular Topology and Routing Table Generation for Network-on-Chip`, IEEE INDICON 2009, Gandhi Nagar, India, Dec 2009

Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Designing Application Specific Irregular Topology for Network-on-Chip`, 17^th International Conference on Advanced Computing and Communications (ADCOM) 2009, Bangalore, Dec 2009

Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `Scan Cells Reordering to Minimize Peak Power during Scan Testing of SoC`, IEEE WRTLT 09, Hong Kong, Nov. 2009

Venkat Rajesh, Erik Larsson, MS Gaur, and Virendra Singh, `An Even Odd DFD Technique for Scan Chain Diagnosis`, IEEE WRTLT 09, Hong Kong, Nov. 2009

Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `Multi-tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients`, IEEE Asian Test Symposium (ATS) 2009, Taichung, Taiwan, Nov 2009

Deepak K.G., Robinson Reyna, Virendra Singh, and Adit Singh, `Leveraging Partial Enhanced Scan for Improved Observabilty in Delay Fault Testing`, IEEE Asian Test Symposium (ATS) 2009, Taichung, Taiwan, Nov 2009

Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `V-Transform: An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits`, IEEE East-West Design and Test Symposium (EWDTS) 2009, Moscow, Russia, Sep 2009

Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik Larsson, and Virendra Singh, `Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation`, IEEE East-West Design and Test Symposium (EWDTS) 2009, Moscow, Russia, Sep 2009

Viney Kumar, Rahul Raj, and Virendra Singh, `FREP: A Soft-Error Resilient Pipelined RISC Architecture`, IEEE East-West Design and Test Symposium (EWDTS) 2009, Moscow, Russia, Sep 2009

Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Adit Singh, `Capture Power Reduction for Modular System-on-Chip Test`, IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 2009.
Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing`, IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 2009

Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `Power Efficient Redundant Execution for Chip Multiprocessor`, Workshop on Dependable and Secure Nanocomputing (WDSN) 2009, Lisbon, Portugal, June 2009

Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Vishwani D. Agrawal, `On Minimization of Peak Power during SoC Test`, IEEE European Test Symposium (ETS) 2009, Seville, Spain, May 2009

Suraj Sindia, Virendra Singh, and Vishwani D. Agrawal, `Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits`, 18^th IEEE North Atlantic Test Workshop (NATW) 2009, New York, USA, May 2009

Reshma Jumani, Niraj Jain, Virendra Singh, and Kewal K. Saluja, `DX-Compactor: Distributed X-Compaction for SoC Test`, ACM Annual Great Lake Symposium on VLSI (GLSVLSI) 2009, Boston, USA, May 2009

Suraj Sindia, Virendra Singh, and Vishwani Agrawal, `Coefficient-Based Parametric Testing of Non-Linear Analog Circuits`, ACM Annual Great Lake Symposium on VLSI (GLSVLSI) 2009, Boston, USA, May 2009

Mikael Vayrynen, Virendra Singh, and Erik Larsson, `Fault-Tolerant Average Execution Time Optimization for General Purpose Multi-Processor System-on-Chips`, Intl. Conference on Design Automation and Test in Europe (DATE) 2009, Nice, France, Apr 2009

Vinay NS, Erik Larsson, and Virendra Singh, `Thermal Aware Test Scheduling of Stacked Multi-Chip Modules`, Workshop on 3D Integration (In conjunction with DATE 2009), Nice, France, Apr 2009

Selected Publications (Before 2008)

Virendra Singh and Erik Larsson, `On Reduction of Capture Power for Modular System-on-Chip Test`, 9^th IEEE WRTLT 2008, pp. 35-40, Sapporo, Japan, Nov 2008

Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Instruction-Based Self-Testing of Delay Faults in Pipelined Processors`, IEEE Trans. on VLSI Systems, Vol. 14, No. 11, Nov. 2006, pp. 1203-1215

Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Delay Fault Testing of Processor Cores in Functional Mode`, IEICE Trans. on Information & Systems, Vol. E-88D, No. 3, March 2005, pp. 610-618

Michiko Inoue, Kazuko Kambe, Virendra Singh and Hideo Fujiwara, `Software-Based Self-Test of Processors for Stuck-at Faults and Path Delay Faults`, Trans. of IEICE (DI), Vol. J88-D-I, No. 3, June 2005, pp. 1003-1011

Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Program-Based Testing of Superscalar Microprocessor`, Proceedings of the IEEE 14^th North Atlantic Test Workshop (NATW), May 2005, pp. 79-86, Berlington, VT, USA, May 2005

Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Testing Superscalar Processors in Functional Mode`, Proceedings of the 15^th International Conference on Field Programmable Logic and Applications, Aug. 2005

Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Instruction-Based Delay Fault Self-Testing of Pipelined Processor Cores`, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2005, Kobe, Japan, May 2005

Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Instruction-Based Delay Fault Testing of Processor Cores`, Proceedings of the International Conference on VLSI Design (VLSID) 2004, Mumbai, India Jan. 2004

Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, `Software-Based Delay Fault Testing of Processor Cores`, Proceedings of the IEEE 12^th Asian Test Symposium (ATS) 2003, Xian, China, Nov. 2003