Ongoing Projects

  1. FPGA Based High Power Computing Hardware for 3D Occupancy Map

    2. Investigators: Prof. Sachin Patkar, Prof. Debraj Chakraborty, Mandar Datar

    Sponsored by DRDO.

    Reference Documents

  2. GPGPU based parallelization of Bremics(Bombay Relaxation MOS Integrated Circuit Simulator )

    3. Investigators: Prof. H. Narayanan, Prof. Sachin Patkar, Dr. Gaurav Trivedi, Yogesh Save and Abhijit Joshi.

  3. High Performance Navier-Stokes CFD solver using GPU and Multicore Processors

    4. Investigators: Prof. Sachin Patkar, Prof. Saravanan Vijayakumaran Nishant Shelar and Mandar Gurav.

    Sponsored by VSSC, ISRO.

  4. Approximate solution of combinatorial optimization problems using electrical network analysis

    5. Investigators: Prof. H. Narayanan, Prof. Sachin Patkar, Dr. Gaurav Trivedi and Yogesh Save.

    Sponsored by VLSI Consortium.

    Downloads

  5. Exploration of New Communication Methods for Many-core VLSI Systems

    6. Investigators: Prof. Sachin Patkar and Hrishikesh Sharma.

    Sponsored by Tata Consultancy Services Ltd..

  6. System for Parallel Matrix-vector Computations.

    7. Investigators: Prof. Sachin Patkar and Prof. Shreeniwas Sapre.

    Sponsored by Intel Corp.

  7. High Performance Computing using GPU, FPGA and Multicore Processors.

    8. Investigators: Prof. Sachin Patkar, Prof. Rajbabu Velmurugan, Prof. Saravanan Vijayakumaran and Prof. Dinesh Kumar Sharma

    Sponsored by Naval Research Board, India.

  8. Accelerating performance analysis of Photo-voltaic cell arrays of arbitrary geometry, using two-graph method based circuit simulator.

    9. Investigators: Dr. Gaurav Trivedi, Dr. Mahesh B. Patil, Dr. S. Patkar and Dr. H. Narayanan

  9. Topological Network Transformation based parallel circuit simulator using manycore/multicore processors.

    10. Investigators: Dr. Gaurav Trivedi, Prof. Sachin Patkar and Prof. H. Narayanan

  10. Accelarating accurate nerve conduction analysis, using modified two-graph method

    11. Investigators: Dr. Gaurav Trivedi, Dr. S. Patkar and Dr. H. Narayanan

  11. Development of a ESL-level Synthesis tool for a class of VLSI Systems based on Projective Geometry

    12. Investigators: Prof. Sachin Patkar, Hrishikesh Sharma and Utkarsh Gupta.

    In collaboration with Tata Consultancy Services Ltd..

  12. Prototyping of a Projective Geometry-based On-chip Network for CMP VLSI Systems.

    13. Investigators: Prof. Sachin Patkar, Hrishikesh Sharma and Chiraag Juvekar.

    In collaboration with Tata Consultancy Services Ltd..

Finished Projects

  1. Modified Nodal Analysis(MNA) based circuit simulator using LU decomposition – GPGPU based parallelization of non linear circuit updation with devices having non-linear VI characteristics

    2. Investigators: Prof. H. Narayanan, Prof. Sachin Patkar, Dr. Gaurav Trivedi, Ajay Gopal Kannampallil and Abhijit Joshi.

  2. CUDA Based Acceleration of Haptic Rendering

    3. Investigators: Prof. Subhasis Chaudhuri, Prof. Sachin Patkar, Abhijit Joshi and Mandar Gurav.

  3. High Performance Navier-Stokes CFD solver using GPU and Multicore Processors

    4. Investigators: Dr. Sachin B. Patkar, Dr. Rajbabu Velmurugan, Dr. Saravanan Vijayakumaran, Dr. Gaurav Trivedi and Dr. Praveen Nair

    Consultancy Project with VSSC, Indian Space Research Organization..

  4. Scientific Computation on Graphics Processing Unit using CUDA

    5. Investigators: Prof. Sachin Patkar and Pradip Panchal.

    In collaboration with Computational Research Labs.

  5. A System for Error Control Coding using Expander-like codes and its Applications

    6. Investigators: Prof. Sachin Patkar, Swadesh Choudhary and Hrishikesh Sharma.

    In collaboration with Tata Consultancy Services Ltd..

  6. Accelerating Double Precision Sparse Matrix Vector Multiplication on FPGAs

    7. Investigators: Prof. Sachin Patkar, Sumedh Attarde and Sunil Puranik.

    In collaboration with Computational Research Labs.

  7. Applications of Projective Geometry in Computing and Communications

    8. Investigators: Prof. Sachin Patkar, Abhishek Patil, Dr. B.S. Adiga and Hrishikesh Sharma.

    Sponsored by Tata Consultancy Services Ltd..

  8. FPGA Design for Decoder of Projective Geometry(PG)-based Low Density Parity Check(LDPC) Codes

    9. Investigators: Prof. Sachin Patkar, Hrishikesh Sharma and Nachiket Gajare.

    Sponsored by Tata Consultancy Services Ltd..

  9. FPGA-based High Performance Double-Precision Matrix Multiplication

    10. Investigators: Prof. Sachin Patkar, V.B.Y. Vinay Kumar, Siddharth Joshi and Sunil Puranik.

    In collaboration with Computational Research Labs.

Reports for many of these projects are found in section on Project Reports.