Prof. Supratik
Chakraborty
[1] S. Sunkari, S.
Chakraborty, V. Vedula
and K. Maneparambil, "A
Scalable Symbolic
Simulator for Verilog
RTL", / in Proc.of IEEE
International Workshop
on Microprocessor
Testing and
Verification, December
2007
[2] D. Thomas, S.
Chakraborty and P. K.
Pandya, "Efficient
Guided Symbolic
Reachability using
Reachability
Expressions",/ in
International Journal on
Software Tools for
Technology Transfer,
Vol. 10, No. 2, pp.
113-129, Jan 2008,
Springer
Prof. M.B.Patil
[1]
A. M. Chopde, S.
Khandelwal, R. A.
Thakker, S. S. Mande,
and M. B. Patil,
“Verification of
Parameter Extraction
Stratergy for MOS model
11,” Proc. Int. Conf.
on Trends in
IntelligentElectronic
Systems, pp. 638642,
Nov. 2007.
[2] R. A. Thakker, N.
Gandhi, M. B. Patil, and
K. G. Anil, “Parameter
extraction for PSPMOSFET
model using particle
swarm optimization,” Proc. Int. Workshop Phy.
of Semi. Dev.,pp.
130133,Dec. 2007.
[3] A. M. Chopde, S.
Khandelwal, R. A.
Thakker, M. B. Patil,
and Anil K. G.,
“Parameterextraction for
MOS model 11
using++particle swarm
optimization,” Proc.
Int. Workshop Phy. Of
Semi. Dev., pp.
253256,Dec. 2007.
[4] R. A. Thakker, M. B.
Patil, and K. G. Anil,
“Parameter extraction
for Advanced MOSFET
model using particle
swarmoptimization,” Workshop on Compact
Modeling, NanoTech
2008,Boston, pp.
845848,Vol. 3, June
2008.
[5] V. Hariharan, R. A.
Thakker, J. Vasi, V.
Ramgopal Rao, and M. B.
Patil, “Closed
FormCurrent and
Conductance Model for
Symmetric DoubleGate
MOSFETs using Field
Dependent Mobility,” Workshop on Compact
Modeling, NanoTech
2008,Boston, pp.
857860,Vol. 3, June
2008.
[6] R. A. Thakker, M. B.
Patil, and K. G. Anil,
“Parameter Extraction
for PSP MOSFET
Modelusing Hierarchical
Particle Swarm
Optimization,” International Scientific
Journal of Engineering
Applications of
Artificial Intelligence
Elsevier.
Prof. Madhav.P.
Desai
[1]
"Learning Based Online Optimization of
Address Mapping in Memory Subsystem, Pratyush Kumar,
Madhav P.Desai, MASCOTS 2009, London, September 2009
[2]
"Bottleneck Identification Techniques
leading to Simplified Performance Models for Efficient
Design Space Exploration in VLSI Memory Systems"
G.Hazari, M.P.Desai, G.Srinivas, IEEE International
Conference on VLSI Design, Bangalore, January 2010
Prof Maryam Shojaei Baghini / Prof. D.K.Sharma
[1]. M. Shojaei Baghini,
S. Nag, R. K. Lal and D.
K. Sharma, “An UltraLow-Power
Current-Mode Integrated
CMOS
Instrumentation
Amplifier for Personal
ECG Recorders”, WS J. of
Circuits, Systems, and
Computers, Dec. 2008.
[2]. M. Srivastava, M.
Shojaei Baghini, A. B.
Sachid, D. K. Sharma and
Ramgopal Rao, “A Novel
and Robust Approach for
Common Mode Feedback
using IDDG FinFET”,
IEEE Trans. on Electron
Devices, Nov. 2008.
[3]. A. B. Sachid, R.
Francis, M.Shojaei
Baghini, D.K. Sharma,
Karl-Heinz Bach, R.
Mahnkopf, V. Ramgopal
Rao,
“Sub-20 nm gate length
FinFET design:Can
high-κ spacers make
a difference?” Proc. of
IEEE IEDM 2008, USA.
[4]. A. B. Sachid, M.
Srivastava, R. A.
Thakker, M. Shojaei
Baghini, D. K. Sharma,
M.B.Patil, V. Ramgopal
Rao, “Technology-Aware
Design (TAD) for
Sub-45nm CMOS
Technologies”, Intel AAF
2008, Taiwan (Received
the best research paper
award in circuit design
category) .
[5]. R. A. Thakker, M.
Shojaei Baghini, M. B.
Patil, “Low-Power
Low-Voltage Analog
Circuit Design using
HPSO”, Proc. of IEEE
Int. Conf. on VLSI
Design 2009 (Sister
Conf. of DAC), India.
[6]. M. Dave, M. Shojaei
Baghini and D. K.
Sharma, “Low-power
current-mode receiver
with inductive input
impedance”,Proc. of IEEE
ISLPED 2008, India.
[7]. R. Satkuri, M.
Dave, M. Shojaei Baghini
and D. K. Sharma,
“On-chip Test Circuits
for Fast Interconnects”,
IEEE VDAT 2008, India.
[8] R. A. Thakker, C. Sathe, A. B.
Sachid, M. Shojaei Baghini, V. Ramgopal Rao, M. B. Patil,
“Automated Design and Optimization of Circuits in
Emerging Technologies”, will be presented in IEEE
ASP-DAC 2009 (Sister Conf. of DAC), Japan, 2009.
[9] R. A. Thakker, C. Sathe, A. B.
Sachid, M. Shojaei Baghini, V. Ramgopal Rao, M. B. Patil,
“A Novel Table-based approach for Design of FinFET
Circuits ”, submitted to IEEE Transactions on CAD. Paper
Submit
[10]“A Novel Table–Based Approach for Design
of FinFET Circuits”
R. A. Thakker, C. Sathe, A. B. Sachid, M. Shojaei
Baghini, V. R. Rao, M. B. Patil IEEE Transactions on Computer-aided Design of
Integrated Circuits and Systems, July 2009
[11]
“Automatic
Design of Low-Power
Low-Voltage Analog
Circuits using PSO with
Re-initialization”
R. A. Thakker, M.
Shojaei Baghini, M. B.
Patil Journal of Low-Power
Electronics, Oct.
2009 - Special Issue on
International VLSI
Design Conference 2009.
[12]“Comments
on “Improved Accuracy
Pseudo-Exponential
Function Generator with
Applications in Analog
Signal Processing”“N. V. Karanjkar, R. R.
Sahoo and M. Shojaei
Baghini
accepted for publication
in IEEE Transactions
on VLSI, 2009.
[13]“A
Table-Based Approach to
Study the Impact of
Process Variations on FinFET Circuit
Performance”
R. A. Thakker, C. Sathe,
M. Shojaei Baghini, M.
B. Patil
Accepted for publication
in IEEE Transactions
on Computer-aided Design
of Integrated Circuits
and Systems, 2010.
[14]
“Part I:
Mixed Signal Performance
of Various High Voltage
Drain Extended MOS
Devices”
M. Shrivastava, M.
Shojaei Baghini,
H.Gossner, V. Ramgopal
Rao
Accepted for publication
in IEEE Transactions
on Electron Devices,
2010.
[15]“Part II:
A Novel Scheme to
Optimize the Mixed
Signal Performance and
Hot Carrier Reliability
of Drain Extended MOS
Devices”
M. Shrivastava, M.
Shojaei Baghini,
H.Gossner, V. Ramgopal
Rao
Accepted for publication
in IEEE Transactions
on Electron Devices,
2010.
Prof. Sachin Patkar
[1] "FPGA Based High
Performance
Double-Precision Matrix
Multiplication" Vinay
B.Y. Kumar, Siddharth
Joshi, Sachin B. Patkar,
and H. Narayanan 22nd
International Conference
on VLSI Design,2009, pp
341
[2] "Exploiting Hybrid
Analysis in Solving
Electrical Networks "
V. Siva Sankar, H.
Narayanan, and Sachin
B.Patkar 22nd
International Conference
on VLSI Design,2009, pp
206
[3]
Kumar
V.B.Y; Joshi, S.; Patkar,
S.; Narayanan, H. : FPGA-based
High Performance
Double-Precision Matrix
Multiplication
Exploiting Hybrid
Analysis in Solving
Electrical Networks
(recommended for
publication) in
International Journal of
Parallel Programming,
Springer
[4]
Sankar,
V.S.; Narayanan, H.;
Patkar, S. : Exploiting
Hybrid Analysis in
Solving Electrical
Networks 22nd
International Conference
on VLSI Design, 2009,
5-9 Jan 2009, Page(s):
206-211
[5]Kumar
V.B.Y; Joshi, S.; Patkar,
S.; Narayanan, H. : FPGA-based
High Performance
Double-Precision Matrix Multiplication 22nd
International Conference
on VLSI Design, 2009,
5-9 Jan 2009, Page(s):
341-346
[6]Baviskar,
D; Patkar, S. : A
Pipelined Simulation
Approach for Logic
Emulation Using Multi-FPGA
Platforms IEEE
International Symposium
on Circuits and Systems,
2009, ISCAS 2009, 24-27
May 2009, Page(s):
1141-1144
Prof. H. Narayanan
[1] .Fujishige and
H.Narayanan,
Polyhedrally tight set
functions and
convexity, Pacific
Journal of
Optimization (2008)
139-151.
[2] V. Siva Sankar, H.
Narayanan and Sachin B.
Patkar, "Exploiting
Hybrid Analysis in
solving Electrical
Networks",submitted
to 22nd International
Conference on VLSI
Design, Jan 2009.
[3] H. Narayanan Sachin
Patkar and Yogesh Dilip
Save, "Application of DC
Analyzer to Large
Scale Minimum Cost Flow
Problem", submitted to
22nd
International Conference
on VLSI Design, Jan
2009.
[4] Gaurav Trivedi,
Madhav P. Desai and H.
Narayanan,Parallelization
of DC Analysis through
Multiport
Decomposition,20th
International Conference
on VLSI Design,2007,pp
863-868.
[5] Gaurav Trivedi,
Sumit Punglia and H.
Narayanan, Application
of DC Analyzer to
combinatorial
optimization problems,
20th
InternationalConference
on VLSI Design,2007,pp
869-874.
[6] H. Narayanan,
Mathematical Programming
and Electrical Network
Analysis II:
Computational Linear
Algebra through Network analysis,International
Symposium on
Mathematical
Programming for
Decision Making: Theory
and Applications
(ISMPDM07),ISI Delhi,
January 10-11, 2007.
[7] G.Trivedi and
H.Narayanan, Application
of Fast DC Analysis to
Partitioning
Hypergraphs,ISCAS 2007
3407-3410. papers in
VLSI conference .
[8]S.Fujishige and
H.Narayanan,
Polyhedrally tight set
functionsand convexity,
Pacific Journal of
Optimization (2008)
139-151
Prof. J. Mukherjee
[1]“LOW COST EFFICIENT HIGH
GAIN ANTENNA USING ARRAY
OF PARASITIC PATCHES ON
A SUPERSTRATE LAYER”R. K. Gupta and J.
Mukherjee, Microwave and
Optical Technology
letters, March 2009
[2]
”EFFECT OF
SUPESTRATE MATERIAL ON A
HIGH GAIN ANTENNA USING
ARRAY OF PARASITIC
PATCHES”, R.K Gupta and
J. Mukherjee, Microwave
and Optical Technology
Letters, Jan 2010
[3]”LOW COST
EFFICIENT HIGH GAIN
ANTENNA USING ARRAY OF
PARASITIC PATCHES ON A
SUPERSTRATE LAYER”,R. K.
Gupta and J. Mukherjee,
Microwave and Optical
Technology letters,
March 2009
[4] “27.1GHz CMOS
Distributed Voltage
Controlled Oscillators
With Body Bias for
Frequency Tuning of
1.28GHz”, Kalyan
Bhattacharyya, J.
Mukherjee and M. Shojaei,
MWSCAS 2009, Cancun
Mexico, Aug 2 - 5 2009.
[5] “Phase
Noise Reduction in
Quadrature LC
Oscillators Using
Inverter Based Tail
Noise Shaping”, J.
Mukherjee, M
Shojaei-Baghini, Manoj
Johnson,
NEWCAS-TAISA’09,
Toulouse, France
June-July 2009.
[6]
”20GHz
CMOS Distributed Voltage
Controlled Oscillators
With Frequency Tuning By
MOS Varactors”, Kalyan
Bhattacharyya, Jayanta
Mukherjee, M.
Shojaei-Baghini, 2nd
INTERNATIONAL WORKSHOP
ON ELECTRON DEVICES AND
SEMICONDUCTOR TECHNOLOGY
(IEDST 2009), June 1-2,
2009, Indian Institute
of Technology Bombay,
Mumbai, India.
[7] “CURRENT-MODE CMOS
PIPELINED ADC”, S.R
Krishna R, M
Shojaei-Baghini, J.
Mukherjee, IEEE Eurocon
2009, St Petersburg,
Russia, May 2009
Prof. Shalab. Gupta
[1]D. Solli,
S. Gupta, and B. Jalali,
“Optical phase recovery
in the dispersive
Fourier transform,” to
appear in Applied
Physics Letters,
2009.
[2]S. Gupta
and B. Jalali, “Time
Stretch Enhanced
Recording Oscilloscope,”
Applied Physics
Letters 94,
041105 (2009).
[3]
B. Jalali,
D. Solli, and S. Gupta,
“Silicon Photonics:
Silicon’s time lens,”
Nature Photonics
3, 8-10 (2009).
[4]A.
Motafakker-Fard, S.
Gupta, and B. Jalali,
“Eye Diagram
Measurements and
Equalization with
Real-time Burst
Sampling,” to be
presented at 2010 IEEE
I2MTC Conference,
Austin Texas, May 2010.
[5]J. Yu, X.
Zhou, Y.-K. Huang, S.
Gupta, M.-F. Huang, T.
Wang, P. Magill,
“112.8-Gb/s PM-RZ-64QAM
Optical Signal
Generation and
Transmission on a
12.5GHz WDM Grid,” to
be presented at 2010
IEEE/OSA Optical Fiber
Communication (OFC)
Conference, March
2010.
[6]A.
Motafakker-Fard, S.
Gupta, and B. Jalali,
“Digital Equalization of
Ultrafast Data Using
Real-Time Burst
Sampling,” to be
presented at 2010 IEEE/OSA
Optical Fiber
Communication (OFC)
Conference, March
2010.
[7]S. Gupta,
G. C. Valley, R. H.
Walden, and B. Jalali,
“Power Scaling in
Photonic Time-Stretched
Analog-to-Digital
Converters,” 2009
IEEE Avionics,
Fiber-Optics and
Photonics Conference,
September 2009.
[8]S. Gupta
and B. Jalali, “Impulse
Response of the Photonic
Time-Stretched
Analog-to-Digital
Converter,” 2009 IEEE
Avionics, Fiber-Optics
and Photonics Conference,
September 2009
[9]S. Gupta,
D. Solli, A.
Motafakker-Fard, and B.
Jalali, “Capturing Rogue
Events with the
Time-Stretch Recording
Scope,” 2009 IEEE/OSA
CLEO/Europe - EQEC,
June 2009.
[10]S. Gupta, R. E.
Saperstein, Y.-K. Huang,
P. N. Ji, A. Dogariu,
and T. Wang, “Ultra
High-Speed,
Multi-Wavelength
Polarization Impairment
Characterization
Technique for Pol-Muxed
Optical Links,” 2009
IEEE/OSA Optical Fiber
Communication (OFC)
Conference, March
2009
[11]
A.
Motafakker-Fard, S.
Gupta, and B. Jalali,
“Dynamic Range
Improvement in Photonic
Time-Stretch
Analog-to-Digital
Converter,” 2009
IEEE/OSA Optical Fiber
Communication (OFC)
Conference, March
2009.
[12]
S. Gupta,
“Automatic Analog
Beamforming Transceiver
for 60 GHz Radios,”
E-print archive:
arXiv:0901.2771v1
(2009).
[13]S. Gupta, G. C. Valley,
R. H. Walden, B. Jalali,
“Power Scaling in High
Speed Analog-to-Digital
Converters using
Photonic Time Stretch
Technique,” E-print
archive:
arXiv:0901.2767v1 (2009
