EE-748: Advanced Topics in Computer Architecture

 

Semester: July - Nov 2013

 

Instructor: Virendra Singh

 

Class Timings:

 

Office Hours:

 

Syllabus:

 

Overview Superscalar and VLIW architectures. Limits of instruction level parallelism (ILP). Simultaneous multi-threaded (SMT) architecture, Performance enhancement through branch prediction and value prediction, BulkSMT, Thread level speculation. Run ahead execution, proactive instruction fetch, multi-core architectures, data marshaling for multi-core architectures, power constrained CMPs, heterogeneous core design, Core Fusion, Transactional memories. Performance evaluation of complex microarchitectures. On-chip interconnects (Network-on-Chip). Architectural vulnerabilities and reliable architectures. Patchable design. Secure architectures. Energy efficient architectures. Power management. Cache design, energy efficient cache partitioning, fast thread migration, thread throatling.

 

 

References (Mostly from current literature):

 

  1. JP Shen and MH Lipasti, Modern Processor Design, MC Graw Hill, Crowfordsville, 2005
  2. J.L. Hennessy, and D.A. Patterson, Computer Architecture: A quantitative approach, Fifth Edition, Morgan Kaufman Publication, 2012
  3. Current Literature (Papers from ISCA, Micro, HPCA, ICCD, DSN, and Trans. on Computers)

 

List of representative papers

 

  1. Pejman Lotfi-Kamran et al., `Scale-Out Processors`, Proc. of ISCA 2012
  2. K.V. Craeynest et al., Scheduling Heterogeneous Multi-Cores through Performance Impact Estimation (PIE), Proc. of ISCA 2012
  3. A. Nair et al, `A First-Order Mechanistic Model for Architectural Vulnerability Factor`, Proc. of ISCA 2012
  4. Rami Sheikh et al., `Control-Flow Decoupling `, Proc. of Micro 2012
  5. Andrew Lukefahr et al. `Composite Cores: Pushing Heterogeneity into a Core`, Proc. of Micro 2012
  6. Khubaib et al., `MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP`, 
Proc. of Micro 2012
  7. Akbar Sharifi et al., `Addressing End-to-End Memory Access Latency in NoC-Based Multicores`
, Proc. of Micro 2012
  8. Xuehai Qian et al., `BulkSMT: Designing SMT Processors for Atomic-Block Execution`, Proc. of HPCA 2012
  9. Shekhar Srikantaiah et al., `MorphCache: A Reconfigurable Adaptive Multi-level Cache Hierarchy`, Proc. of HPCA 2011
  10. Michael Ferdman et al., `Proactive Instruction Fetch`, Proc. of Micro 2012
  11. Mark Gebhart et al, `Energy-efficient mechanisms for managing thread context in throughput processors`, Proc. of ISCA 2011
  12. Omid Azizi et al, `Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis`, Proc. of ISCA 2010
  13. M.A. Suleman et al., `Data marshaling for multi-core architectures`, Proc. of ISCA 2010

 

 

Prerequisite: CS-683: Advanced computer architecture/EE-739: Processor Design. Instructor`s consent is mandatory.

 

Evaluation:

 

 

Class Schedule: