EE-709: Testing and Verification of VLSI Circuits


Semester: Jan - Apr 2013


Instructor: Virendra Singh


Class Timings (Tentative): SLOT4 [11:30 am - 12:30 pm (Monday), 8:30 am - 9:30 am (Tuesday), 9:30 am - 10:20 am (Thursday) ]


Office Hours: To be decided




Scope of testing and verification in VLSI design process. Issues in test and verification of complex chips, embedded cores and SOCs.

Fundamentals of VLSI testing. Fault models. Automatic test pattern generation. Design for testability. Scan design. Test interface and boundary scan. System testing and test for SOCs. Iddq testing. Delay fault testing. BIST for testing of logic and memories. Test automation.

Design verification techniques based on simulation, analytical and formal approaches. Functional verification. Timing verification. Formal verification. Basics of equivalence checking and model checking. Hardware emulation.



1.     M. L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing for Digital Memory and Mixed Signal VLSI Circuits, Springer, 2005

2.     H. Fujiwara, Logic Testing and Design for Testability, MIT Press, 1985

3.     M. Abramovici, M. Breuer, and A. Friedman, Digital System Testing and Testable Design, IEEE Press, 1994

4.     M. Huth and M. Ryan, Logic in Computer Science, Cambridge Univ. Press, 2004

5.     T. Kropf, Introduction to Formal Hardware Verification, Springer Verlag, 2000

6.     Current Literature

7.     Class notes


Prerequisite: Knowledge of Digital System Design


Evaluation: Mid term (15%), Final Exam (30%), Course Projects (20%), Assignments (15%), and Continuous Assessment (20%)


Exam Schedule:





Mid Term Exam:

Final Exam:


Assignment 1:


Assignment 2:


Assignment 3:


Assignment 4:


Class Schedule: (For course material access)


Jan 7

Course Introduction

Course Introduction, VLSI design flow, need of test, pre-silicon verification and post-silicon validation, and debug

























































































Selected Readings (Papers):

  1. D. Baik, K. K. Saluja and S. Kajihara, `Random Access Scan: a solution to test power, test data volume and test time`, International Conference on VLSI Design, Jan. 2004
  2. H. Fujiwara, `A new class of sequential circuits with combinational test generation complexity`, IEEE Trans. on Computers, Vol. 49, No. 5, Sep 2000, pp. 895-905
  3. S. Ohtake, T. Masuzawa, and H. Fujiwara, `A non-scan DfT method for controllers to achieve complete fault efficiency`, Proc. of the IEEE Asian Test Symposium (ATS) 1998, pp. 204-211.
  4. T. Iwagaki, S. Ohtake, and H. Fujiwara, `A design methodology to realize delay testable controllers using state transition information`, Proc. of the IEEE European Test Symposium (ETS) 2004, pp. 168-173.
  5. Y. Bonhomme et al., `Power driven chaining of flip-flops in scan architecture`, Proc. of the IEEE International Test Conference (ITC) 2002, pp. 796-803.