EE-739: Processor Design


Semester: Jan - Apr 2013


Instructor: Virendra Singh


Class Timings (Tentative): SLOT1 [8:35 am - 9:30 am (Monday), 9:30 am - 10:30 am (Tuesday), 10:30 am - 11:30 am (Thursday) ]


Office Hours: To be decided


Moodle (Course material access)




CISC Processor Design: Defining microprocessor, hardware flowchart, implementing from flowchart, exception, control store, microcode design.

RISC Processor Design: Building datapath and controller, single cycle implementation, multi cycle implementation, pipelined implementation, exception and hazards handling. (Example: DLX Processor)


Superscalar Processors Design: Superscalar organization, superscalar pipeline overview, VLSI implementation of dynamic pipelines, register renaming, reservation station, re-ordering buffers, branch predictor, and dynamic instruction scheduler etc.; simultaneous multi-threading (SMT) design. (Example: Open SPARC T1)


Memory System Design. Application specific instruction set processor (ASIP) design. Dynamic reconfigurable processors (DRP).

Impact of physical technology, trends in power consumption, low power techniques, low voltage techniques, clock distribution. Verification and test challenges.





  1. Nick Tredennick, Microprocessor Logic Design, Digital Press, 1987
  2. D.A. Patterson and J.L. Hennessy, Computer Organization and Design, Morgan Kaufman Pub., N. Delhi, 2005
  3. JP Shen and MH Lipasti, Modern Processor Design, MC Graw Hill, Crowfordsville, 2005
  4. Mike Johnson, Superscalar Microprocessor Design, Prentice Hall, Englewood Cliffs, NJ, 1991
  5. J.L. Hennessy, and D.A. Patterson, Computer Architecture: A quantitative approach, Fifth Edition, Morgan Kaufman Publication, 2012
  6. A. Chandrakasan and WJ Bowhill, and F. Fox, Design of High Performance Microprocessor Circuits, IEEE Press, 2001
  7. OpenSparc T1 manual,



Prerequisite: Knowledge of Digital System Design


Evaluation: Mid term (15%), Final Exam (30%), Course Projects (20%), Assignments (15%), and Continuous Assessment (20%)


Exam Schedule:





Mid Term Exam:

Final Exam:


Assignment 1:


Assignment 2:


Assignment 3:


Assignment 4:


Class Schedule: (For course material access)


Jan 7

Course Introduction

Introduction to computer systems design and processor architecture/micro-architecture