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Computer Architecture and Dependable Systems Lab

Welcome to CADSL!

CADSL was established in 2012 to conduct research in the area of:

  1. Advance and futuristic architecture and system including compiler and operating system support for architecture
  2. Advanced dependable system including formal verfication and VLSI testing, and
  3. Computer Aided design of VLSI and hardware accelerator.

For detail information on research activity please visit the Research page.

EA-305, Annex Building
Department of Electrical Engineering
Indian Institute of Technology Bombay
Powai, Mumbai, 400076, INDIA
๐Ÿ“ž +91-22-2576-4415
๐Ÿ“งย  cadsl[AT]ee.iitb.ac.in

News

  • Paper titled “Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects” has been accepted in IEEE International Test Conference (ITC2017)
  • Synopsys tools Desing Compiler, TetraMax, VCS, and PrimeTime are up for use

Faculty Members

Prof. Virendra Singh
Ph.D. (NAIST, Japan)

Professor,
Department of Electrical Engineering,
Indian Institute of Technology Bombay
๐Ÿ“ง: viren[AT]ee.iitb.ac.in
Research: Computer Architecture & Dependable Systems
๐ŸŒ: Homepage

Prof. Janak H. Patel

D J Ghandhi Distinguished Visiting Professor,
Department of Electrical Engineering,
Indian Institute of Technology Bombay
๐Ÿ“ง: jhpatel[AT]illinois.edu
Research: Computer Architecture & Dependable Systems

๐ŸŒ:Homepage

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