Computer Architecture and Dependable Systems Lab
Welcome to CADSL!
CADSL was established in 2012 to conduct research in the area of:
- Advance and futuristic architecture and system including compiler and operating system support for architecture
- Advanced dependable system including formal verfication and VLSI testing, and
- Computer Aided design of VLSI and hardware accelerator.
For detail information on research activity please visit the Research page.
EA-305, Annex Building
Department of Electrical Engineering
Indian Institute of Technology Bombay
Powai, Mumbai, 400076, INDIA
๐ +91-22-2576-4415
๐งย cadsl[AT]ee.iitb.ac.in
News
- Paper titled “Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects” has been accepted in IEEE International Test Conference (ITC2017)
- Synopsys tools Desing Compiler, TetraMax, VCS, and PrimeTime are up for use
Faculty Members
![](https://www.ee.iitb.ac.in/~cadsl/wp-content/uploads/2023/01/VirendraSingh-263x300.jpg)
Prof. Virendra Singh
Ph.D. (NAIST, Japan)
Professor,
Department of Electrical Engineering,
Indian Institute of Technology Bombay
๐ง: viren[AT]ee.iitb.ac.in
Research: Computer Architecture & Dependable Systems
๐: Homepage
![](https://www.ee.iitb.ac.in/~cadsl/wp-content/uploads/2023/01/janak-patel.jpg)
Prof. Janak H. Patel
D J Ghandhi Distinguished Visiting Professor,
Department of Electrical Engineering,
Indian Institute of Technology Bombay
๐ง: jhpatel[AT]illinois.edu
Research: Computer Architecture & Dependable Systems
๐:Homepage