1. Mini K. Namboothiripad, Mandar J. Datar, Mukul C. Chandorkar, Sachin B. Patkar, "FPGA Accelerator for Real-Time Emulation of Power Electronic Systems Using Multiport Decomposition”,National Power Electronics Conference - 2019 (NPEC 2019),National Institute of Technology, Tiruchirappalli, 13th – 15th December 2019.
  2. Prathmesh Sawant, Yashwant Kumar, Mandar Datar, Imran Ahmed, Vinayak Shriniwas and Sachin Patkar, "Single Storage Semi-Global Matching for Real Time Depth Processing”,National Conference on Computer Vision, Pattern Recognition, Image Processing and Graphics - 2019 (NCVPRIPG-2019), Hubli, India, 22nd - 24th December 2019
  3. “Case Study in FPGA Based HIL Simulation of Power Electronic Systems”, Mini N., Yash D., Mandar D., Vinay B.Y. Kumar, M. Chandorkar, S. Patkar
  4. Pinalkumar Engineer, Rajbabu Velmurugan, Sachin Patkar, “Scalable implementation of particle filter-based visual object tracking on network-on-chip (NoC)”, Journal of Real-Time Image Processing, Mar. 2019
  5. Mandar J. Datar, Vinay B.Y. Kumar and Sachin Patkar, “Combinatorial Geometry for Petascale Boolean Matrix Vector Multiplication over a Packet-switched Network of FPGAs” , Kiel Symposium on Discrete Algorithms and their Applications in Marine- and Life Sciences – An Indo-German Perspective Kiel University, September 12-14, 2018
  6. Vinay B Y Kumar, Deval Shah, Mandar Datar and Sachin B Patkar, “Lightweight Forth Programmable NoCs” in 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 2018, pp 368-373
  7. H. Narayanan and Sachin B. Patkar, “Matroids”, in Handbook of Graph Theory, Combinatorial Optimization, and Algorithms, Editor-in-Chief K. Thulasiraman, Chapman and Hall/CRC Press, 2016 . pp. 879-922
  8. Sachin B. Patkar and H. Narayanan, “Graph and Hypergraph Partitioning”, Invited Chapter in Handbook of Graph Theory and Algorithms, Editor-in-Chief K. Thulasiraman, Chapman and Hall/CRC Press, 2016, pp. 829-878
  9. Vinay BY Kumar, K Dhiman, M Datar, A Pacharne, H Narayanan and Sachin B Patkar, “Relaxation based circuit simulation acceleration over CPU-FPGA”, 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016 , pp 409-414
  10. Vinay B. Y. Kumar, Pinalkumar Engineer, Mandar Datar, Yatish Turakhia, Saurabh Agarwal, Sanket Diwale and Sachin B. Patkar. “Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies”, in: International Workshop on FPGAs for Software Programmers (FSP 2015), London, UK, September 1 – 4, 2015, arXiv preprint arXiv:1508.06823
  11. Dash S., Bangera V., Kumar V. B. Y., Patkar S. B., Trivedi G : “Power Grid Analysis on Parallel Computing Platforms”, MAREW, Microwave and Radio Electronics Week 2015 25th International Conference Radioelektronika 2015, 14th Conference on Microwave Techniques COMITE 2015, Pardubice, Czech Republic, April, 21 - 23, 2015
  12. Barath Sastha S, Sachin B Patkar and Y. S. Rao : Synthetic Aperture Radar Image Processing by Range Migration Algorithm using Multi-GPUs, GPU Technology Conference, GTC 2015, MARCH 17-20, 2015, SILICON VALLEY
  13. Pinalkumar J. Engineer, Ayan Mishra, Rajbabu Velmurugan, Sachin Patkar : GPU implementation of Particle Filter based Object Tracking, GPU Technology Conference, GTC 2015, MARCH 17-20, 2015, SILICON VALLEY
  14. P Engineer, R Velmurugan, S Patkar : Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video, VLSI Design (VLSID), 2015 28th International Conference on, 35-40, Banglore, 2015, pp. 35-40, 3-7 Jan. 2015
  15. VBY Kumar, S Maity, SB Patkar : Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping, Computer Design (ICCD), 2014 32nd IEEE International Conference on, 464-469, 19-22 Oct. 2014, Seoul, South Korea 2014
  16. V Kumar, VBY Kumar, SB Patkar : FPGA-based implementation of M4RM for matrix multiplication over GF (2), VLSI Design and Test, 18th International Symposium on, 1-2, Banglore, 2014
  17. J Porwal, S Diwale, VBY Kumar, SB Patkar : Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems, VLSI Design, Automation and Test (VLSI-DAT), 2014 (IEEE) International Symposium on , 28-30 April 2014, Hsinchu city, Taiwan
  18. H Sharma, S Sivasubramanian, S Patkar : Optimal communication scheduling for iterative decoding of irregular codes, Communications (NCC), 2014 Twentieth National Conference on, pp. 1-5, Feb. 28 2014-March 2 2014, Kanpur, India, 2014
  19. Jasveer Singh T Jethra, Sachin B Patkar, Shamik Datta: Remote Triggered FPGA based Automated System, 11th International Conference on Remote Engineering and Virtual Instrumentation (REV), 309 - 314, Porto, Portugal, 26-28 Feb. 2014
  20. S Choudhary, H Sharma, S Patkar: Optimal folding of data flow graphs based on finite projective geometry using vector space partitioning, Discrete Mathematics, Algorithms and Applications 5 (04), 2013
  21. Hrishikesh Sharma and Sachin B. Patkar: “A Design Methodology for Optimally Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices”, accepted for publication in Elsevier Journal of Microprocessors and Microsystems 37 (6), 674-683, 2013
  22. Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar, “Solution of PDEs-Electrically Coupled Systems with Electrical Analogy.” Integration, the VLSI Journal 46 (4), 427-440, 2013
  23. Prateek Saxena, Vinay B.Y. Kumar, Dilawar Singh. H Narayanan and Sachin B. Patkar, “Hardware –Software Scalable Architectures for Gaussian Elimination over GF(2) and higher Galois Fields” to appear in Proceedings of PECCS 2013, Barcelona.
  24. Saurabh Agrawal, Debapratim Ghosh, Abhishek Kamath, Kaushlesh Sharma, Sneha Mistry, Madhumita Date, Sachin B. Patkar, and Dinesh Sharma: “An Affordable on-site and Remote Laboratory Solution for a Course in Modern Digital Design”, accepted for publication in IEEE EDUCON, Berlin 13th-17th March 2013.
  25. Yogesh Dilip Save, H.Narayanan, Sachin B. Patkar, “Memory Efficient Implementation of Two Graph based circuits Simulator for PDE-Electrical Analogy”, in proceedings of 26th International Conference on VLSI Design, Pune, India 2013
  26. Sumeet Agrawal, Pinalkumar Engineer, Rajbabu Velmurugan and Sachin B. Patkar, “FPGA Implementation of particle filter based object tracking in video”, 3rd International Symposium on Electronic System Design (ISED), Kolkata, 19th-22nd December 2012.
  27. Samir Shelke, Madhumita Date, Sachin B. Patkar, Rajbabu Velmurugan, and Preeti Rao, “A Remote Lab For Real-Time Digital Signal Processing”, EDERC2012: 5th European DSP Education and Research Conference, 13- 14 September 2012, Amsterdam, Netherlands
  28. Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar, “Two Graph based cicuitsimulator for PDE –Electrical Analogy”, 25thIntl. in proceedings of International Conference on VLSI Design, 2012
  29. Yogesh Dilip Save, H. Narayanan and Sachin B. Patkar, “Solution of Partial Differential Equations by electrical analogy”, (Elsevier) Journal of Computational Science 2 (2011) 18–30
  30. Hrishikesh Sharma, Subhasis Das, Rewati Raman Raut and Sachin Patkar, "High-throughput Memory-efficient VLSI Designs for Structured LDPC decoding”, PECCS-2011 (Pervasive and Embedded Computing and Communications Systems - 2011)
  31. Subhasis Das and Sachin Patkar, "A Compact Gaussian Random Number Generator for Small Word Lengths”, Applied Reconfigurable Computing - 2011 (ARC-2011), Belfast, Ireland, 23-25 March 2011
  32. Sumedh Attarde, Siddharth Joshi, Yash Deshpande, Sunil Puranik and Sachin Patkar, "Double Precision Sparse Matrix Vector Multiplication Accelerator on FPGA”, PECCS-2011 (Pervasive and Embedded Computing and Communications Systems - 2011)
  33. Balwinder Kumar, Yogesh Dilip Save, H. Narayanan and Sachin B. Patkar, "A Simple Relaxation Based Circuit Simulator for VLSI Circuits with Emerging Devices", CSC(International Conference on Scientific Computing), 2011.
  34. Swadesh Choudhary, Tejas Hiremani, Hrishikesh Sharma and Sachin Patkar, "A Folding Strategy for DFGs derived from Projective Geometry based graphs”, The 2010 International Congress on Computer Applications and Computational Science (CACS 2010), Singapore, Dec 4-6, 2010
  35. Subhendu Roy, Yogesh Dilip Save, H. Narayanan and Sachin B. Patkar, "Large Scale VLSI Circuit Simulation Using Point Relaxation”, CSC, 2010 (The 2010 International Conference on Scientific Computing), July 12-15, USA, 2010
  36. A. Maringanti, V. Athavale, and S. Patkar, "Acceleration of the conjugate gradient method for circuit simulation using CUDA,” in Proc. 16th International Conference on High Performance Computing, 2009.
  37. D. Baviskar and S. Patkar, "A Pipelined Simulation Approach for Logic Emulation Systems,” in Proc. IEEE International Symposium on Circuits and Systems, 2009, pp. 1141-1144.
  38. V.B.Y Kumar, S. Joshi, S. Patkar and H. Narayanan, "FPGA-based High Performance Double- Precision Matrix Multiplication,” in Proc. 22nd Int. Conference on VLSI Design, 2009, pp. 341-346.
  39. V.S. Sankar, S. Patkar, and H. Narayanan, "Exploiting Hybrid Analysis in Solving Electrical Networks,” in Proc. 22nd International Conference on VLSI Design, 2009, pp. 206-211.
  40. J. Porwal and S. B. Patkar, "Algorithms for scheduling of data transfer across FPGAs in a grid,” in Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005.