- System for Parallel Matrix-vector Multiplication, Indian Patent Requested (2011), 2104/MUM/2011. Shreeniwas Sapre(IITB) and Dr. B. S. Adiga(TCS/IITB).
- System for Error Control Coding using Expander-like codes constructed from higher dimensional Projective Spaces, and their Applications, Indian Patent Requested (2010), 2455/MUM/2010. B. S. Adiga, H. Sharma(TCS) and S. Chowdhary, S. Patkar(IITB).
- A system and method for emulating a logic circuit design using programmable logic devices”, Patent Application No. 211/MUM/2005, Published 2005-06-04, Filed 2005-02-05, United States Patent Application Pub. No. US 2006/0247909 A1 , Pub. Date Nov. 2, 2006. Madhav P. Desai, and Sachin B. Patkar(IITB) and Himanshu Sharma, Mitra Purandare(Powai Labs).
- A method and system to accelarate performance analysis of Photo-voltaic cell arrays of arbitrary geometry, using two-graph method based circuit simulator. To be applied for patent, by Dr. Gaurav Trivedi, Dr. Mahesh B. Patil, Dr. S. Patkar and Dr. H. Narayanan
- A method and system to accelarate accurate nerve conduction analysis, using modified two-graph method. To be applied for patent, Dr. Gaurav Trivedi, Yogesh Dilip Save, Dr. S. Patkar and Dr. H. Narayanan