Virendra Singh, Ph.D(NAIST, Japan)
PROFESSOR
Department of Electrical Engineering, and
Department of
Computer Science & Engineering
Indian Institute of Technology Bombay
Powai, Mumbai 400076 India
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E-mail : |
viren@ee.iitb.ac.in, viren@cse.iitb.ac.in singhv@iitb.ac.in,
virendra@computer.org |
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Tel : |
+91-22-2576-9432 (O) |
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+91-22-2576-8432 (R) |
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Fax : |
+91-22-2572-3707 |
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Office : |
122 D, EE Building |
________________________________________________________________________________________________________
Publications .
Teaching . Funding . Professional
Activities . Students
. Visitors . RASDAT . IWPVTD . WHF
_____________________________________________________________________________________________________
Research Lab.: Computer
Architecture and Dependable Systems Lab. (CADSL)
Coordinator: Indo-Japanese Joint Laboratory for
Intelligent Dependable Cyber Physical Systems (IDCPS)
Coordinator (PI): Information Security Research and Development Centre
(ISRDC)
Associated Lab: Gigabit
Networking Lab. (GNL), CSE
Associated Lab: Centre of excellence for
Blockchain research
Affiliation: Centre for Machine Intelligence and Data
Science
New:
Requirements: PDFs, Ph.D Aspirants,
Project Associates/Assistants (experience in Cyber Security)
New Project: AI powered adaptive cyber defence
framework (sponsored by NSCS, GoI)
Announcements:
Funding: DST-JST
funding, DRDO funding, SRC funding, NSCS funding
Papers: ISCAS`21 paper
Conferences: VDAT`22, ITC-India`22, RASDAT`22, ICISS-21
Received SP Sukhatme excellence in teaching award in 2021
Courses: [Next Semester-
Spring 2022]: CS-654: Current Topics in VLSI & System Design, EE-739: Processor Design,
EE-309: Microprocessors, CS-226: Digital Logic &
Computer Architecture
[Last Semester- Autumn
2021]: EE-748:
Advanced Topics in Computer Architecture, CS-683: Advanced
Computer Architecture, EE-677: Foundation of VLSI
CAD
Debates at EE-748: End to VN
Architecture, Is
Microarchitecture dead ?
_____________________________________________________________________________________________________
Research Interest:
- Cyber security
- Computer architecture
- Processor architecture &
micro-architecture
- Memory system design
- Reconfigurable computing
- Adaptive
computing/architectures
- Compiler support for modern
architectures
- Fault-tolerant computing
- Robust design and architectures
- Self-healing system design
- VLSI testing and design for
testability
- SoC/NoC design and test
- Post silicon debug
- High level synthesis
- Formal verification
- Trusted computing
- FPGA based acceleration
- Trusted hardware design
- Cyber physical systems
- Network router design and
algorithms
- Software defined networking
(SDN)
- Blockchain Technology
Education:
- Ph.D (Computer Science) - (2002-2005)
Nara Institute of
Science and Technology (NAIST)
Kansai Science City, Nara, Japan
Advisor: Prof. Hideo Fujiwara
Co-Advisors: Prof. Kewal K.
Saluja (Univ. of Wisconsin-Madison, USA)
and Prof. Michiko Inoue (NAIST)
Thesis: Instruction-Based Self-Testing of
Performance Oriented Faults in Modern Processors
- M.E
(Electronics & Communication) - (1994-1996)
Malaviya National
Institute of Technology (MNIT)
Jaipur (Rajasthan) India
Advisor: Prof.
MS Gaur
Thesis:
Simulation of ATM Networks with Heavy Tail Traffic Distribution
- B.E (Hons)
in Electronics & Communication - (1990-1994)
Malaviya National
Institute of Technology (MNIT)
Jaipur (Rajasthan)
Professional Experience:
- Faculty
member, Indian Institute of Technology
Bombay (Since Dec 2011)
- Faculty
member, SERC (presently CDS dept.), Indian Institute of Science (IISc),
Bangalore (May 2007 - Dec 2011)
- Scientist,
Central Electronics Engg.
Research Institute (CEERI), Pilani (Mar 1997 - May 2007)
- Faculty
member, Banasthali University (Jun 1996 - Mar
1997)
Current Major Research Projects:
AI Powered
Adaptive Cyber Defence Framework (2021 – 2023)
Sponsor: National Security Council Secretariat (NSCS),
Govt. of India, Funding: USD 16M (INR 1.2 Arab)
Architecting
Intelligent Dependable Cyber Physical System Targeting IoTs and Mobile Big Data
Analysis (2017-2022)
Sponsor: JST & DST, Funding: INR 12.5 Crores
(IITB: INR 5.1 Crores, and Tokyo Univ.: Yen 14.8 Crores)
Analyzing vulnerabilities in applications and device
drivers in Linux and Windows OS platforms using symbolic execution
(with IIT Jammu and MNIT Jaipur)
Trustable Cyber Physical Cognitive System
(with Tokyo University, Japan)
Publications: List of my
publications
Recent
Publications:
Papers
in 2025
·
Pinaki
Das, Virendra Singh, Pushpak Bhattacharyya, and Gholamreza Haffari, `Video-guided
multimodal machine translation: A survey of models, Datasets, and challenges`, International Joint Conference on Natural
Language Processing and Asia Pacific Chapter of the Association of
Computational Linguistics (IJCNLP-AACL), Mumbai, India, Dec 20-25, 2025.
·
Anuj
Kumar, Satyadev Ahlawat, Yamuna Prasad, and Virendra Singh, `LRMGS: A language robust metric for evaluating
question answering in very low resource Indic languages`, International Joint Conference on Natural
Language Processing & Asia-Pacific Chapter of the Association for
Computational Linguistic (IJCNLP-AACL) 2025, Mumbai, India, Dec 20-24, 2025
·
Rohit
Badjatya, Kapil Sharma, Makoto Ikeda, Masahiro Fujita and Virendra Singh, `Weight-Aware Scan Chain Stitching for Shift
Power Minimization under Routing Constraints`,
34th IEEE Asian Test Symposium (ATS 2025), Tokyo, Japan, Dec 16-19, 2025.
·
Hasmita
Kurre and Virendra Singh, `ME-XHRL: Malware
Evasion using Explainable Hierarchical Reinforcement Learning`, International Conference on Artificial
Intelligence Computing and Systems (AICompS 2025),
Fukuoka, Japan, November 26-28, 2025
·
Avinash
Kumar, Virendra Singh, and Supratim Biswas, `Characterizing
irregular memory accesses for better prediction prefetching`, 23rd Asian Symposium on Programming
Languages and Systems (APLAS 2025), Mumbai, India, October 27-30, 2025. (Poster
presentation).
·
Samiksha
Verma and Virendra Singh, `TRAP: Time-aware
probabilistic In-DRAM Row Hammer solution`,
37th IEEE/SBC International Symposium on Computer Architecture and High
Performance Computing (SBAC-PAD 2025), Bonito, MS, Brazil, October 28-31, 2025.
·
Varun
Venkitaraman, Tejeshwar Thorawade, Mitul Tandon, Keerthisagar
Kokkiligadda, Virendra Singh and Janak Patel, `LiC: Low-Cost Cache
Replacement Algorithm for All Cache Levels`,
33rd IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC 2025), Puerto Varas, Chile, October 12-15, 2025.
·
Jaidev
Shenoy, Kelly Ockunzzi and Virendra Singh, `Tester
time savings for LBIST diagnostics using enhanced version of On-chip MISR
signature comparison with self-test and bypass`, International Test Symposium India
(ITC-India) 2025, Bangalore 20-22, 2025.
·
Raghunandana
K, Yogesh Prasad R, Matteo Sonza Reorda, and Virendra Singh, `GPD: Predictive
control flow error detection leveraging data flow error detection methods`,
Proc. of 31st International Symposium on Online Testing and Robust System
Design (IOLTS-25), Ischia, Italy, July, 2025.
·
Rushikesh Kawale,
Sonali Shukla, Makoto Ikeda, Masahiro Fujita and Virendra Singh, `HiPeR-SM: High Performance Reconfigurable Scalar Multiplier
over NIST-P256 and CURVE25519`, 34th International Workshop on Logic
& Synthesis (IWLS 2025), Verona, Italy, June, 2025.
·
Varun
Venkitaraman, Rishabh Ravi, Tejeshwar Thorawade,
Nirmal Boran, and Virendra Singh, `SCAM: Secure shared cache partitioning to
enhance throughput of CMPs`, Proc. of 22nd International Conference on Security
and Cryptography (SECRYPT 2025), Bilboa, Spain, June, 2025
·
Nikhil
Kumar Parida, Sarath Babu, Neeraj Pawar, and Virendra Singh, `EDQKD:
Enhanced-Dynamic Quantum Key Distributions with Improved Security and key
rate`, Proc. of 22nd International Conference on Security and Cryptography
(SECRYPT 2025), Bilboa, Spain, June, 2025
·
Rushikesh
Kawale, Sarath Babu, and Virendra Singh, `Stegoslayer: A robust browser
integrated approach for Thwarting Stegomalware`,
Proc. of 22nd International Conference on Security and Cryptography (SECRYPT
2025), Bilboa, Spain, June, 2025
- Varun Venkitaraman, Shrasti Bhargava, Tejeshwar Bhagatsing
Thorawade, Keerthisagar Kokkiligadda,
Rahul Kumar, Virendra Singh, `RRR: Robust Runtime Reconfigurable Shared
Cache Management Scheme for GPGPUs`, Proc. of 58th IEEE International
Symposium on Circuits and Systems 2025 (ISCAS 2025), London, UK, May 2025.
·
Anjum
Riaz, Gaurav Kumar, Yamuna Prasad, Satyadev Ahlawat, and Virendra Singh, `A New
Hardware Trojan Attack on Scan-obfuscated Logic-locked Circuits`, Proc. of 58th
IEEE International Symposium on Circuits and Systems 2025 (ISCAS 2025), London,
UK, May 2025.
- Yogesh Gholap, Prajakta Yeola, Virendra Singh, `On Developing a Hybrid
Cyber-Physical Testbed for Cyber-Secure Industrial Control System`, Proc.
of IEEE Latin American Conference on Internet of Things (LatinIoT-2025), Forateza, Brazil, April 2025
·
Prakhar
Diwan, Nirmal Kumar Boran, and Virendra Singh, `Li-chen:
Leveraging Coupled Heterogeneity`, Proc. of 38th International Conference on
VLSI Design (VLSID-2025), Bangalore, India, Jan 2025
·
Aditi
Gupta, Adeiza James Onumanyi, Satyadev Ahlawat,
Yamuna Prasad, and Virendra Singh, `B-CAVE: A robust online time series change
point detection algorithm based on between-class average and variance
evaluation approach`, IEEE Trans. on Knowledge and Data Engineering (TKDE),
vol. 37, no. 1, Jan 2025
Selected Publications
(Before 2025):
·
Suma
Sri Mandru, Srikanth Yadav Chakka, Tikaram Sanyasi, and Virendra Singh, `MALAI:
ML-based attack on learning with error (LWE) problem`, Proc. of 20th
International Conference on Information Systems Security (ICISS 2024), Jaipur,
India, Dec 2024
·
Tarun
Bisht, Sarath Babu, and Virendra Singh, `Critical behaviour sequence monitoring
for early malware detection`, Proc. of 17th International Conference on
Security of Information Networks (SINConf-2024), Sydney, Australia, Dec 2024
·
Tejeshwar
Thorawade, Prajakta Yeola, Varun Venkitaraman, and Virendra Singh, `S-Cflush: Securing against flush-based cache timing side
channel attacks`, Proc. of 36th IEEE International Symposium on
Computer Architecture and High Performance Computing (SBAC-PAD 2024), Hawaii,
USA, Nov 2024
·
Samiksha
Verma, and Virendra Singh, `SMS: Solving many RowHammer`,
Proc. of 11th International Symposium on Memory Systems (MEMSYS-24), Washington
DC, Oct 2024
·
Tikaram
Sanyasi, Nirmal Kumar Boran, and Virendra Singh, `Secure KNN Computation on
Cloud`, Proc. of 19th International Conference on Information Systems Security
(ICISS 2023), Raipur, India, Dec 2024
·
Neha
Hooda and Virendra Singh, “Brutector: A probabilistic
detection model for Bruteforce attacks in SSH
servers”, Proc. of 16th International Conference on Security of Information
Networks (SINConf-2023), Jaipur, India, Dec 2023
·
Varun
Venkitaraman, Ashok Sathyan, Shrihari Deshmukh, and Virendra Singh, “Novel
efficient synonym handling mechanism for virtual real cache hierarchy”, Proc.
of IEEE Design Automation and Test in Europe (DATE’23), Antwerp, Belgium, April
2023
·
Ashwin
Lele, Srivastava Jandhyala, Saurabh Gangurde, Virendra Singh, Srinivas
Subramoney, and Udayan Ganguly, `Disrupting low-write energy vs fast-read
dilemma in RRAM to enable L1 instruction cache`, 26th International Symposium
on VLSI Design and Test (VDAT’22), Jammu, India, July 2022.
- Jaynarayan Tudu,
Satyadev Ahlawat, Sonali Shukla, and Virendra Singh, `A framework for
configurable for joint-scan design-for-test architecture`, Journal of
Electronic Testing: Theory and Application, 2021
- Arindam Sarkar, Newton Singh,
Varun Venkitaraman, and Virendra Singh, `DAM:
Deadlock aware migration techniques for STT-RAM based hybrid caches`, IEEE
Computer Architecture Lettres (CAL), 20(1), 2021
- Nirmal
Kumar Boran, Shubhankit Rathore, Meet Udeshi,
and Virendra Singh, `Fine-grained scheduling in heterogeneous-ISA
architectures`, IEEE Computer Architecture Letters (CAL), 20(1), 2021
- Antara Ganguly, Shankar
Balachandran, Anant Nori, Virendra Singh, and Sreenivas Subramoney, `Characterization of data generating
neural network application on x86 server architecture`, Proc. of IEEE
International Symposium on Performance Analysis of Systems and Software
(ISPASS), Boston, USA, April 2020
- Jiji Angel and Virendra Singh,
`On the DSA key recovery attack with variable partial nonces known`, ISEA
International Conference on Security and Privacy (ISEA-ISAP), Guwahati,
India, Feb 2020
- Binod Kumar, Swapaniel Thakur, Kanad Basu, Masahiro Fujita, and
Virendra Singh, `A low overhead methodology for validating memory
consistency models in chip multiprocessors`, 33rd International
Conference on VLSI Design (VLSID-2020), Bangalore, India, Jan 2020
- Rajkumar Choudhary, Newton
Singh, Harideep Nair, Rishabh Rawat, and Virendra Singh, `Free-flow Core:
Enhancing performance of in-order cores with energy efficiency`, 37th
IEEE International Conference on Computer Design (ICCD-2019), Abu Dhabi,
UAE, Nov 2019
- Binod
Kumar, Masahiro Fujita and Virendra Singh, "A Methodology for
SAT-based Electrical Error Debugging during Post-silicon Validation",
32nd International Conference on VLSI Design (VLSID-19) 2019, Delhi,
Jan 2019
- Jaidev
Shenoy, Virendra Singh, Kelly Ockunzzi and
Kushal Kamal, "On-chip MISR compaction technique to reduce diagnostic
effort and test time", 32nd International Conference on VLSI
Design (VLSID-19) 2019, Delhi, Jan 2019
- Antara
Ganguly, Virendra Singh, Rajiv Muralidhar, and Masahiro Fujita,
"Memory system requirements for convolutional neural networks",
International Symposium on Memory Systems (MEMSYS-2018), Washington DC,
USA, October 2018
- Suhit
Pai, Newton, and Virendra Singh, "AB-Aware: Application Behavior
Aware Management of Shared Last Level Caches", 28th
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2018, Chicago,
Illinois, USA, May 23-25, 2018
- Darshit
Vaghani, Satyadev Ahlawat, Jaynarayan Tudu,
Masahiro Fujita, and Virendra Singh, "On Securing Scan Design
Through Test Vector Encryption", 51st IEEE
International Symposium on Circuits and Systems (ISCAS) 2018,
Florence, Italy, May 2018
- Rohini
Gulve and Virendra Singh, "ATPG Power Guards: On limiting the test
power below threshold", Proc. of Design Automation and Test in
Europe (DATE), Dresden, Germany, March 2018
- Ankush
Srivastava, Virendra Singh, Adit Singh, and Kewal Saluja, "A reliability aware methodology to
isolate timing critical paths under aging", Journal of
Electronic Testing: Theory and Application (JETTA), Vol. 34, No. 1, Feb 2018
- Newton, Sujit Mahto, Suhit Pai, and Virendra Singh, "DAAIP: Deadblock Aware
Adaptive Insertion Policy for High Performance Caching", 35th
International Conference on Computer Design (ICCD), Boston, MA, USA, November 2017
- Shoba
Gopalkrishnan and Virendra Singh, `REMORA:
A hybrid low-cost soft-error reliable fault tolerant architecture`,
30th IEEE International Symposium on Defect and Fault Tolerance
in VLSI and Nanotechnology Systems (DFT), Cambridge, UK, October
2017
- Binod
Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, and Virendra Singh, `Improving post-silicon error detection
with topological selection of trace signals`, 25th
IEEE/IFIP International Conference on Very Large Scale Integration (VLSI-SoC),
Abu Dhabi, UAE, October 2017
- Ankush
Srivastava, Adit Singh, Virendra Singh, and Kewal K. Saluja, `Exploiting path delay test generation
to develop better TDF tests for small delay defects`, 48th
IEEE International Test Conference (ITC), Texas, USA, November 2017
- Abhishek Rajgadia,
Newton Singh, and Virendra Singh, `EEAL: Processors performance
enhancement through early execution of aliased loads`, 27th ACM
Great Lakes Symposium on VLSI (GLSVLSI),
Alberta, Canada, May 2017
- Nihar Hage, Rohini Gulve, Masahiro Fujita, and Virendra Singh,
`Instruction-based self-test for delay faults maximizing operating
temperature`, 23rd IEEE International Symposium on On-Line
Testing and Robust System Design (IOLTS),
Thessaloniko, Greece, July 2017
- Satyadev Ahlawat, Darshit
Vaghani, and Virendra Singh, `An efficient test technique to prevent
scan-based side-channel attacks`, 22nd IEEE European test
Symposium (ETS), Limassol,
Cyprus, May 2017
- Toral Shah, Anzhela Matrosova,
Binod Kumar, Masahiro Fujita and Virendra Singh, `Testing Multiple
Stuck-at Faults of ROBDD Based Combinational Circuit Design`, 18th IEEE
Latin American Test Symposium (LATS), Bogota, Colombia, March 2017
- Nihar Hage, Rohini Gulve, Masahiro Fujita, and Virendra Singh, `On
testing of superscalar processors in functional mode for delay faults`, 30th
International conference on VLSI Design (VLSID), Hyderabad, Jan 2017
- Nirmal Kumar Boran, Rameshwar Prasad Meghwal, Kuldeep Sharma, Binod
Kumar, and Virendra Singh, ` Performance modelling of heterogeneous ISA
multicore architecture`, 14th IEEE
East-West Design and Test Symposium (EWDTS)
2016, Yerevan, Armenia, Oct 2016
- Shoba Gopalakrishnan and
Virendra Singh, `REMO: Redundant execution with minimum area, power,
performance overhead fault tolerant architecture`, 22nd IEEE
International Symposium on Online Testing and Robust System Design (IOLTS) 2016, Catalunya, Spain,
July 2016
- Satyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova,
and Virendra Singh, `A high performance scan flip-flop design for serial
and mixed mode scan test` 22nd IEEE International Symposium on
Online Testing and Robust System Design (IOLTS) 2016, Catalunya, Spain, July 2016
- Parth Lathigara,
Shankar Balachandran, and Virendra Singh, `Application behavior aware
re-reference interval prediction for LLC`, 33rd IEEE
International Conference on Computer Design (ICCD) 2015, New York, USA, Oct 2015
- Ankush Srivastava, Virendra
Singh, Adit Singh, and Kewal Saluja, `A methodology for identifying high
timing variability paths in complex designs`, 24th IEEE Asian
Test Symposium (ATS) 2015,
Mumbai, India, Nov 2015
- Satyadev Ahlawat, Jaynarayan Tudu, Virendra Singh, and Anzhela Matrosova, `A new scan flip flop design to eliminate
performance penalty of scan`, 24th IEEE Asian Test Symposium (ATS) 2015, Mumbai, India, Nov 2015
- Adithyalal P.M,
Shankar Balachandran, and Virendra Singh, `A soft error resilient low
leakage SRAM cell design`, 24th IEEE Asian Test Symposium (ATS) 2015, Mumbai, India, Nov 2015
- Toral Shah, Anzhela Matrosova, and Virendra Singh, `PDF testability of a
combinational circuit derived by covering ROBDD nodes by Invert-And-Or graph,` 19th International Symposium on VLSI
Design and Test (VDAT) 2015,
Ahmedabad, India, May 2015
- D. Nikolov, U. Ingelsson, V.
Singh, and E. Larsson, `Evaluation of level of confidence and optimization
of roll-back recovery with check pointing for real time systems`,
Microelectronics Reliability, vol 54, 2014, pp. 1022-1049.
- Lokesh Siddhu, Amit Mishra, and
Virendra Singh, `Operand isolation circuit with reduced overhead for datapath design`, 27th International
Conference on VLSI Design (VLSID)
2014, Mumbai, India, Jan 2014
- Anzhela Matrosova,
Evgenii Mitrofanov, and Virendra Singh, `Delay testable sequential circuit
design`, 11th IEEE East-West Design and Test Symposium (EWDTS), Rostov, Russia, Aug 2013
- Suraj Sindia, Vishwani D.
Agrawal, and Virendra Singh, `Parametric fault testing of non-linear
analog circuits based on polynomial and v-transform coefficients`, Journal
of Electronic Testing: Theory and Applications (JETTA), Vol. 28, No. 5, pp. 557-571, 2012
- Suraj Sindia, Vishwani D.
Agrawal, and Virendra Singh, `Defect level and fault coverage in
coefficient based analog circuit testing`, Journal of Electronic Testing:
Theory and Applications (JETTA),
Vol. 28, No. 4, pp. 541-549, 2012
- Pawan Kumar, and Virendra
Singh, `Efficient regular expression pattern matching for network
intrusion detection system using modified word based automata`, 5th
ACM International Conference on Security of Information and Networks (SIN) 2012, Jaipur, India, Oct 2012
- Indira Rawat, M.K. Gupta, and
Virendra Singh, `Scheduling test for 3D SOCs with temperature
constraints`, 10th IEEE International East West Design and Test
Symposium (EWDTS) 2012,
Kharkov, Ukrain, Sep 2012
- A. Matrosova,
E. Nikolaeva, D. Kudin, and V. Singh, `PDF testability of circuits derived
by special covering ROBDDs with gates`, 10th IEEE International
East West Design and Test Symposium (EWDTS)
2012, Kharkov, Ukrain, Sep 2012
- A. Matrosova,
S. Ostanin, A. Melnikov, and V. Singh,
`Observability calculations of variables oriented to robust PDFs and LOC
or LOS techniques`, 10th IEEE International East West Design
and Test Symposium (EWDTS)
2012, Kharkov, Ukrain, Sep 2012
- Mohammed Shayan, Virendra
Singh, Adit Singh, and Masahiro Fujita, `SEU tolerant robust memory cell
design`, 18th IEEE International On-Line Testing Symposium (IOLTS) 2012`, Sitges, Spain, June
2012
- Jaynarayan Tudu,
Deepak Malani, and Virendra Singh, `ILP based approach for input vector
controlled toggle maximization in combinational circuits`, 16th
International Symposium on VLSI Design and Test (VDAT) 2012, Kolkata, India, July 2012
- Mohammad Shayan, Virendra
Singh, Adit Singh, and Masahiro Fujita, `SEU tolerant robust latch
design`, 16th International Symposium on VLSI Design and Test (VDAT) 2012, Kolkata, India, July
2012
- Suraj Sindia, Vishwani D.
Agrawal, and Virendra Singh, `Impact of process variation on computers
used for image processing`, IEEE International Symposium on Circuits and
Systems (ISCAS) 2012, Seoul,
Korea, May 2012
- Prasanth
V., Rubin Parekhji, and Virendra Singh,
`Derating based hardware optimizations in soft error tolerant designs`, 30th
IEEE VLSI Test Symposium (VTS)
2012, Hawai, USA, April 2012.
- Vijay
Sheshadri, Prasanth V., Rubin Parekhji, Vishwani
D. Agrawal, and Virendra Singh, `Evaluating impact of soft errors in
embedded system`, IEEE International Workshop on Reliability Aware System
Design and Test (RASDAT) 2012, Hyderabad, India, Jan 2012.
- Pramod Subramanyan, Virendra
Singh, Kewal Saluja, and Erik Larsson, `Adaptive execution assistance for
multiplexed fault-tolerant chip multiprocessors`, 29th IEEE
International Conference on Computer Design (ICCD) 2011, Amherst, MA, USA, October 2011
- Mohammed Abdul Razzaq, Virendra
Singh, and Adit Singh, `SSTKR: Secure and testable scan design through
test key randomization`, 20th IEEE Asian Test Symposium (ATS) 2011, New Delhi, India, Nov.
2011
- Suraj Sindia, Vishwani Agrawal,
and Virendra Singh, `Test and diagnosis of analog circuits using moment
generating functions`, 20th IEEE Asian Test Symposium (ATS) 2011, New Delhi, India, Nov.
2011
- Manas Puthal,
Virendra Singh, MS Gaur and Vijay Laxmi, `C-Routing: An adaptive
hierarchical NoC routing methodology`, 19th IFIP/IEEE
International Conference on Very Large Scale Integration (VLSI-SoC) 2011, Hongkong, China,
October 2011
- Pawan Kumar and Virendra Singh,
Efficient regular expression pattern matching using cascaded automata architecture
for network intrusion detection system`, 9th IEEE East-West
Design and Test Symposium (EWDTS)
2011, Sevastopol, Ukraine, September 2011.
- V. Prasanth, Virendra Singh,
and Rubin Parekhji, `Reduced overhead soft error
mitigation methodology using error control coding technique`, 17th
IEEE International On-Line Test Symposium (IOLTS) 2011, Athens, Greece, July 2011.
- Suraj Sindia, Vishwani Agrawal,
and Virendra Singh, `Nonlinear analog circuit test and diagnosis under
process variation using V-transform coefficients`, 29th IEEE
VLSI Test Symposium (VTS),
2011, California, USA, May 2011
- Naveen Choudhary, M.S. Gaur,
Vijay Laxmi, and Virendra Singh, `Traffic aware topology generation
methodology for application specific NoC`, IEEE International Symposium on
Electronic Design, Test and Application (DELTA) 2011, Queens Town, New Zealand, Jan 2011
- [Book Chapter] Dimitar Nikolov, Mikael Vayrynen,
Urban Ingelson, Virendra Singh, and Erik Larsson, `Optimizing Fault
Tolerance for Multi-Processor System-on-Chip`, Design and Test Technology for Dependable Systems-on-Chip, Editors:
Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, 2010, Hardcover, ISBN:978-1-6096-0212-3.
- Pramod Subramanyan, Virendra
Singh, Kewal K. Saluja, and Erik Larsson, `Energy efficient fault
tolerance in chip multiprocessors using critical value forwarding`, 40th
IEEE International Conference on Dependable Systems and Networks (DSN), Chicago, IL, USA, June 2010.
- Jaynarayan Tudu,
Erik Larsson, Virendra Singh, and Hideo Fujiwara, `Scan cell reordering to
minimize peak power during test cycle: A graph theoretic approach`, 15th
IEEE European Test Symposium (ETS)
2010, Prague, Czech Rep., May 2010.
- Pramod Subramanyam, Virendra
Singh, Kewal Saluja, and Erik Larsson, `A low cost redundant execution
architectures for Chip multiprocessors`, Design Automation and Test in
Europe (DATE) 2010, Dresden,
Germany, March 2010.
- Dimitar Nikolov, Urban
Ingelsson, Virendra Singh, and Erik Larsson, `Estimating error probability
and its application for optimizing roll-back recovery with checkpointing`,
IEEE Symposium on Electronic Design, Test & Applications (DELTA) 2010, Ho Chi Minh , Vietnam, Jan 2010
- Suraj Sindia, Virendra Singh,
and Vishwani Agrawal, `Multi-tone Testing of Linear and Nonlinear Analog
Circuits using Polynomial Coefficients`, IEEE Asian Test Symposium (ATS) 2009, Taichung, Taiwan, Nov
2009.
- Jaynarayan Tudu,
Erik Larsson, Virendra Singh, and Vishwani D. Agrawal, `On Minimization of Peak Power during
SoC Test`, IEEE European Test Symposium (ETS) 2009, Seville, Spain, May 2009.
- Reshma Jumani, Niraj Jain,
Virendra Singh, and Kewal K. Saluja, `DX-Compactor:
Distributed X-Compaction for SoC Test`, ACM Annual Great Lake
Symposium on VLSI (GLSVLSI)
2009, Boston, USA, May 2009.
- Mikael Vayrynen,
Virendra Singh, and Erik Larsson, `Fault-Tolerant
Average Execution Time Optimization for General Purpose Multi-Processor
System-on-Chips`, Intl. Conference on Design Automation and Test in
Europe (DATE) 2009, Nice,
France, Apr 2009.
- Virendra Singh, Michiko Inoue,
Kewal K. Saluja, and Hideo Fujiwara, `Instruction-Based Self-Testing of
Delay Faults in Pipelined Processors`, IEEE Trans. on VLSI Systems,
Vol. 14, No. 11, Nov. 2006, pp. 1203-1215.
- Virendra Singh, Michiko Inoue, Kewal
K. Saluja, and Hideo Fujiwara, `Program-Based Testing of Superscalar
Microprocessor`, Proceedings of the IEEE 14th North Atlantic
Test Workshop, May 2005, pp. 79-86, Berlington,
VT, USA, May 2005.
- Virendra Singh, Michiko Inoue,
Kewal K. Saluja, and Hideo Fujiwara, `Delay Fault Testing of Processor
Cores in Functional Mode`, IEICE Trans. on Information & Systems,
Vol. E-88D, No. 3, March 2005, pp. 610-618.
Funding:
· Project: AI Powered Adaptive Cyber Defence
Framework (2021 – 2023)
PI: Virendra Singh
Sponsor: National Security Council Secretariat, Govt.
of India, Funding: USD 16M (INR 1.2 Arab)
- Indo Japanese Joint Research
Laboratory Program (2016 to 2021)
Project: Architecting Intelligent Dependable Cyber
Physical System Targeting IoTs and Mobile Big Data Analysis
PI: Virendra Singh, IITB and Prof. Masahiro Fujita,
The University of Tokyo
Funding: INR 12.5 Crores (IITB: INR 5.1 Crores, and
TU: Yen 14.8 Crores)
· Indo
Russian (DST-RMES) Joint Project (2017 to 2020)
Project:
Technologies and Toolset for Reliable Control of Production Areas of Internet
of Things
PI:
Prof. RK Shyamasundar, Co-PI: Virendra Singh, IITB,
and Prof. Vsevolod Kotlyarov, SPBSTU, Russia
Funding:
INR 60 Lakhs (IITB)
- Project: Design Development and
Prototype of 720 Gbps Capable Transport Cross Connect Switch (2016 to
2018)
Agency: DRDO, Funding: INR 11.4 Crores
PI: Prof. Ashwin Gumaste, Co-PI: Virendra Singh
- Project: Special Manpower Development
Program for Chip to System Design (2015 to 2020)
Agency: MCIT, Govt. of India, Funding: INR 7.2 Crores
PI: Prof. Shalabh Gupta, Co-PI: Virendra Singh
- Project: Information Security
Research and Development Centre (2015 to 2018)
Agency: MCIT, Govt. of India
PI: Prof. R.K. Shyamasundar,
Investigator: Virendra Singh
- Indo French Cooperative Project
(2016 to 2019)
Project: Reflection Aware ICC Analysis Framework for
Android Apps
PI: Prof. M.S. Gaur, Co-PI: Virendra Singh
- Institutional Grant for
Younger Researchers by Swedish Foundation of International Cooperation
in Research and Higher Education, with Prof. Erik Larsson, Linkoping
University, Sweden - (2008 to 2011)
Project: Design of Self-healing System Chips
Funding: INR 72 Lakhs
- UK India
Education and Research Initiative (UKIERI)
grant, with Prof. MS Gaur, MNIT, Jaipur and Prof. Mark Zwolinski,
Southampton University, UK - (2009 to 2011)
Project: Multi-Processor
Electronic Design Automation
Funding: INR 22 Lakhs
- LSI Technology Research Grant
(2009 to 2013)
Project: Techniques
to Speedup Loading of Scan Pattern
Funding: INR 40 Lakhs (INR 10 Lakhs
per year)
· Research grant under strategic Japanese-Indian
cooperative program (DST-JST) with Prof. Masahiro Fujita,
Tokyo University, Tokyo, Japan (2010 - 2013)
Project: Computer aided design
of hardware accelerated Tsunami prediction system
Funding: INR 1.6 Crores
- Indo Russian
(DST-RFBR) joint research grant with Prof. Anzhela Matrosova,
Tomsk State University (2011 - 2013)
Project: Synthesis of high quality
testable circuits and diagnosis of performance oriented
faults
Funding: INR 20 Lakhs
- Indo Russian
(DST-RFBR)) joint research grant with Lyudmila Babenko, Taganrog Institute
of Technology, and Prof. M.S. Gaur, MNIT, Jaipur (2011 - 2013)
Project: Development of techniques for metamorphic
malware detection and analysis
Teaching:
Last Semester
(Jan-Apr 2018)
- EE-739: Processor Design (Basic
& Advanced)
- EE-709: Testing and
Verification of VLSI Circuits
- CS-654: Current Topics in VLSI
and System Design
Current
Semester (July-Nov 2017)
- CS-683: Advanced
Computer Architecture
- EE-748: Advanced
Topics in Computer Architecture
- EE-309: Microprocessors
Recent Past (at
IIT-B)
- EE-739: Processor
Design (Jan-Apr 2013)
- EE-709: Testing and
Verification of VLSI Circuits (Jan-Apr 2013,
Jan-Apr
2012)
- EE-705: VLSI Design Lab.
(Jan-Apr 2013)
- CS-210: Logic Design (Jan-Apr
2013)
- EE-453/EE-717: Advanced
Computing for Electrical Engineers (Jul-Nov 2012)
- Computer
Architecture (CS-226, MNIT,
Jaipur): (Jan-Apr
2013)
- Computer
Organization and Architecture (IIT
Mandi): (Jan-Apr
2013)
- IT-448: Multi-core
Architectures (MNIT, Jaipur) (Jul-Nov
2012)
Past (at IISc)
- E0-285: Computer
Aided Design of VLSI Systems (Aug -
Dec 2008, Aug -
Dec 2009, Aug-Dec
2010, Aug-Dec
2011)
- E0-286: Testing and
Verification of SoC Design (Jan - Apr 2008, Jan -
Apr 2009, Jan -
Apr 2010, Jan -
Apr 2011)
- SE-286: Data Structures and
Programming (Aug - Dec 2007, Aug - Dec 2008, Aug -
Dec 2009, Aug-Dec
2010, Aug-Dec
2011)
- MEL-G626: VLSI Testing and
Testability (at BITS, Pilani,
Aug-Dec 2006)
(VLSI Testing and Formal Verification)
Other Activities/ Courses:
- IEP on Digital
System Synthesis at IIT Kanpur
(Dec 10-21, 2007)
- Co-coordinator, IEP on VLSI Testing & Verification at
IISc. (Mar 10-19, 2008)
Professional Activities
Convener,
Computer Architecture & Dependable Systems Lab., IITB (2011 - till date)
Convener,
Computer Design and Test Lab., SERC, IISc (2007-2011)
Member,
Departmental Curriculum Committee (DCC), SERC, IISc (2007-2011)
Steering
Committee member
- VLSI Design Conference
- IEEE Intl. Workshop on
Reliability Aware System Design and Test (RASDAT)
- IEEE Asian Test Symposium (ATS)
- IEEE Workshop on RTL and High
Level Testing (WRTLT)
General
Co-Chair - RASDAT
(2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018)
Vice General
Chair: VLSI Design Conference 2014, Embedded Systems Conference 2014
Program
Co-Chair: VLSI Design Conference 2014, Embedded Systems Conference 2014
Program
Co-Chair - WRTLT 2011, VDAT 2013, VDAT 2016, VDAT 2017
Finance Chair -
ATS 2011
Program
Co-Chair - DRV 2011
General
Co-Chair - IWPVTD 2011,
IWPVTD 2012
General
Co-Chair – ATS 2015
Technical
Program Committee Member
- IEEE International Conference on
Computer Design (ICCD) - 2011, 2012, 2013, 2014 (Processor
architecture track)
- IEEE Asia Pacific Design
Automation Conference (ASPDAC) - 2011, 2012, 2013
- IEEE International Symposium on
VLSI (ISVLSI) - 2011
(Chennai)
- IEEE/IFIP International
Symposium on Very Large Scale Integration (VLSI-SoC) - 2011 (Hong Kong)
- Design Automation and Test in
Europe (DATE) - 2009 (Nice), 2010 (Dresden)
- Intl. Conference on VLSI Design
- 2010 (Student
track chair), 2011 (Test Track Chair), 2012 (TV track chair), 2013
- VLSI
Design and Test Symposium (VDAT) - 2009
(Bangalore), 2010 (Chandigarh), 2012 (Kolkata)
- IEEE Workshop on RTL and High
Level Testing (WRTLT) - 2009 (Hong Kong),
2010 (Shanghai), 2011, 2012
- Intl. Conference on Risk and
Security of Internet and Systems (CRiSIS) - 2009 (Toulouse)
- Intl. Conf. on Advanced
Computing and Communication (ADCOM) - 2009
(track chair)
- Intl. Workshop on Network on
Chip Architectures (NoCArc) - 2009 (New York)
- Intl. Conf. on Emerging Trends
in Engineering and Technology (ICETET) - 2009
- IEEE Workshop on Design
Reliability and Variability (DRV) - 2009 (Austin, USA)
- IEEE North Atlantic Test
Workshop (NATW) - 2010 (New York)
Current Students (at IITB)
1.
Suryakant Toraskar (Ph.D,
EE) - Thesis submitted
Thesis: Performance
enhancement in modern computing system
2.
Rajkumar
Chaudhary (Ph.D, EE) - Thesis
submitted
Thesis: Energy
efficient and fault tolerant architectures
3.
Varun Venkitaraman (Ph.D,
EE) - Thesis submitted
Thesis:
Improving efficiency of cache in CPUs and GPUs
4.
Sonali Shukla (Ph.D, EE) - Presynopsis
completed
Thesis:
Securing VLSI systems against hardware attacks
5.
Avinash Kumar (Ph.D, CSE) - Presynopsis
completed
Thesis:
Compiler optimization and their algebraic foundations for irregular programs
6.
Raghunandan K.K
(Ph.D, EE) - Presynopsis completed
Thesis:
Reliable GPGPU architectures
7.
Prokash Ghosh (Ph.D, EE)
Thesis:
Securing memory systems against hardware attacks
8.
Keerthi Sagar Kokkiligadda (Ph.D,
EE)
Research topic:
Efficient virtual memory systems
9.
Veerendrababu Vakkapatla (Ph.D, CSE)
Research topic:
Reinforcement Learning
10.
Sravanthi Settaluri (Ph.D,
CSE)
Research topic: Natural Language Processing
11.
Sourabh Deoghare (Ph.D,
CSE)
Research topic: Machine Translation
12.
Rohit Badjatya (Ph.D,
EE)
Research topic:
Low power VLSI testing
13.
Yogesh Gholap (Ph.D, EE)
Research topic:
Security issues in cyber physical systems
14.
Tejeshwar Thorawade (Ph.D,
EE)
Research topic:
Secure and energy efficient memory hierarchy in computing systems
15.
Samiksha Verama (Ph.D,
CSE)
Research topic:
Secure memory subsystems
16.
Munawira Kotyad (Ph.D, CSE)
Research topic:
Performance efficient GPGPU architecture
17.
Suma Sri Mandru (Ph.D,
CSE)
Research topic:
Security of AI/ML systems, cryptography
18.
Nikhil Kumar
Parida (Ph.D, CSE)
Research topic:
Quantum Key Distribution, Quantum computing
19.
Hasmita Kurre (Ph.D, CSE)
Research topic:
AI/ML powered cybersecurity
20.
Tarun Bisht (Ph.D, CSE)
Research topic:
Trustable and explainable AI, Privacy preserving AI
21.
Pinaki Das (Ph.D, CSE)
Research topic:
Multi-modal machine translation
22.
Rahul Kumar (Ph.D, EE)
Research topic:
Formal verification
23.
Yogeshwar Nath
(Ph.D, EE)
Research topic:
High performance and reliable systems
Full list of
current and former students