EE-709: Testing and Verification of VLSI Circuits

EE-709: Testing and Verification of VLSI Circuits

Semester: Jan - Apr 2012

Class Timings: 10:35 am - 11:30 am (Monday), 11:35 am - 12:30 pm (Tuesday), 8:30 am - 9:25 am (Thursday)

Office Hours: 3:00 pm - 4:00 pm (Thursday)

Syllabus:

Scope of testing and verification in VLSI design process. Issues in test and verification of complex chips, embedded cores and SOCs.

Fundamentals of VLSI testing. Fault models. Automatic test pattern generation. Design for testability. Scan design. Test interface and boundary scan. System testing and test for SOCs. Iddq testing. Delay fault testing. BIST for testing of logic and memories. Test automation.

Design verification techniques based on simulation, analytical and formal approaches. Functional verification. Timing verification. Formal verification. Basics of equivalence checking and model checking. Hardware emulation.

Reference:

1. M. L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing for Digital Memory and Mixed Signal VLSI Circuits, Springer, 2005

2. H. Fujiwara, Logic Testing and Design for Testability, MIT Press, 1985

3. M. Abramovici, M. Breuer, and A. Friedman, Digital System Testing and Testable Design, IEEE Press, 1994

4. M. Huth and M. Ryan, Logic in Computer Science, Cambridge Univ. Press, 2004

5. T. Kropf, Introduction to Formal Hardware Verification, Springer Verlag, 2000

6. Current Literature

7. Class notes

Prerequisite: Knowledge of Digital System Design

Evaluation: Mid term (15%), Final Exam (40%), Course Projects (20%), Assignment (15%), and Continuous Assessment (10%)

Exam Schedule:

Test1:

Test2:

Test3:

Mid Term Exam: Feb 22 (Wednesday) 0830 Hrs to 1030 Hrs

Final Exam:

Assignment 1: Submission deadline – Mar 12(Monday) 5:00 pm

Assignment2:

Assignment3:

Class Schedule:

Jan 2	Course Introduction	Course Introduction, VLSI design flow, need of Pre-silicon verification and post-silicon validation and debug
Jan 3	Course Introduction
Jan 5	Introduction to VLSI Testing	VLSI Testing needs and challenges
Jan 5	Test challenges by Prof. Adit Singh	Test Challenges, yield, and defects
Jan 12	Fault modeling by Prof. Kewal Saluja	Faults and fault models
Jan 16	Fault Equivalence	Yield and Fault Equivalence
Jan 17	Equivalence Checking	Combinational Equivalence Checking
Jan 18	Equivalence Checking - II	BDD operations and SAT
Jan 19	Fault Simulation - I	Logic Simulation, Fault Simulation
Jan 23	Fault Simulation - II	Deductive and Concurrent Fault Simulation
Jan24	CEC-I	Combinational Equivalence Checking
Jan 26	ATPG-1	Automatic Test Pattern Generation (ATPG): Algebraic Method
Jan 30	ATPG-2	D Algorithm, PODEM
Jan 31	ATPG-3	PODEM, FAN
Feb 2	SEC-1	Sequential Equivalence checking
Feb 6	ATPG-4	FAN
Feb 7	ATPG-5	Sequential ATPG
Feb 8	SEC-2	Sequential Equivalence Checking
Feb 9	SEC-3	Sequential Equivalence Checking
Feb 13	Scan-1	Scan Design
Feb 14	SEC-4	Sequential Equivalence Checking
Feb 15	MC-1	Model Checking
Feb 16	Scan-2	Issues in San Design
Feb 22	Midsem Exam
Feb 27	RAS-1	Random Access Scan
Feb 28	RAS-2	Random Access Scan
Mar 01	MC-2	Basics of Model Checking
Mar 05	PScan	Partial Scan
Mar 06	MC-3	LTL
Mar 07	MC-4	LTL & CTL

Selected Readings (Papers):

D. Baik, K. K. Saluja and S. Kajihara, `Random Access Scan: a solution to test power, test data volume and test time`, International Conference on VLSI Design, Jan. 2004
H. Fujiwara, `A new class of sequential circuits with combinational test generation complexity`, IEEE Trans. on Computers, Vol. 49, No. 5, Sep 2000, pp. 895-905
S. Ohtake, T. Masuzawa, and H. Fujiwara, `A non-scan DfT method for controllers to achieve complete fault efficiency`, Proc. of the IEEE Asian Test Symposium (ATS) 1998, pp. 204-211.
T. Iwagaki, S. Ohtake, and H. Fujiwara, `A design methodology to realize delay testable controllers using state transition information`, Proc. of the IEEE European Test Symposium (ETS) 2004, pp. 168-173.
Y. Bonhomme et al., `Power driven chaining of flip-flops in scan architecture`, Proc. of the IEEE International Test Conference (ITC) 2002, pp. 796-803.