Presenter Name	Prottay Adhikari
Email-id:	prottay@ee.iitb.ac.in
Topic:	'Where Digital Design meets Power Systems'
Venue:	To be decided
Date:	19/08/2015
Pre-Requisite:	None
Abstract:	DC-AC converters are important components of any energy system. In present days, the focus of the research has been shifted to multilevel DC-AC converters. However, there are many a topologies to construct a multilevel converter. Once such topology is Modular Multilevel Converter (MMC). MMCs typically consists of stack of capacitances along with switches-which are controlled by the controller. To produce a desired output voltage level, it relies on the voltage across the capacitances, and the switching conditions. The switching conditions are determined depending on the state of each capacitance, desired output voltage level, and loading conditions. This is of great computational complexity to determine the switching states, and those computations are to be carried out every cycle. FPGAs-if connected through a high speed communication interface with the system- offer a very efficient platform for these computations. In the current work, we propose a novel state space model of the MMC, and write a controller algorithm in C. We then test our controller model with the C model of the MMC. If the results are satisfactory, we convert our controller into VHDL using AHIR V2 (Developed at IIT Bombay) synthesis tools. Then, those VHDL designs are tested with the same MMC model. Upon successful validation, the controller will be put on FPGA board, and the communication interface between the host and the FPGA is created using RIFFA 2.0(developed at UCSD) infrastructure. If the FPGA based controller hardware performs well to control the C model of the hardware (running on the host machine), we proceed towards controlling the actual MMC hardware with FPGA based controller.

Presenter Name	Abhimanyu Shekhawat
Cluster	EE4/EE5
Email-id:	shekhawat@ee.iitb.ac.in
Topic:	Transition from MOSFETs to FINFETs and the challenges ahead
Venue:
Mentor:	Sushant Mittal
Session Chair:	Sangya Datta
Date:	02/09/2015 at 3:00 PM
Pre-Requisite:	None
Abstract:	After discovery of transistors, introduction of FinFETs has been considered as the most radical shift in the semiconductor technology. FinFETs has enabled industry to produce most powerful chips in terms of density, speed and power. In my talk I will present the journey of transistors from MOSFETs to FinFETs. And will discuss challenges caused by the process variability and their circuit impact in FinFETs.

Presenter Name	Shikhar Chouhan
Cluster	EE4/EE5
Email-id:	shikhar.chouhan@gmail.com
Topic:	Emerging Solid State Non-Volatile Memory Technologies
Venue:	GG103
Mentor:	Pankaj Kumbhare
Session Chair:	Pankaj Kumbhare
Date:	01/10/2015 at 3:00 PM
Pre-Requisite:	None
Abstract:	The demand for portable devices has raised the technological need for fast, ultra low power, low cost and high density non-volatile memory over the years. Presently, NAND Flash based Solid State Devices (SSDs) are being used as hard disk in hybrid & stand alone configurations. Emerging memory technologies such as Magnetic-RAM, Spin-Transfer Torque RAM, Fe-RAM, Phase Change Memory, and Resistive-RAM have shown the speed of Static-RAM and non-volatile property of Flash Memory and hence become a very attractive topic for exploration. Feasibility in 3-D stacking of such structures gives them an unmatched edge in density over the existing technologies. My talk will give brief introduction to various memory technologies and then I will discuss about the challenges which we face in RRAM development. Keywords: Flash Memory, MRAM, SRAM, RRAM, Fe-RAM, STTRAM, Memristor, Fe-RAM, PCM, DRAM

Presenter Name	Amaldev V
Cluster	EE4/EE5
Email-id:
Topic:	How to build a Consumer Electronic Product - An Engineer's Story
Venue:	TBA
Mentor:	TBA
Session Chair:	TBA
Date:	07/10/2015 at TBA
Pre-Requisite:	None
Abstract:	In this session, the speaker will go through his engineering journey of building a consumer electronics product named ACPAD (Wireless MIDI controller) for the international market during his days at IITB. The talk will focus on how to take an idea to the prototype stage and then to a product which can be sold to the masses - Right from the sourcing of components, to designing electronics for passing international certifications. The speaker will discuss the engineering challenges faced while the building the product on a shoe-string budget and also give sense of how to sell/market a consumer domain product without spending much on marketing. The talk will also include an overview of the speakers experience with the manufacturing setup for hardware electronics in India. Video: Have a look

Presenter Name	Vinayak Hande
Cluster	EE4/EE5
Email-id:	hande.vinayak@gmail.com
Topic:	Design and development of CMOS voltage reference circuits since 1973
Venue:	GG302
Session Chair:	Anamika Singh
Date:	15/1/2016 at 3:30 PM
Pre-Requisite:	None
Abstract:	The design challenges of voltage reference generators in CMOS technology have increased over the years in low voltage low power CMOS integrated circuits constituting analog, digital and mixed-signal modules. The emergence of hand-held power autonomous devices push the power consumption limit to nW regime. Along with these confrontations, limited full scale range of data converters at low supply levels demands accurate reference voltage generators. This talk overviews the allied design challenges and discusses the evolved methodologies to tackle them. Non-bandgap (only CMOS) based reference architectures are proven to be area and power efficient but always have to be accompanied with auxiliary on/off chip trimming mechanism for high accuracy.

Presenter Name	Prof. Shouri Chatterjee
Cluster	EE4/EE5
Email-id:	shouri@ee.iitd.ac.in
Topic:	Energy harvesting from ambient sources
Venue:	GG302
Photo :
Date:	20/1/2016 at 3:30 PM
Pre-Requisite:	None
Abstract:	In this talk we will go through circuits developed at IIT Delhi for energy harvesting. The first IC to be presented is a 300nW sensitive DC DC boost converter with optimally minimized switching and resistive losses. The second IC to be presented is a 10nW sensitive maximum power point tracking DC DC buck boost converter with cold startup.

Presenter Name	Mr. Yogendra Yadav
Cluster	EE4/EE5
Email-id:
Topic:	A partial insight into the nitty-gritty of Semiconductor Foundry
Venue:	GG-302
Speaker Bio :	Mr. Yogendra Yadav completed his M.Tech. from IIT Bombay in 2007 from Department of Electrical Engineering. He has been with TSMC (Taiwan Semiconductor Manufacturing Company) since 2007. Currently he is Senior Engineer in the Device Road-map Development Department in the Power management ICs Group (R&D). He has two US patents and is co-author of a paper in IEEE Transaction on Electron Devices. He is associated with several associations and events and is the President of the Indian Club in TSMC.
Date:	05/02/2016 at 5:30 PM
Pre-Requisite:	None
Abstract:	The speaker will introduce many topics related to a semiconductor foundry, particularly in TSMC. He will be sharing his experience working with TSMC and life in Taiwan. He will speak about topics such as bipolar-CMOS-DMOS technology, SPICE modeling, layout optimization and wafer testing to name a few.

Presenter Name	Reshma Krishnan
Cluster	EE4/EE5
Email-id:	reshma.g.k@gmail.com
Topic:	Molecular Monolayers for Conformal doping on 3D structures
Venue:	GG303
Session Chair:	Tejas Naik
Date:	11/02/16 at 4 PM
Pre-Requisite:	None
Abstract:	It has been a few years since industry has switched to tri-gate transistors and FinFETs. They provide better gate controllability and reduce short channel effects in our current nanometer regime transistor. However, doping the source and drain regions of these vertical transistors is a bottleneck. Alternate approaches to get a uniform doping along the height of these transistors are now being looked at. In this talk, we will be discussing "a Molecular Monolayer Growth" oriented approach for getting defect free, conformal doping on 3D structures.
Presentation Slides:	Click Here.

Presenter Name	Sai Kurude
Cluster	EE4/EE5
Email-id:	skurude@gmail.com
Topic:	A novel SRAM noise margin analysis technique.
Venue:	GG 302
Session Chair:	Abhimanyu Sekhawat
Date:	08/03/2016 at 5:00 PM
Pre-Requisite:	None
Abstract:	Circuit level bench-marking of emerging devices is done from its SRAM performance. However compact model is needed for statistical analysis of SRAM noise margin. We proposed a method to serve the purpose without the use of SPICE compact model. The application of the method is demonstrated. P.S: Main focus of the presentation will be on "How we bypassed a dead-end in research and proposed a simpler and effective method.".
Presentation Slides:	Click Here.

Presenter Name	Akshay Adlakha
Cluster	EE4/EE5
Email-id:	akshayadlakha91@gmail.com
Topic:	Methods to Compensate the Heating Effects in CMOS Power Amplifier Circuits
Venue:	GG 302
Session Chair:	Mahima Arrawatia
Date:	11/03/2016 at 5:00 PM
Pre-Requisite:	None
Abstract:	Power amplifiers (PAs) are the key component in today’s communication circuits. Being high power devices they lead to increase in the on-chip temperature. Heating of chip not only degrades the major performance characteristics (viz. gain, linearity) of PA but also affects the other on-chip components. In this talk, I will discuss different compensation circuits to stabilize PA’s gain over the temperature.
Presentation Slides:	Click Here.

Presenter Name	Snehasish Roychowdhury
Cluster	EE4/EE5
Email-id:	snehasish@ee.iitb.ac.in
Topic:	EMI immune Gm-C Filter Design
Venue:	GG 302
Session Chair:	Anjan Kumar
Date:	07/4/2016 at 3:30PM
Pre-Requisite:	None
Abstract:	In highly densed Analog integrated circuits, Electromagnetic Interference is the major practical concern now-a-days. Though odd harmonics contributed by out of band EMI inputs can be restricted by low pass characteristics of the filter, but even harmonics cause DC offset which can't be anyway eliminated. This DC offset may change the region of operation of some of transistors. Hence, Immunity to out-of band Interference is necessary as well. In this approach, I have designed a very low cut-off frequency highly EMI Immune cross coupled trans-conductor based Gm-C filter of cut-off frequency in tens of Hertz (70Hz).
Presentation Slides:	Click Here.