H. Narayanan, "Some applications of an Implicit Duality Theorem to connections of structures of special types including Dirac and reciprocal structures", Systems & Control Letters 45 (2) (2002) pp. 87-95.

H.Narayanan, "Minimization of Symmetric and General Submodular Functions" (Accepted, Discrete Applied Maths, Special Issue on Submodular Functions, 2002, North Holland)

H.Narayanan,"The Realization of Finite State Machines by Decomposition and the Principal Lattice of Partitions of a Submodular Function (Accepted, Discrete Applied Maths, Special Issue on Submodular Functions, 2002, North Holland)

M.P.Desai,H. Narayanan,S.Patkar, "Improving Graph Partitions using Submodular Functions" (Accepted, Discrete Applied Maths, Special Issue on Submodular Functions, 2002, North Holland)

Sachin B. Patkar and H. Narayanan,"A note on optimal covering augmentation for graphic polymatroids", Information Processing Letters, 79 (6) (2001) pp. 285-290.

H.Narayanan, "On the Duality between Controllability and Observability in Behavioural Systems Theory" Proc. International Conference on Communications Control and Signal Proc. CCSP 2000, Bangalore, July 25-July 28,2000, pp 183-186.

R. Shelar, H. Narayanan and M. P. Desai, "Orthogonal Partitioning and Gated Clock Architecture for Low Power Realization of FSMs", Proceedings of the 13th Annual IEEE International ASIC/SOC Conference, 13-16 Sept. 2000, Washington, pp. 266-270.

Sachin B. Patkar, H. Narayanan, "Fast Algorithm for Succesive Reinforcement of a Network", FSTTCS2000, New Delhi, December 2000.

H.Narayanan, "On the Minimization of symmetric and general submodular functions" Invited talk delivered at the International Symposium of Mathematical Programming 2000, Atlanta, U.S.A, Aug 7-Aug 11,2000

S.Patkar and H.Narayanan, "Applications of submodular functions to problems in VLSI CAD" Invited talk delivered at the International Symposium of Mathematical Programming 2000, Atlanta, U.S.A, Aug 7-Aug 11,2000.

Shabbir H. Batterywala and H.Narayanan, "Efficient DC analysis of circuits for moment and derivative computations of interconnect networks" Proceedings of 12th international conference in VLSI design, pages 169--174, Jan. 1999.

H.Narayanan B.N.V.M.Gupta and M.P.Desai, "A state assignment scheme targeting performance and area" Proceedings of 12th international conference in VLSI design, pages 378--383, Jan. 1999.

R.Shelar, M.P.Desai and H.Narayanan, "Decomposition of Finite State Machines for Area, Delay minimization", The proceedings of the 1999 IEEE International Conference on Computer Design, Austin, Texas, USA.

Shabbir H. Batterywala and H. Narayanan, "Spectral Approximation Method for Choosing `Relevant' Eigenvalues During Interconnect Analysis" Proceedings of the 3rd World Multiconference on Systemics, Cybernetics and Informatics, The 5th International Conference on Information Systems, Analysis and Synthesis}, Orlando, USA, September 1999,

H. Narayanan and Shabbir H. Batterywala, "Time Domain Method for Reduced Order Network Synthesis of Large RC Circuits", The proceedings of the 1998 IEEE International Symposium on Circuits and Systems, p.82-85, Monterey, California, USA, 1998.

S.Patkar, S.Batterywala, M.Chandramouli and H.Narayanan, "A New Partitioning Strategy Based on Supermodular Functions" Proceedings of 10th International Conference on VLSI Design, Hyderabad,India,(1997) 32-37.

H. Narayanan, "Submodular Functions and the Hybrid Rank Problem for electrical networks" Invited Talk delivered at the Indian Science Congress '97, New Delhi, January 3- 8, 1997

H.Narayanan, "Principal Partition and Principal Lattice of Partitions - connections and analogies" Invited talk delivered at the 16th International Symposium on Mathematical Programming, Lausanne August 23-August 29,1997.

H.Narayanan, "Membership problem for polymatroids with matroid expansion" Invited talk delivered at the 16th International Symposium on Mathematical Programming, Lausanne August 23-August 29,1997.

S. Patkar, S. Batterywala, M. Chandramouli and H. Narayanan, "A New Partitioning Strategy Based on Supermodular Functions," Proceedings of 10th International Conference on VLSI Design, Hyderabad, India, 32, (1997).

H. Narayanan, "Submodular Functions and the Hybrid Rank Problem for electrical networks," Invited Talk delivered at the Indian Science Congress '97, New Delhi, January 3-8 (1997).

H. Narayanan, "Submodular Functions and Electrical Networks," Annals of Discrete Mathematics 54, North-Holland (1997).

H. Narayanan, "Principal Partition and Principal Lattice of Partitions - connections and analogies," Invited Talk delivered at the 16th International Symposium on Mathematical Programing, Lausanne, August 23-29 (1997).

H. Narayanan, "Membership problem for polymatriods with matroid expansion," Invited Talk delivered at the 16th International Symposium on Mathematical Programming, Lausanne, August 23-29 (1997).

Ranjeet Ranade, Sanjay Bhandari, A.N. Chandorkar, "VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder," Proc. 9th International Conference on VLSI Design, Bangalore, India (1996).

H. Narayanan, S. Roy and S. Patkar "Approximation algorithms for min-k-overlap using the PLP approach," Journal of Algorithms 21, 306 (1996).

M. P. Desai and Y. T. Yen, "A systematic technique for the verification of critical paths in a 300 Mhz CPU using circuit simulation," 33rd Design Automation Conference, June (1996).

M. P. Desai, R. Crijetic and J. Jensen, "Sizing of clock distribution networks for high performance CPU chips," 33rd Design Automation Conference, June (1996).

H. Narayanan, "Convolution and Dilworth truncation of submodular functions" Special issue on Decision Sciences, Journal of Indian Institute of Science, Bangalore, 75, 25 (1995).

M. V. Kamath and H. Narayanan, "The partition approach to the solution of a class of routing problems," International Journal of Management and Systems, Special Issue on Mathematical Computing 11, 353 (1995).

S. Y. Kulkarni, K. D. Patil and K. V. V. Murthy, "Experimental Characterization of VLSI Interconnects Used in High-speed Multichip Modules," Proc. 4th Intl. Conference on VLSI and CAD (ICVC 95), Seoul (1995).

S. Y. Kulkarni and K. V. V. Murthy, "Transmission Line Model Parameters for Very High-speed VLSI interconnects in MCMs Using FEM with Special Elements," Proc. 8th International Conference on VLSI Design, New Delhi (1995).

S.Y. Kulkarni and K.V.V. Murthy, "Multichip Module structures for minimizing crosstalk effects in high-speed applications," Proc. 1995 Intl. Conf. on EMI/EMC, Madras, India (1995).

S.Y. Kulkarni and K.V.V. Murthy, "SPICE simulations of high-speed VLSI interconnects for MCM's," Proc. Intl. Conf. on Automation (ICAUTO '95) (1995).

S.Y. Kulkarni, K.V.V. Murthy, N.N.S.S.R.K. Prasad and Y.G.K. Patro, "High-frequency characterisation of Multilayer PCB's," Proc. Intl. Conf. on EMI/EMC, Madras, India (1995).

K.V.V. Murthy and P.C. Unnikrishnan, "A Neural Network Approach to Design Circuits with Lesser Complexity," Computer Science and Informatics 25, 76 (1995).

M. P. Desai and V. B. Rao, "A characterization of the smallest eigenvalue of a graph," Journal of Graph Theory, February (1994).

M. P. Desai, P. R. Kumar and Sunil Kumar, "Quasi-Statically cooled Markov Chains," Probability in the Engineering and Information Sciences, March (1994).

H. Narayanan, "Polymatroids and electrical networks," Invited Talk, 15th International Symposium on Mathematical Programming, Ann Arbor, USA, Aug. 15-19 (1994).

S. Roy and H. Narayanan, "Application of the principal partition and principal lattice of partitions of a graph to the problem of decomposition of a finite state machine," Proceedings of the IEEE Internationa l Symposium of CAS, Chicago, Illinois, (1993).

M. P. Desai and V.B. Rao, "On the Convergence of revisable Markov Chains," SIAM J. Matrix Analysis and Applications, October (1993).