V. Ramgopal Rao, Ph.D., IEEE Fellow


P. K. Kelkar Chair Professor, Department of Electrical Engineering (On Lien)

IIT Bombay

Home page of Prof.V.Ramgopal Rao





















Principal Investigator/Co-Investigator for the following funded sponsored / consultancy projects:

  1. (Centre for Excellence in Nanoelectronics project)(Ministry of Communications and Information Technology, Govt. of India (ongoing) (2006-2010) - As part of this US $ 50 Million (Phase-1 & Phase-2) project between IIT Bombay & IISc Bangalore, supported by the Ministry of Communications & Information Technology (MCIT), two Centres of Excellence in Nanoelectronics are established at these two institutions. These centres possess state-of-the art facilities for nano-device fabrication. The two centres collaborate closely with over a dozen leading international semiconductor industries involving substantial funding from them. For example, at IIT Bombay, Applied Materials has created a "Nano-manufacturing laboratory" with state of the art equipment for CMOS fabricaton. The equipment involves 8-inch cluster tools for high-k deposition, PVD Endura & Etch Centura with the total cost of donation amounting to approximately US $ 10 Million. There are also Applied Materials researchers stationed at IIT Bombay for the running, maintenance and research activities involvng these tools. IIT Bombay has also generously funded this project as part of its internal thrust area programme. Overall, at IIT Bombay, a 200 crore facility (~US $ 25 Million) is fully operational currently with active involvement of Government, industry & IITB. Over 200 users are currently using this facility at IIT-B including users from over 75 organizations in India. The external users are supported by the "Indian Nanoelectronics User Programme (INUP)", funded by the Ministry of Communications & Information Technology (MCIT).

    For more information about the CEN Activities, please visit:
  2. Polymer based sensors for environmental applications (DAE-SRC Outstanding Research Investigator award) (2011-2015) – as part of this activity, polymer nano-mechanical sensor platforms developed in our group over the past 5 years are being applied to solve some of the key problems in strategic areas.
  3. Low-k Dielectrics & Bottom-up approaches for CMOS Scaling (Applied Materials Corporation) (2010-2013) – as part of this activity and involving a team of chemists, we are screening a variety of organic materials for their dielectric constant with a view to identify the most suitable candidates for CMOS back-end applications. The work is also focused on developing bottom-up approaches to solve some of the CMOS scaling issues. The work has resulted in high quality publications jointly with Applied Materials.
  4. Dielectrics & their Integration into Nano-scale Logic and Memory Devices (DST, Govt. of India) (2012-2014): The work mainly focusses on developing a gate stack for future logic and memory applications.
  5. iSens: A point of care diagnostic system for early detection of myocardial infarction (under the National Programme on Smart Structures & Systems (NPMASS) 2009-2013** - as part of this project a lab-on-chip for cardiac diagnostics is currently being developed with the aim to commercialize the technology. The work involves prototype buildng, field trials, and close interactions with the industry. A company NanoSniff Technologies Pvt. Ltd. has been incubated at IIT Bombay based on this technology.
  6. Radiation Hard CMOS Technologies for Space Applications (Texas Instruments India)** - As part of this collaboraton with TI, commercial off-the-shelf CMOS technologies were optimized for improved radiation hardness using various design/layout techniques.
  7. Micro-fabricated sensors for Vapour Phase Explosive Detection (ongoing) (2007-2011)** - This is a project sponsored by the Principal Scientific Advisor's office, Govt. of India to develop micro-fabricated sensors for RDX & TNT detection. This is a collaborative activity with the School of Bio-sciences & Engg. and the Department of Chemistry at IIT Bombay and involves multiple organizations in the country.A company NanoSniff Technologies Pvt. Ltd. has been incubated at IIT Bombay based on this technology.
  8. MEMS Switches for Power Electronics Applications (Larsen &Toubro (L&T) Limited) (2008-2009)** - As part of this project various MEMS switches were designed for power electronics applications.
  9. Novel Circuit Design Approaches with Multi-gate MOSFETs (Intel, CRL, Portland Group),(2006-2008):** Through this collaboration with the CRL group Intel, the circuit design challenges and the use of multi-gates in circuit design were ssstematically investigated for logic as well as mixed-signal applications.
  10. I/O Circuit applications for Novel devices (Infineon, Munich, Germany and currently Intel Mobile Communications, Munich Germany) (2008-2013) (ongoing):** Efforts are made to find circuit solutions which reduce the special requirements for the IO devices. Novel IO devices have been proposed to overcome this problem which are compliant with the processing of the thin gate oxide devices and do not cause large additional process costs. Multiple US patents have been filed based on this work.
  11. Ultra-low Voltage CMOS Circuits (Infineon, Munich, Germany& currently Intel Mobile Communications, Munich, Germany) (2008-2013)(ongoing):** As part of this project with Infineon, sub 0.3-0.4 V CMOS circuits are being designed with novel devices. The work entails coming up with device design methodologies for such ultra low voltage operation, and demonstrating the applicability for specific applications that are of interest to Infineon.
  12. Technology/Device Options for sub 22nm node CMOS (Infineon, Munich, Germany) (2008-2010)** As part of this project with Infineon, various CMOS technologies were investigated for the 22m and below CMOS nodes.
  13. Sub 65 nm node CMOS - Novel Devices (2005-2010)(Department of Science and Technology, Govt. of India [UNDER THE SWARNAJAYANTI FELLOWSHIP SCHEME](ongoing)** - The work is primarily targeted towards solving the scaling issues with CMOS technologies. We have proposed novel device structures that show a steep sub-threshold swing, and efforts are currently being made to experimentally realize these structures. Various device concepts have also been looked into using advanced 3-D simulations, which has helped understand the limitations with the current technologies. The work has resulted in multiple US patent filings, IEDM papers and a large number of publications in the world’s leading journals.
  14. Technology aware Design Challenges in Nano-scale CMOS Technologies (IBM Corporation) (2007-2008)** - As part of this effort (sponsored as a [[http://www-304.ibm.com/jct09002c/university/scholars/ur/awards/faculty/index.html|IBM Faculty Award ]]), technology aware design challenges specific to the Finfets were investigated. The work has resulted in high quality publications in the world’s leading journals and conferences.
  15. Optimization of Power Transistors (International Rectifier Corporation & Vishay Siliconix-USA) (2006-2007):** As part of this project, IRC's power transistor designs were optimized for improved performance.
  16. Multigate MOSFETs (IMEC, Belgium) (2005-2007)** - As part of this interaction with IMEC Belgium, Multi-gate MOSFETs were optimized from both the device and circuit performance point of view. Novel characterization techniques were also developed for interface characterization in MuGFETs. The Taurus TCAD tools are optimized for the IMEC process flow based on the extensive device characterization data. These optimized TCAD tools were used for understanding the device-circuit level interactions using look-up-table based ciruit simulation approaches. A comprehensive MuGFET device-circuit simulation framework has been developed as part of this activity.
  17. Radiation Sensors/Silicon Drift Detectors (BARC) (2005-2006)** - as part of this project, novel detectors were fabricated on silicon for low noise and high resolution X-ray spectroscopy and other applications.
  18. Nitride Based Passive Dosimeters (MHRD, Govt. of India)(2005-2006)** - as part of this project a nitride based dosimeter technology was developed that does not require external power supply during the sensing operation.
  19. CMOS Noise/Device Characterization for Mixed Signal Applications (Department of Science and Technology, Govt. of India (2004-2006)** - as part of this sponsored project, extensive experimental characterization of sub 100 nm MOSFETs has been carried out for their noise and other analog/digital device figures of merit.
  20. Mixed Signal CMOS: Intel (2003-2005)** - through this research collaboration with Intel (CRL-Portland), scaled CMOS technology optimizations have been looked at and a methodology developed for mixed-signal circuits
  21. Biosensors for Cardiac Applications: National Programme on Smart Materials (NPSM), ADA, India (2004-2006)** - a full system development containing bio-sensors for myocardial infarction has been initiated as part of this interdisciplinary project, involving faculty and students from EE, Material Science, Bio, Chemistry and Mechanical Engg. departments. The work is currently continuing as part of the Nanoelectronics centre activities with the goal to develop a lab-on-chip for cardiac diagnostics.
  22. "Nanotechnology" (Celebration Motion Pictures)(2005-2006)-** as a consultant, Prof. Rao advised a company for creation of video content on Naotechnology for children. 13 episodes (of 30 minutes each) addressing different aspects of Nanotechnology were created that were telecast on Doordarshan India (Sunday mornings). The idea for doing this was to make Nanotechnology and the associated areas interesting for children by using lively characters and animation.
  23. Molecular Electronics: Cross Disciplinary Research Group (CDRG), IITB (2004-2006)** - as part of this interdisciplinary project, various molecules have been chemically synthesized and electrically characterized for various electrical applications. The work is continuing as part of the Nanoelectronics centre activities.The work has resulted in high quality publications in the world’s leading journals and conferences.
  24. Plasma Damage Characterization: Department of Science and Technology, Govt. of India (2002-2004)** - as part of this project, plasma implantation induced damage on sub 3 nm gate oxides was investigated. We had also subsequently developed a plasma immersion ion implantation system at IIT Bombay which is currently used for CMOS applications.
  25. Understanding and Modeling of Fringing fields in High-K Gate Dielectric MOSFETs: Intel (2000-2002)** - an analytical model has been developed for circuit simulations, by taking into account the fringing fields in high-k gate dielectric MOSFETs. Extensive device optimizations have been carried out to optimize a device employing high-k gate dielectrics. The work has resulted in high quality publications jointly with Intel Corporation in the world’s leading journals and conferences.
  26. Oxide scaling effects on design issues: Intel (2000-2002)** - using an in-house look-up-table simulator, extensive work has been done at optimizing the gate dielectrics for circuit applications. The work has resulted in high quality publications jointly with Intel Corporation in the world’s leading journals and conferences.
  27. Channel Engineering for Sub 100 nm MOSFETs:Department of Science and Technology, Govt. of India (2000-2002)** - process window for Single Halo MOSFETs has been identified for optimum mixed-signal performance using extensive device/circuit simulations.



Email id : rrao@ee.iitb.ac.in

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