H. Narayanan

Affiliations and Address:

Department of Electrical Engineering,
Department of Electrical Engineering,
Room no 310,
Indian Institute of Technology
Powai, Mumbai 400076
Ph: +91-22-576 8431, +91-22-576 7431, + 91-22-576 7400  
FAX: +91-22-572 3707



H. Narayanan did  his B.Tech. and Ph.D. from IIT Bombay. He has been a faculty member with the Electrical Engineering Department at IIT Bombay since 1974. He was a visiting faculty with the EE-CS Department at UC Berkeley, Berkeley, California during 1983-1985. During 2000-2003, he was Head of the Department of Electrical Engineering at IIT Bombay.  Dr. Narayanan's primary interests are in the area of Electrical Network Analysis - particularly in the use of topological methods for the efficient analysis of networks. He has supervised the building of the general purpose circuit simulator BITSIM, which uses such methods. BITSIM permits the option of using the Conjugate gradient method for solution of the linear equations which arise during circuit simulation.  He is also interested in VLSI optimization problems such as partitioning where he applies the theory of submodular functions to produce efficient partitioners. He has participated in the building of VLSI circuit partitioners (related to realization through FPGAs) for industries in the US and in Japan.  He is the author of  the  monograph, Submodular Functions and Electrical Networks (North Holland, 1997).

Courses Offered