The group has a strong research programme encompassing all the different
areas of Microelectronics & VLSI. A large number of research papers are published every year in high impact peer  ..



     The Group has considerable expertise in characterization, modeling and simulation. An important part of the characterization and modeling work has been to model radiation effects in MOS devices and circuits. This has included modeling build-up of radiation-induced charge in the oxide, threshold shifts and mobility degradation as well as performance changes in digital and analog circuits. In addition, the Group has studied modeling radiation effects in bipolar transistors and circuits, and SiGe HBTs. An outcome of these efforts were compact radiation models suitable for inclusion into a circuit simulator, and the development of a version of SPICE including such models. A related area of work has been in modeling hot-carrier effects, which show many similarities to radiation effects. Much of this modelling work has been supported by extensive experimental characterization in our well-equipped Characterization Laboratory.

     In the area of compact modeling for circuit simulation applications, we have also developed compact charge and capacitance models for ultra-small geometry MOS transistors, models for SOI MOS transistors, and models for ESD and latch-up simulation. We are also working on interconnect capacitance extraction using Monte Carlo techniques, and modeling of high-power devices.

In the area of simulation, we have worked extensively on developing new device simulators. The focus has been to develop simulators which can predict degradation in the performance of MOS devices, under radiation and hot-carrier stress. This means that the simulation has to be done in full in both the oxide as well as the semiconductor, which sets these simulators apart from most available simulators. Again, experimental validation in our laboratory has accompanied the simulations. We have also worked on design and simulation of advanced sub-0.1 µ CMOS devices which have novel structures,high-k dielectrics,and channel engineered structures. This includes optimization of thickness and k value of high-k dielectrics, and optimization of doping profiles in delta-doped and lateral asymmetric channel (LAC) devices.