Several chips have been designed at IIT Bombay. This includes small-sized 3 and 5 mm nMOS test and gate array chips designed for fabrication at the IIT Bombay laboratory (including a radiation-hard gate array chip), as well as LSI/VLSI level chips. Most of the work has been on MOS, but some bipolar LSTTL chips have been designed for Bharat Electronics Ltd., which are now being manufactured and marketed in India.

     Chips which have been designed include a 4 bit microcontroller, a RISC based microcontroller, a pipelined linear equation solver, and several FPGA based applications, such as an IEEE 488 interface controller and DSP based lock in amplifier. Chips based on new algorithms for addition, multiplication, and digital filtering have also been designed. Current interests focus on low power and mixed analog/digital design. The group uses the MOSIS programme very effectively for getting the designs fabricated.

    In the area of CAD tool development, there is considerable experience in circuit and timing simulators, and the related issue of resistance and capacitance extraction. A circuit simulator and a timing simulator have been written at IIT Bombay. The circuit simulator is based on the idea of improving efficiency tremendously by using multiport decomposition. There is also work on VLSI problems of partitioning using the theory of submodular functions. Expertise exists in the group for timing verification, delay modelling, and circuit and interconnect optimization. We have also developed tools for reliability prediction and yield based on the layout geometry, including identification of critical areas. A CAD tool is currently under development for assessing EMI/EMC effects on ICs.