IEEE International Workshop on Reliability Aware
System Design and Test |
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Even as advances in CMOS technology come up
against physical limits of material properties and lithography, raising many
new challenges that must be overcome to ensure IC quality and reliability,
there appears to be no obvious alternate technology that can replace
End-of-Roadmap CMOS over the next decade. However, many reliability
challenges from increasing defect rates, manufacturing variations, soft
errors, wearout, etc. will need to be addressed by
innovative new design and test methodologies if device scaling is to continue
on track as per Moore`s Law to 10nm and beyond. The key objective of this annual
workshop, started in conjunction with the International Conference on VLSI
Design in 2010, is to provide an informal forum for vigorous creative
discussion and debate of this area. The aim is to encourage the presentation
and discussion of truly innovative and `out-of-the-box`
ideas that may not yet have been fully developed for presentation at reviewed
conferences to address these challenges. Additionally, the workshop includes
embedded talks and tutorials on cutting edge topics related to reliability
aware design of CMOS and hybrid nanotechnology systems. Representative topics include, but are not limited to:
RASDAT 2010 RASDAT 2011 RASDAT 2012 RASDAT 2013 Pune, India
(Jan 9-10, 2013) RASDAT 2014 IIT Bombay,
Mumbai, India (Jan 9-10, 2014) RASDAT 2015 Bangalore,
India (Jan 8, 2015) RASDAT 2016 Kolkata,
India (Jan 7-8, 2016) Steering Committee Kewal K. Saluja (US) -
Chair Jacob A. Abraham (US) Vishwani
D. Agrawal (US) Bashir Al-Hashimi (UK) Bernd Becker (DE) Abhijit Chatterjee (US) Hideo Fujiwara (JP) Masahiro Fujita (JP) Erik Larsson (SE) Rubin Parekhji
(IN) Sudhakar M. Reddy (US) Adit D.
Singh (US) Virendra Singh (IN) |