Course Content
Scope of testing and verification in VLSI design process. Issues in test and verification of complex chips, embedded cores and SOCs. Fundamentals of VLSI testing. Fault models. Automatic test pattern generation. Design for testability. Scan design. Test interface and and boundary scan. System testing and test for SOCs. Iddq testing. Delay fault testing. BIST for testing of logic and memories. Test automation.Design verification techniques based on simulation, analytical and formal approaches. Functional verification. Timing verification. Formal verification. Basics of equivalence checking and model checking. Hardware emulation.
Text / References
- 1 267011M. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits", Kluwer Academic Publishers, 2000.267011M. Abramovici, M. A. Breuer and A. D. Friedman, "Digital Systems Testing and Testable Design", IEEE Press, 1990.267011T.Kropf, "Introduction to Formal Hardware Verification", Springer Verlag, 2000.267011P. Rashinkar, Paterson and L. Singh, "System-on-a-Chip Verification - Methodology and Techniques", Kluwer Academic Publishers, 2001.