Course Content
Basic concepts of hardware description languages. Hierarchy, Concurrency,Logic and Delay modeling. Structural, Data-flow and Behavioural styles of hardware description. Architecture of event driven simulators. Syntax and Semantics of VHDL. Variable and signal types, arrays and attributes. Operators, expressions and signal assignments. Entities, architecture specification and configurations. Component instantiation. Concurrent and sequential constructs. Use of Procedures and functions, Examples of design using VHDL. Syntax and Semantics of Verilog. Variable types, arrays and tables. Operators, expressions and signal assignments. Modules, nets and registers, Concurrent and sequential constructs. Tasks and functions, Examples of design using Verilog. Synthesis of logic from hardware description.
Text / References
- 1 J. Bhaskar, "VHDL Primer", Pearson Education Asia 2001.
- 2 Z. Navabi, "VHDL", McGraw Hill International Ed. 1998.
- 3 S. Palnitkar, "Verilog HDL: A Guide to Digital Design and Synthesis", Prentice Hall (NJ, USA), 1996.
- 4 J. Bhaskar, "Verilog HDL Synthesis - A Practical Primer", Star Galaxy Publishing, (Allentown, PA) 1998.