Course Content
Overview Superscalar and VLIW architecture. Limits of instruction level parallelism(ILP). Simultaneous multithreaded (SMT) architecture, Performance enhancement through branch prediction and value prediction, Bulk SMT, Thread level speculation fetch, Multicore architectures, data marshaling for mult-icore architecture, power constrained CMPs, heterogeneous core design, Core Fusion, Transactional memories. Performance evaluation of complex microarchitectures. On-chip interconnects (Network -On-Chip). Architectural vulnerabilities and reliable architectures. Patchable design. Secure architectures. Energy efficient architectures. Power management. Cache design, energy efficient cache partitioning, fast thread migration, thread throatling.
Text / References
- 1 The Course will be based on the research papers from current conferences and journals.I. J.L. Hennessy and D.A. Patterson, Computer Architecture: A quantitative approach, Fifth Edition, Morgan Kaufman Publication 2II JP Shen and MH Lipasti, Modern Processor Design, MC Graw Hill, Crowfordsville, 2005,III. Current literature (Conferences: ISCA, Micro, HPCA, ICCD, DSN etc; Journals: IEEE Trans. on Computers, IEEE Computer Architecture Letters etc.)Some Representative Research Papers:
- 2 Shekhar Borkar and Andrew Chien, "The future of microprocessors", Communications of ACM, vol.54, no.5, May 20112. A. Tumeo, S.Secchi and O. Villa, "Designing next-generation massively multithreaded architectures for irregular application", IEEE Computers, vol.45, no.8, Aug. 2.
- 3 Andrew Lukefahr et al. "Composite Cores: Pushing Heterogeneity into a core", Proc. of Micro 2.