Test and Verification of Digital Integrated Circuits

This course will cover the aspects of challenges and complexities associated with testing and verification of digital integrated circuits in the context of RTL to GDS flow and post-fabrication test. The course will introduce functional, timing, physical and electrical verification concepts at various stages of the design cycle. Verification principles including equivalence checking, property checking, formal property, assertion and simulation-based verification along with scoreboards for code coverage, and functional coverage will be addressed. Background on SAT solvers and SAT-based ATPG generation for post-fabrication tests and developing the stuck-at-fault models. Generation of ATPG patterns and additional on-chip hardware for test infrastructure such as scan chain and general DFT concepts from an SoC point of view will be explored.