Course Content
In this course, fundamentals of high-speed chip-to-chip communication, including on-chip and system level design and analysis techniques will be taught. The course will also cover various multi-die packaging techniques with new off-chip interconnect technologies. The course will then focus on high speed system design, clocking methodologies in serial links, SerDes IC design, transmission line and channel effects, cross-talk, noise, phase-noise and jitter, power and signal integrity considerations. The topics include an in depth discussion on phase-locked loops (loop), delay-locked loops (DLL), clock data recovery, half duplex and full duplex interconnects. Electronic packaging, multi-chip packaging, wire bonding, chip to board connections, multi-die packaging and their modeling will form other portion of the course.
Text / References
- 1 1 - High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting, KSD Oh and XCC Yuan. Prentice Hall, 2011. 2 - Advanced Signal Integrity for High-Speed Digital Designs, S. H. Hall and H.L. Heck, John Wiley & Sons, 2009. 3 - Digital Systems Engineering, W. Dally and J. Poulton, Cambridge University Press, 1998. 4 - Design of Integrated Circuit for Optical Communications, Behzad Razavi, McGraw-Hill, 2003.