IEEE Reliability Aware System Design and Test (RASDAT) 2013

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6^th IEEE International Workshop on Reliability Aware System Design and Test

(In conjunction with the 28^th International Conference on VLSI Design)

Bangalore, India January 7-8, 2015

Past Events

Call for Papers (pdf)

Key Dates

Invited Talks

Panel

Visa

Venue

Hotel

Registration

RASDAT 2016

Submission deadline: 20 November 2014

Keynote/Invited Talks:

Dipti Deodhare, DRDO

Somyendu Raha, IISc

Aditya Kanade, IISc

Prahalad, Math Works

Susanta Chakrabarty, IIEST

Even as advances in CMOS technology come up against physical limits of material properties and lithography, raising many new challenges that must be overcome to ensure IC quality and reliability, there appears to be no obvious alternate technology that can replace End-of-Roadmap CMOS over the next decade. However, many reliability challenges from increasing defect rates, manufacturing variations, soft errors, wearout, etc. will need to be addressed by innovative new design and test methodologies if device scaling is to continue on track as per Moore`s Law to 10nm and beyond. The key objective of this annual workshop, planned to be held in conjunction with the International Conference on VLSI Design, is to provide an informal forum for vigorous creative discussion and debate of this area. The aim is to encourage the presentation and discussion of truly innovative and `out-of-the-box` ideas that may not yet have been fully developed for presentation at reviewed conferences to address these challenges. Additionally, the workshop invites embedded talks and tutorials on cutting edge topics related to reliability aware design of CMOS and hybrid nanotechnology systems.

Representative topics include, but are not limited to:

-Design for test,

- Built-in self-test

- ATPG and defect oriented test

- Delay test

- Low power test

- Instruction-based self-test

- On-line test methodology

- Reliability of CMOS circuits

- Self checker circuits

- Self diagnosis methods

- Fault tolerant micro-architecture

- Self-healing system design

- Energy and performance aware fault tolerant micro-architectures

- Device degradation and mitigation

- System validation methodology

- Secure system design

- Design for reliability, dependability, and verifiability

Submissions: Authors are invited to submit previously unpublished technical proposals. The proposals must be full papers not to exceed 6 pages. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and 4 to 6 keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address. Submit a copy of your proposal in PDF either online submission or via e-mail to: rasdat@ee.iitb.ac.in

Key Dates:

Paper Submission: November 20, 2014

Acceptance Notification: November 30, 2014

Final Paper Due: December 15, 2014

Presentation Due: Jan 1, 2015

General Information

Adit Singh

Auburn University, Auburn, USA

E-mail: adsingh@auburn.edu

Tel: +1.334.644.1647

Fax: +1.334.844.1809

Virendra Singh