Table of Contents

Anil Kottantharayil

(Associate Professor, EE)

anilkg.jpg

Research Interests:

  • CMOS device physics, design and modelling
  • Materials for advanced CMOS devices
  • Electrical characterization
  • Gate oxide reliability and hot-carrier effects
  • Radiation effects on MOS devices
  • Silicon solar cells

M. Tech/DD Project Topics for Y2012:

  • Nano structured gate stack for flash memory applications: Flash memory is currently the technology driver for the semiconductor industry. However scaling of flash memories is challenged and material solutions are explored for further scaling. The leading material innovations are expected in the gate stack. In this project/seminar you would work on various material innovations being explored for the gate stack in flash technology like metal nanocrystals, graphene etc. The project is funded by the Semiconductor Research Corporation, USA.
  • Graphene for CMOS: Graphene is an interesting material for several applications in advanced semiconductor devices. Since the material do not have a band gap and is hence a bad semiconductor. However other properties of the material could be of interest to electronic applications. An example of our work in this area can be found in item 45 of the “conference” publication list.
  • Simulation/fabrication/characterization of new Si/Ge semiconductor device architectures, for example junctionless transistors: Please refer to the publication list (journals: 27 & 29, 30) for some of the work we have reported. The project is part of phase 2 of centre of excellence in nanoelectronics.
  • Simulation/Fabrication/characterization of Silicon Wire Solar Cells: Silicon wire solar cells promise reasonably high efficiency with small thickness of Silicon used.

Sponsored/Consultancy Projects

(PI/co-PI/Investigator)

  • Optimization of Silicon Nitride for Application in Charge Trap Nanoelectronic Non-volatile Memories by Direct Characterization of Bulk Traps; DST, Government of India; 2008-2011; INR 39 lakhs. (PI).
  • Low temperature CMOS; Industrial Research and Consultancy Centre, IIT Bombay, 2007-2010; INR 10 lakhs (PI)
  • High-k/metal gate for logic and memory applications; Semiconductor Research Corporation (SRC), USA; 2007-2010; US$ 120K (Co-PI)
  • Indian Nanoelectronics Users Program; Ministry of Communication and Information Technology, Government of India; 2008-2012; INR 125M (Co-PI)
  • Nano Centre project; Ministry of Communication and Information Technology, Government of India; 2006-2010; INR 500M (Investigator)
  • Metal Nano Crystals for Nanocrystal Flash Memory Technologies, Semiconductor Research Corporation (SRC), USA; 2010-20112; US$ 150K (PI)
  • National Center for Photovoltaic Research and Education, Ministry of New and Renewable Energy, Government of India; 2010-2014; INR 480M (Investigator)
  • UMG Silicon solar cells, Northern Research Institute, Norut, Norway, 2011-2014; NOK 55K (PI)
  • Centre of Excellence in Nanoelectronics, phase II; Ministry of Communication and Information Technology, Government of India; 2012-2016; INR 830M (Co-PI)
  • Assessment of Silicon Wire Array Radial Junction Solar Cells by Simulations and Experiments, DST, Government of India; 2012-2013; INR 27.5 lakhs. (PI).

Courses Offered

  • CS212: Electronic Design
  • EE230: Analog Circuits Lab
  • EE005: Electronics Lab
  • EE672: Microelectronics Lab
  • EE661: Physical Electronics
  • EE101: Introduction to Electrical and Electronic Circuits
  • EE728: Growth and Characterization of Nanoelectronic Materials and Devices
  • EE669: VLSI Technology
  • EN703: Advanced Photovoltaics

Academic Background

  • B. Tech in Electronics and Communication Engineering from NIT Calicut, Kerala: 1993
  • M. Tech in Electrical Engineering with Specialization in Microelectronics from IIT Bombay: 1997
  • Dr. Ingenieur (summa-cum-laude) in Electrical Engineering from the Universitaet der Bundeswehr, Munich, Germany: 2002

Work Experience

  • February 2009 - : Associate Professor, Department of Electrical Engineering, IIT Bombay.
  • November 2006 - January 2009: Assistant Professor, Department of Electrical Engineering, IIT Bombay.
  • 2001-2006: R & D Engineer in Interuniversity Microelectronics Centre, Leuven, Belgium (IMEC).
  • October 1998-Januray 1999: Fall intern at the semiconductor division of Siemens AG, Perlach, Munich, Germany, (now Infineon Technologies) from October 1998 to January 1999.
  • 1994-1995: Deputy Engineer Bharat Electronics.

Contact Information

Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email : anilkg[AT]ee.iitb.ac.in
Phone (O) : +91 22 2576 7438
Phone (R) : +91 22 2576 8438
Facsimile (O): +91 22 2572 3707

Awards and Honours

  • Best poster award at the IIIrd International Conference on Advances in Energy Research (ICAER 2011), IIT Bombay, for the poster: “PULSED DC REACTIVE SPUTTER DEPOSITED ALUMINUM OXIDE FOR SURFACE PASSIVATION OF P-TYPE SILICON FOR SOLAR CELL APPLICATIONS” by Meenakshi Bhaisare, Gaudhaman Jeevanandam and Anil Kottantharayil.
  • Best paper award at the ESSDERC 2005 held at Grenoble, France for the paper: “Minimization of the MuGFET Contact Resistance by Integration of NiSi Contacts on Epitaxially Raised Source/Drain Regions” by A. Dixit, K. G. Anil, R. Rooyackers, F. Leys, M. Kaiser, R. Weemaes, I. Ferain, A. De Keersgieter, N. Collaert, R. Surdeanu, M. Goodwin, P. Zimmerman, R. Loo, M. Caymax, M. Jurczak, S. Biesemans, and K. De Meyer.
  • Siemens AG doctoral research fellowship from July 1997 to September 2001 under the Siemens “Youth and Knowledge” program.

Other Professional Activities

  • Senior Member of IEEE since 2008 and member since 1997
  • Member of the Materials Research Society
  • Publicity Chair and member of program committee, International Workshop on Physics of Semiconductor Devices (IWPSD) 2007, Mumbai, India
  • Organizing committee co-chair, 2nd INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY (IEDST 2009) June 1-2, 2009, Indian Institute of Technology Bombay, Mumbai, India.
  • Poster committee chair of International Conference on Nano science and Technology (ICONSAT-2010), February 17 - 20, 2010, Indian Institute of Technology Bombay, Mumbai, India.
  • Reviewer for the following journals:
    • IEEE Transactions on Electron Devices
    • IEEE Electron Device Letters
    • IEEE Transactions on Nanotechnology
    • Applied Physics Letters
    • Progress in Photovoltaics: Research and Applications
    • Journal of Applied Physics

Patents

  1. A system for extracting water from air for drinking and cleaning purposes and a method thereof (2011), Jim John, Mehul Rawal, Chetan Singh Solanki, Anil Kottantharayil, Indian patent filed, Application number 2408/MUM/2011. PTC filing PCT/1N2011/000701 on 10th Oct 2011.
  2. Method for doping a fin-based semiconductor device, (2008) Kottantharayil, Anil, EP1916717, Patent record available from the European Patent Office, http://v3.espacenet.com/textdoc?DB=EPODOC&IDX=EP1916717&F=0
  3. Method for doping a fin-based semiconductor device, (2008) Kottantharayil, Anil, EP1892765, Patent record available from the European Patent Office http://v3.espacenet.com/textdoc?DB=EPODOC&IDX=EP1892765&F=0
  4. Method for doping fin-based semiconductor device, (2008) Kottantharayil, Anil, JP2008053725, Patent record available from the Japanese Patent Office, http://v3.espacenet.com/textdoc?DB=EPODOC&IDX=JP2008053725&F=0
  5. Method for doping a fin-based semiconductor device, (2008) Kottantharayil, Anil, US20080050897, Patent record available from the US Patent Office, http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=0&p=1&f=S&l=50&d=PG01&Query=20080050897
  6. Formation method for fully silicided gate MOSFET and device obtained by the same method, (2007) Kittl Jorge Adrian, Lauwers Anne, Veloso Anabela, Kottantharayil Anil, Van Dal Marcus Johannes Henric, JP2007027727, Patent record available from the Japanese Patent Office, http://v3.espacenet.com/textdoc?DB=EPODOC&IDX=JP2007027727&F=0
  7. Method of forming dual fully silicided gate and device obtained by the method, (2006) Kittl Jorge Adrian, Lauwers Anne, Veloso Anabela, Kottantharayil Anil, Van Dal Marcus Johannes Henric, JP2006324627, Patent record available from the Japanese Patent Office, http://v3.espacenet.com/textdoc?DB=EPODOC&IDX=JP2006324627&F=0
  8. Method for Forming Dual Fully Silicided Gates and Devices with Dual Fully Silicided Gates, (2006) Kittl, Jorge Adrian, Lauwers, Anne, Veloso, Anabela, Kottantharayil, Anil, van Dal, Marcus Johannes Henricus, US20060263961, Patent record available from the US Patent Office, http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=0&p=1&f=S&l=50&d=PG01&Query=20060263961
  9. Multiple gate semiconductor device and method for forming same, (2005) Kottantharayil, Anil, EP1519420, Patent record available from the European Patent Office, http://v3.espacenet.com/textdoc?DB=EPODOC&IDX=EP1519420&F=0
  10. Multilayer gate semiconductor device and manufacturing method therefore, (2005) Kottantharayil Anil, Loo Roger, JP2005051241, Patent record available from the Japanese Patent Office, http://v3.espacenet.com/textdoc?DB=EPODOC&IDX=JP2005051241&F=0
  11. Multiple gate semiconductor device and method for forming same (2005) Kottantharayil, Anil, Loo, Roger, US20050093154, Patent record available from the US Patent Office, http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=0&p=1&f=S&l=50&d=PG01&Query=20050093154

List of Publications

H-index = 14 (Scopus/Google scholar)
Relative h-index = 1.07

Journal Publications

  1. Kaesen, F., Fink, C., Anil, K.G., Hansch, W., Doll, T., Grabolla, T., Schreiber, H., Eisele, I., Optimization of the channel doping profile of vertical sub-100 nm MOSFETs, (1998) Thin Solid Films, 336 (1-2), pp. 309-312.
  2. Stadler, A., Sulima, T., Schulze, J., Fink, C., Kottantharayil, A., Hansch, W., Baumgärtner, H., Eisele, I., Lerch, W., Dopant diffusion during rapid thermal oxidation, (2000) Solid-State Electronics, 44 (5), pp. 831-835.
  3. Fink, C., Anil, K.G., Geiger, H., Hansch, W., Schulze, J., Sulima, T., Eisele, I., Optimization of breakdown behaviour and short channel effects in MBE-grown vertical MOS-devices with local channel doping, (2000) Thin Solid Films, 369 (1), pp. 383-386.
  4. Fink, C., Anil, K.G., Hansch, W., Sedlmaier, S., Schulze, J., Eisele, I., MBE-grown vertical power-MOSFETs with 100-nm channel length, (2000) Thin Solid Films, 380 (1-2), pp. 207-210.
  5. Anil, K.G., Eisele, I., Mahapatra, S., Observation of double peak in the substrate current versus gate voltage characteristics of n-channel metal-oxide-semiconductor field effect transistors, (2001) Applied Physics Letters, 78 (15), pp. 2238-2240.
  6. K. G. Anil, S. Mahapatra, V. Ramgopal Rao and I. Eisele, Comparison of Sub- Bandgap Impact Ionization in Deep-Sub-Micron Conventional and Lateral Asymmetrical Channel nMOSFETs, Japanese Journal of Applied Physics, vol. 40, Part 1, No. 4B, pp. 2621-2626, April 2001.
  7. Anil, K.G., Mahapatra, S., Eisele, I., Experimental verification of the nature of the high energy tail in the electron energy distribution in n-channel MOSFETs, (2001) IEEE Electron Device Letters, 22 (10), pp. 478-480.
  8. Fink, C., Anil, K.G., Geiger, H., Hansch, W., Kaesen, F., Schulze, J., Sulima, T., Eisele, I., Enhancement of device performance in vertical sub-100 nm MOS devices due to local channel doping, (2002) Solid-State Electronics, 46 (3), pp. 387-391.
  9. Anil, K.G., Mahapatra, S., Eisele, I., Electron-electron interaction signature peak in the substrate current versus gate voltage characteristics of n-channel silicon MOSFETs, (2002) IEEE Transactions on Electron Devices, 49 (7), pp. 1283-1288.
  10. Anil, K.G., Mahapatra, S., Eisele, I., A detailed experimental investigation of impact ionization in n-channel metal-oxide-semiconductor field-effect-transistors at very low drain voltages, (2003) Solid-State Electronics, 47 (6), pp. 995-1001.
  11. Collaert, N., Dixit, A., Goodwin, M., Anil, K.G., Rooyackers, R., Degroote, B., Leunissen, L.H.A., Veloso, A., Jonckheere, R., De Meyer, K., Jurczak, M., Biesemans, S., A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node, (2004) IEEE Electron Device Letters, 25 (8), pp. 568-570.
  12. Dixit, A., Kottantharayil, A., Collaert, N., Goodwin, M., Jurczak, M., De Meyer, K., Analysis of the parasitic S/D resistance in multiple-gate FETs, (2005) IEEE Transactions on Electron Devices, 52 (6), pp. 1132-1140.
  13. Collaert, N., De Keersgieter, A., Anil, K.G., Rooyackers, R., Eneman, G., Goodwin, M., Eyckens, B., Sleeckx, E., de Marneffe, J.-F., De Meyer, K., Absil, P., Jurczak, M., Biesemans, S., Performance improvement of tall triple gate devices with strained SiN layers, (2005) IEEE Electron Device Letters, 26 (11), pp. 820-822.
  14. Janssens, T., Pawlak, M.A., Kittl, J.A., Fouchier, M., Lauwers, A., Kottantharayil, A., Vandervorst, W., Dopant profiling in Nix Si1-X gates with secondary-ion-mass spectroscopy, (2006) Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 24 (1), pp. 399-403.
  15. Kittl, J.A., Pawlak, M.A., Lauwers, A., Demeurisse, C., Opsomer, K., Anil, K.G., Vrancken, C., van Dal, M.J.H., Veloso, A., Kubicek, S., Absil, P., Maex, K., Biesemans, S., Work function of Ni silicide phases on HfSiON and SiO2: NiSi, Ni2Si, Ni31Si12, and Ni3Si fully silicided gates, (2006) IEEE Electron Device Letters, 27 (1), pp. 34-36.
  16. Pawlak, M.A., Lauwers, A., Janssens, T., Anil, K.G., Opsomer, K., Maex, K., Vantomme, A., Kittl, J.A., Modulation of the workfunction of Ni fully silicided gates by doping: Dielectric and silicide phase effects, (2006) IEEE Electron Device Letters, 27 (2), pp. 99-101.
  17. Dixit, A., Anil, K.G., Rooyackers, R., Leys, F., Kaiser, M., Collaert, N., De Meyer, K., Jurczak, M., Biesemans, S., Minimization of specific contact resistance in multiple gate NFETs by selective epitaxial growth of Si in the HDD regions, (2006) Solid-State Electronics, 50 (4), pp. 587-593.
  18. Singanamalla, R., Yu, H.Y., Pourtois, G., Ferain, I., Anil, K.G., Kubicek, S., Hoffmann, T.Y., Jurczak, M., Biesemans, S., De Meyer, K., On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO2 and Poly-Si/TiN/HfSiON gate stacks, (2006) IEEE Electron Device Letters, 27 (5), pp. 332-334.
  19. Dixit, A., Anil, K.G., Collaert, N., Zimmerman, P., Jurczak, M., De Meyer, K., Minimization of MuGFET source/drain resistance using wrap-around NiSi-HDD contacts, (2006) Solid-State Electronics, 50 (7-8), pp. 1466-1471.
  20. Kittl, J.A., Pawlak, M.A., Lauwers, A., Demeurisse, C., Hoffmann, T., Veloso, A., Anil, K.G., Kubicek, S., Niwa, M., van Dal, M.J.H., Richard, O., Jurczak, M., Vrancken, C., Chiarella, T., Brus, S., Maex, K., Biesemans, S., Phase effects and short gate length device implementation of Ni fully silicided (FUSI) gates (2006) Microelectronic Engineering, 83 (11-12), pp. 2117-2121.
  21. Iyengar, V.V., Kottantharayil, A., Tranjan, F.M., Jurczak, M., De Meyer, K., Extraction of the top and sidewall mobility in FinFETs and the impact of fin-patterning processes and gate dielectrics on mobility, (2007) IEEE Transactions on Electron Devices, 54 (5), pp. 1177-1184.
  22. Ferain, I., Pantisano, L., Kottantharayil, A., Petry, J., Trojman, L., Collaert, N., Jurczak, M., De Meyer, K., Reduction of the anomalous VT behavior in MOSFETs with high-κ/metal gate stacks, (2007) Microelectronic Engineering, 84 (9-10), pp. 1882-1885.
  23. Thakker, R.A., Patil, M.B., Anil, K.G., Parameter extraction for PSP MOSFET model using hierarchical particle swarm optimization, (2009) Engineering Applications of Artificial Intelligence, 22 (2), pp. 317-328.
  24. Walawalkar, M.G., Kottantharayil, A., Rao, V.R., Chemical Vapor Deposition Precursors for High Dielectric Oxides: Zirconium and Hafnium Oxide, (2009) Synthesis and Reactivity in Inorganic, Metal-Organic and Nano-Metal Chemistry, 39 (6), pp. 331-340.
  25. Hasanali G. Virani, Rama Bhadra Rao and Anil Kottantharayil, Investigation of Novel Si/SiGe Hetero Structures and Gate Induced Source Tunneling for Improvement of P-channel Tunnel FETs, (2010) Japanese Journal of Applied Physics, 49, 04DC12. http://dx.doi.org/10.1143/JJAP.49.04DC12
  26. Hasanali G. Virani, Adari Rama Bhadra Rao and Anil Kottantharayil, Dual-k Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs, (2010) IEEE Transactions on Electron Devices, 57 (10), pp. 2410-2417. http://dx.doi.org/10.1109/TED.2010.2057195
  27. Suresh Gundapaneni, Swaroop Ganguly and Anil Kottantharayil, Bulk Planar Junction-Less Transistor (BPJLT): An attractive device alternative for scaling, (2011) IEEE Electron Device Letters, 32 (3), pp. 261-263. http://dx.doi.org/10.1109/LED.2010.2099204
  28. Hasanali G. Virani, Suresh Gundapaneni and Anil Kottantharayil, Double Dielectric Spacer for the Enhancement of Silicon p-Channel Tunnel FET Performance, (2011) Japanese Journal of Applied Physics, 50, 04DC04, http://dx.doi.org/10.1143/JJAP.50.04DC04.
  29. Suresh Gundapaneni, Swaroop Ganguly and Anil Kottantharayil, Enhanced electrostatic integrity of short channel junctionless transistor with high-κ spacers, (2011) IEEE Electron Device Letters, 32 (10), pp. 1325-1327. http://dx.doi.org/10.1109/LED.2011.2162309.
  30. Suresh Gundapaneni, Mohit Bajaj, Rajan K. Pandey, Kota V. R. M. Murali, Swaroop Ganguly and Anil Kottantharayil, Effect of Band-to-Band Tunneling on Junctionless Transistors, (2012) IEEE Transactions on Electron Devices, 59 (4), pp. 1023 - 1029. http://dx.doi.org/10.1109/TED.2012.2185800.
  31. Meenakshi Bhaisare, Abhishek Misra, Mayur Waikar and Anil Kottantharayil, High quality Al2O3 dielectric films deposited by pulsed- DC reactive sputtering technique for high-k applications, accepted for publication in Nanoscience and Nanotechnology Letters.

Conference proceedings/presentations

  1. K. G. Anil, J. M. Vasi and R. K. Lal, “Low Dose Radiation Sensor for Medical Therapy Applications”, Proceedings of the Ninth International Workshop on Physics of Semiconductor Devices, New Delhi, India, December 1997, pages 1145-1148.
  2. W. Hansch, K. Anil, P. Bieringer, C. Fink, F. Kaesen, I. Eisele, M. Tanaka and M. Miura-Mattausch, “Channel Engineering for the Reduction of Random-Dopant Placement-Induced Threshold Voltage Fluctuations in Vertical sub-100nm MOSFETs”, Proceedings of the 29th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium, September 1999, pages 408-411.
  3. Anil, K.G., Mahapatra, S., Eisele, I., Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETs, (2000) Technical Digest - International Electron Devices Meeting, pp. 675-678.
  4. K. G. Anil, S. Mahapatra, V. Ramgopal Rao and I. Eisele, Comparison of Sub- Bandgap Impact Ionization in Deep-Sub-Micron Conventional and Lateral Asymmetrical Channel nMOSFETs”, in Proceedings of the International Conference on Solid State Devices and Materials (SSDM) 2000, Sendai, Japan, 29-31 August 2000, pp. 60-61.
  5. K. G. Anil, S. Mahapatra, I. Eisele, V. R. Rao, J. Vasi, “Drain Bias Dependence of Gate Oxide Reliability in Conventional and Asymmetrical Channel MOSFETs in the Low Voltage Regime”, in Proceedings of the 30th European Solid-State Device Research Conference (ESSDERC), Cork, Ireland, 11-13 September 2000, pp. 132-135.
  6. K. G. Anil, T. Pompl, I. Eisele, Impact of Gate Oxide Thickness Scaling on Hot- Carrier Degradation in Deep-sub-micron nMOSFETs”, in Proceedings of the 30th European Solid-State Device Research Conference (ESSDERC), Cork, Ireland, 11-13 September 2000, pp. 124-127.
  7. Shrivastav, G., Mahapatra, S., Ramgopal Rao, V., Vasi, J., Anil, K.G., Fink, C., Hansch, W., Eisele, I., Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering, (2001) Proceedings of the IEEE International Conference on VLSI Design, pp. 475-478.
  8. Anil, K.G., Henson, K., Biesemans, S., Collaert, N., Layout density analysis of FinFETs, (2003) Proceedings of the European Solid-State Device Research Conference, 16-18 Sept. 2003 Page(s):139 – 142.
  9. Anil, K.G., Veloso, A., Kubicek, S., Schram, T., Augendre, E., De Marneffe, J.-F., Devriendt, K., Lauwers, A., Brus, S., Henson, K., Biesemans, S., Demonstration of fully Ni-silicided metal gates on HfO2 based high-k gate dielectrics as a candidate for low power applications, (2004) Digest of Technical Papers - Symposium on VLSI Technology, pp. 190-191.
  10. Kittl, J.A., Lauwers, A., Chamirian, O., Pawlak, M.A., Van Dal, M., Akheyar, A., De Potter, M., Kottantharayil, A., Pourtois, G., Lindsay, R., Maex, K., Applications of Ni-based silicides to 45 nm CMOS and beyond, (2004) Materials Research Society Symposium - Proceedings, 810, pp. 31-42.
  11. Veloso, A., Anil, K.G., Witters, L., Brus, S., Kubicek, S., De Marneffe, J.-F., Sijmus, B., Devriendt, K., Lauwers, A., Kauerauf, T., Jurczak, M., Biesemans, S., Work function engineering by FUSI and its impact on the performance and reliability of oxynitride and Hf-silicate based MOSFETs, (2004) Technical Digest - International Electron Devices Meeting, IEDM, pp. 855-858.
  12. Severi, S., Anil, K.G., Pawlak, J.B., Duffy, R., Henson, K., Lindsay, R., Lauwers, A., Veloso, A., De Marneffe, J.F., Ramos, J., Camillo-Castillo, R.A., Eyben, P., Dachs, C., Vandervost, W., Jurczak, M., Biesemans, S., De Meyer, K., Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices, (2004) Technical Digest - International Electron Devices Meeting, IEDM, pp. 99-102.
  13. Collaert, N., Dixit, A., Anil, K.G., Rooyackers, R., Veloso, A., De Meyer, K. Shift and ratio method revisited: Extraction of the fin width in multi-gate devices (2005) Solid-State Electronics, 49 (5), pp. 763-768.
  14. Subramanian, V., Mercha, A., Dixit, A., Anil, K.G., Jurczak, M., De Meyer, K., Decoutere, S., Maes, H., Groeseneken, G., Sansen, W., Geometry dependence of 1/f noise in n- and p-channel MuGFETs, (2005) AIP Conference Proceedings, 780, pp. 279-282.
  15. Kubicek, S., Veloso, A., Anil, K.G., Hayashi, S., Yamamoto, K., Mitsuhashi, R., Kittl, A., Lauwers, M., Van Dal, S., Horii, Harada, Y., Kubota, M., Niwa, M., De Gendt, S., Heyns, M., Jurczak, M., Biesemans, S., Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS (2005) 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers, art. no. T63, pp. 99-100.
  16. Henson, K., Collaert, N., Demand, M., Goodwin, M., Brus, S., Rooyackers, R., Van Ammel, A., Degroote, B., Ercken, M., Baerts, C., Anil, K.G., Dixit, A., Beckx, S., Schram, T., Deweerd, W., Boullart, W., Schaekers, M., De Gendt, S., De Meyer, K., Yim, Y., Hooker, J.C., Jurczak, M., Biesemans, S., NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics (2005) 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers, art. no. T87, pp. 136-137.
  17. Dixit, A., Anil, K.G., Mercha, A., Collaert, R., Brus, S., Richard, O., Rooyackers, R., Goodwin, M., Jurczak, M., De Meyer, K., Towards optimally shaped fins in p-channel tri-gate FETs: Can fin height be reduced further? (2005) 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers, art. no. T73, pp. 112-113.
  18. Dixit, A., Anil, K.G., Collaert, N., Rooyackers, R., Leys, F., Ferain, I., De Keersgieter, A., Hoffmann, T.Y., Loo, R., Goodwin, M., Zimmerman, P., Caymax, M., De Meyer, K., Jurczak, M., Biesemans, S., Parasitic source/drain resistance reduction in N-channel SOI MuGFETs with 15nm wide fins, (2005) Proceedings - IEEE International SOI Conference, 2005, art. no. 1563597, p. 226.
  19. Dixit, A., Anil, K.G., Rooyackers, R., Leys, F., Kaiser, M., Weemaes, R., Ferain, I., De Keersgieter, A., Collaert, N., Surdeanu, R., Goodwin, M., Zimmerman, P., Loo, R., Caymax, M., Jurczak, M., Biesemans, S., De Meyer, K., Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions, (2005) Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference, 2005, art. no. 1546680, pp. 445-448.
  20. Lauwers, A., Veloso, A., Hoffmann, T., Van Dal, M.J.H., Vrancken, C., Brus, S., Locorotondo, S., De Marneffe, J.-F., Sijmus, B., Kubicek, S., Chiarella, T., Pawlak, M.A., Opsomer, K., Niwa, M., Mitsuhashi, R., Anil, K.G., Yu, H.Y., Demeurisse, C., Verbeeck, R., De Potter, M., Absil, P., Maex, K., Jurczak, M., Biesemans, S., Kittl, J.A., CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON, (2005) Technical Digest - International Electron Devices Meeting, IEDM, 2005, art. no. 1609433, pp. 646-649.
  21. Anil, K.G., Verheyen, P., Collaert, N., Dixit, A., Kaczer, B., Snow, J., Vos, R., Locorotondo, S., Degroote, B., Shi, X., Rooyackers, R., Mannaert, G., Brus, S., Yim, Y.S., Lauwers, A., Goodwin, M., Kittl, J.A., Van Dal, M., Richard, O., Veloso, A., Kubicek, S., Beckx, S., Boullart, W., De Meyer, K., Absil, P., Jurczak, M., Biesemans, S., CMP-less integration of Fully Ni-Silicided Metal Gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach (2005) Digest of Technical Papers - Symposium on VLSI Technology, 2005, art. no. 1469266, pp. 198-199.
  22. Pawlak, M.A., Kittl, J.A., Janssens, T., Lauwers, A., Vandervorst, W., Anil, K.G., Schram, T., Veloso, A., Van Dal, M.J.H., Maex, K., Vantomme, A., Influence of activation annealing and silicidation process on as redistribution and pile-up at the NixSiy/SiO2 interface (2005) Proceedings - Electrochemical Society, PV 2005-05, pp. 241-248.
  23. Kittl, J.A., Lauwers, A., Pawlak, M.A., Demeurisse, C., Anil, K.G., Veloso, A., Van Dal, M.J.H., Schram, T., Brijs, B., Kaiser, M., Kubicek, S., Cunniffe, J., Verbeeck, R., Vrancken, C., Biesemans, S., Maex, K., Materials issues of NI fully silicided (fusi) gates for CMOS applications, (2005) Proceedings - Electrochemical Society, PV 2005-05, pp. 225-232.
  24. Kittl, J.A., Lauwers, A., Pawlak, M.A., Van Dal, M.J.H., Veloso, A., Anil, K.G., Pourtois, G., Demeurisse, C., Schram, T., Brijs, B., De Potter, M., Vrancken, C., Maex, K., Ni fully silicided gates for 45 nm CMOS applications (2005) Microelectronic Engineering, 82 (3-4 SPEC. ISS.), pp. 441-448.
  25. Kittl, J.A., Lauwers, A., Van Dal, M.J.H., Demeurisse, C., Anil, K.G., Veloso, A., Pawlak, M.A., Cunniffe, J., Schram, T., Verbeeck, R., Vrancken, C., Kubicek, S., Maex, K., Materials Issues of Ni Fully Silicided (FUSI) gates for CMOS applications (2005) Meeting Abstracts, p. 633.
  26. Kittl, J.A., Veloso, A., Lauwers, A., Anil, K.G., Demeurisse, C., Kubicek, S., Niwa, M., Van Dal, M.J.H., Richard, O., Pawlak, M.A., Jurczak, M., Vrancken, C., Chiarella, T., Brus, S., Maex, K., Biesemans, S., Scalability of Ni FUSI gate processes: Phase and Vt control to 30 nm gate lengths (2005) Digest of Technical Papers - Symposium on VLSI Technology, 2005, art. no. 1469217, pp. 72-73.
  27. Hoffmann, T., Doornbos, G., Ferain, I., Collaert, N., Zimmerman, P., Goodwin, M., Rooyackers, R., Kottantharayil, A., Yim, Y., Dixit, A., De Meyer, K., Jurczak, M., Biesemans, S., GIDL (Gate-Induced Drain Leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO2/TiN FinFET devices, (2005) Technical Digest - International Electron Devices Meeting, IEDM, 2005, art. no. 1609455, pp. 725-728.
  28. Snow, J., Vos, R., Anil, K.G., Kraus, H., Xu, K., Grinninger, F., Wagner, G., FKovacs, Mertens, P.W., Selective etching of sige for removal of dummy layers in fully silicided gate architectures, (2005) ECS Transactions, 1 (3), pp. 207-213.
  29. Pawlak, M.A., Kittl, J.A., Janssens, T., Lauwers, A., Vandervorst, W., Anil, K.G., Schram, T., Veloso, A., Van Dal, M.J.H., Maex, K., Vantomme, A., Influence of activation annealing and silicidation process on dopant redistribution and pile-up at the NIx SIy/SIO2 interface, (2005) Meeting Abstracts, p. 635.
  30. Dixit, A., Anil, K.G., Baravelli, E., Roussel, P., Mercha, A., Gustin, C., Bamal, M., Grossar, E., Rooyackers, R., Augendre, E., Jurczak, M., Biesemans, S., De Meyer, K., Impact of stochastic mismatch on measured SRAM performance of FinFETs with resist/spacer-defined fins: Role of line-edge-roughness, (2006) Technical Digest - International Electron Devices Meeting, IEDM, art. no. 4154303.
  31. Lenoble, D., Anil, K.G., De Keersgieter, A., Eybens, P., Collaert, N., Rooyackers, R., Brus, S., Zimmerman, P., Goodwin, M., Vanhaeren, D., Vandervorst, W., Radovanov, S., Godet, L., Cardinaud, C., Biesemans, S., Skotnicki, T., Jurczak, M., Enhanced performance of PMOS MUGFET via integration of conformal plasma-doped source/drain extensions, (2006) Digest of Technical Papers - Symposium on VLSI Technology, art. no. 1705270, pp. 168-169.
  32. Jurczak, M., Collaert, N., Rooyackers, R., Kottantharayil, A., Dixit, A., Ferain, I., San, T., Son, N.-J., Lenoble, D., Zimmerman, P., De Keersgieter, A., Von Arnim, K., Ramos, J., Mercha, A., Verheyen, P., MUGFET - Alternative transistor architecture for 32 nm CMOS generation, (2006) Extended Abstracts of the Sixth International Workshop on Junction Technology, IWJT ‘06, art. no. 1669433, p. 1.
  33. Ramos, J., Augendre, E., Kottantharayil, A., Mercha, A., Simoen, E., Rosmeulen, M., Severi, S., Kerner, C., Chiarella, T., Nackaerts, A., Ferain, I., Hoffmann, T., Jurczak, M., Biesemans, S., Experimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of triple-gate FinFETs (2007) ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, art. no. 4098024, pp. 72-74.
  34. Thakker, R.A., Gandhi, N., Patil, M.B., Anil, K.G., Parameter extraction for PSP MOSFET model using particle swarm optimization (2007) Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD, art. no. 4472470, pp. 130-133.
  35. Chopde, A.M., Khandelwal, S., Thakker, R.A., Patil, M.B., Anil, K.G., Parameter extraction for MOS model 11 using particle swarm optimization, (2007) Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD, art. no. 4472494, pp. 253-256.
  36. Thakker, R.A., Patil, M.B., Anil, K.G., Parameter extraction for advanced MOSFET model using particle swarm optimization, (2008) Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, NSTI-Nanotech, Nanotechnology 2008, 3, pp. 845-848.
  37. Nikam, V., Bhuwalka, K.K., Kottantharayil, A., Optimization of n-channel tunnel FET for the sub-22nm gate length regime, (2008) Device Research Conference - Conference Digest, DRC, art. no. 4800742, pp. 77-78.
  38. Hasanali G. Virani, Rama Bhadra Rao and Anil Kottantharayil, “Optimization of P-channel Tunnel FETs using High k spacers”, presented at the 15th International Workshop on the Physics of Semiconductor Devices (IWPSD 2009), Delhi, India.
  39. Hasanali G. Virani, Rama Bhadra Rao, Vishwanath Nikam and Anil Kottantharayil, “Investigation of Novel Si/SiGe Hetero Structures and Gate Induced Source Tunneling for Improvement of P-channel Tunnel FETs”, presented at the 41st Solid State Device Meeting (SSDM-2009), Sendai, Japan.
  40. Hasanali G. Virani and Anil Kottantharayil, “Optimization of Hetero Junction n-channel Tunnel FET with High-k Spacers”, presented at the 2nd INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY (IEDST 2009), Mumbai, India. The article is available on-line at http://dx.doi.org/10.1109/EDST.2009.5166113
  41. Hasanali Virani, David Esseni and Anil Kottantharayil, “Impact of electron velocity on the ION of n-TFETs”, Proceedings of the 40th European Solid State Device Research Conference (ESSDERC) 2010, pp. 349.
  42. Hasanali Virani, Suresh Gundapaneni and Anil Kottantharayil, “Optimization of Silicon ρ-channel Tunnel FET with Dual κ Spacer”, presented at the 42nd Solid State Device Meeting (SSDM-2010), Tokyo, Japan in September 2010.
  43. Abhishek Misra, Sunny Sadana, Satya Suresh, Meenakshi Bhaisare, Senthil Srinivasan, Mayur Waikar, Amit Gaur and Anil Kottantharayil, “Effect of different substrate materials on the Pt Nanocrystal formation statistics (size, density area coverage and circularity) for flash memory application”, presented at the MRS Fall Meeting 2010, Boston in November-December 2010, Proceedings of the MRS Fall meeting 2010, pp. 1288.
  44. Meenakshi Bhaisare, Abhishek Misra, Mayur Waikar and Anil Kottantharayil, “High quality Al2O3 dielectric films deposited by pulsed- DC reactive sputtering technique for high-k applications”, presented at ICMAT 2011, Singapore in June- July 2011
  45. Kousik Midya, Abhishek Sharma, Anil Kottantharayil, Subhabrata Dhar, “RF sputtered ITO thin film with improved optical property”, accepted for presentation at MRS Spring Meeting 2012, San Francisco, USA.
  46. Abhishek Mishra, Mayur Waikar, Amit Gour, Hemen Kalita, Meenakshi Bhaisare, Mohammed Aslam and Anil Kottantharayil, “Large Memory Window Floating Gate Flash Memory with Multilayer Graphene as Charge Storage Layer”, accepted for presentation at the International Memory Workshop 2012, Milano, Italy.
  47. Sandeep S. S., Ketan Warikoo, Anil Kottantharayil, “Optimization of ICP-CVD Silicon Nitride for Si Solar Cell Passivation”, accepted for presentation at the 38th IEEE Photovoltaic Specialist Conference 2012, Austin, USA. 






Books/Chapters in Books




    

  1.  J. Kittl, A. Lauwers, O. Chamirian, M. Kmieciak, M. van Dal, A. Veloso, A. Kottantharayil, G. Pourtois, M. de Potter de ten Broeck, K. Maex, “Silicides - Recent advances and prospects” chapter in Materials for Information Technology: Devices, Interconnects and Packaging edited by Ehrenfried Zschech, Caroline Whelan and Thomas Mikolajick, Springer Verlag, 2005.
    

    2. 







    
  


  
 


  
  


    

      

              

      

        Last modified: 2012/04/30 10:37      

    


   
    

      

        
      

      

                
         
      

    

 










  Valid XHTML 1.0


  Driven by DokuWiki